CN1529476A - Ethernet and ATM tier joined data vonversion and correction device and method - Google Patents
Ethernet and ATM tier joined data vonversion and correction device and method Download PDFInfo
- Publication number
- CN1529476A CN1529476A CNA2003101118924A CN200310111892A CN1529476A CN 1529476 A CN1529476 A CN 1529476A CN A2003101118924 A CNA2003101118924 A CN A2003101118924A CN 200310111892 A CN200310111892 A CN 200310111892A CN 1529476 A CN1529476 A CN 1529476A
- Authority
- CN
- China
- Prior art keywords
- ethernet
- atm
- data
- module
- crc
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Abstract
The devices comprises sending module at same Ethernet from Ethernet to ATM layer, sending module for CRC generation, ATM sending module and ATM receiving module from ATM layer to Ethernet direction, receiving module for CRC checking, Ethernet receiving module as well as sending and receiving storage module at ATM side, and sending and storage module at Ethernet side. The said above devices implement conversion and verification of jointed data between Ethernet and ATM. The invention realizes bus conversion between Ethernet and ATM, and CRC calculation without need of resources of network processor. RAM look-up table is utilized in CRC calculation module so as to save lot of logic resources, and reduce system cost.
Description
Technical field
The present invention relates to digital communication technology, in particular, be a kind ofly to be used for realizing that ATM (AsynchronousTransfer Mode, asynchronous transfer mode) layer is to Ethernet butt joint, the device and the processing method of line data CRC (CRC) verification of going forward side by side.
Background technology
Ethernet is baseband LAN (local area network (LAN)) standard of Xerox company invention.It adopts csma/cd agreement (CSMA/CD), and transmission medium is a coaxial cable, along with the high speed development of mechanics of communication, is used more and more widely in every field.Ethernet insert to adopt the asynchronous working mode, is suitable for the process IP bursty traffic, development so far, existing important change of technology and breakthrough (LAN exchange, star wiring, big capacity MAC Address storage and managerial etc.).ATM is the standard that a kind of ITU-T of International Telecommunications Union formulates, and in this pattern, information is organized into cell, and because of each cell that comprises from certain user profile does not need periodically to occur, this transmission mode is asynchronous.Because both standard differences, when data are need be between Ethernet and ATM mutual, just need change data form and control signal corresponding etc.
Mainly containing number of patent application with the relevant patent of Ethernet, the butt joint of ATM layer at present is 6,414,966 United States Patent (USP) " Bridging device for mapping/demapping ethernet packet datadirectly onto and from a sonet network " is promptly set up, is split the Ethernet data bag and is connected to the bridging device of SONET (multichannel Synchronous Optical Network).
The major function of above-mentioned patent comprises data width, control signal and sequential requirement etc. for to finish the conversion of ethernet processor interface to Utopia Level 2P (Fr-UTOPIA) interface.As long as equipment comprises ethernet control module, memory module, UTOPIA (adopting the universal test and the operating physical layer interface of ATM(Asynchronous Transfer Mode)) interface module, cpu i/f module, work as Ethernet side/UTOPIA side joint in the handling process and harvest complete data, give the opposite side control module control again, again control is returned after this side disposes equally.
Above-mentioned patent is not carried out the CRC16 verification to ATM cell simultaneously and is calculated except that the data communication that realizes ATM layer and Ethernet in the transmission data procedures.Two transmission direction can not concurrent working from the ATM layer to Ethernet and from Ethernet to the ATM layer, is confined to have only a processing module to work, and treatment effeciency is not high.
Summary of the invention
The object of the present invention is to provide a kind of new Ethernet and ATM layer Interworking Data conversion calibration equipment, and the method for Ethernet to transmission of ATM layer data and verification that realize is provided on this basis.The present invention provides the network processing unit dedicated bus to the translation interface between the atm standard bus according to system requirements, carries out CRC check simultaneously and calculates carrying out interface conversion, reduces the workload of upper layer software (applications), improves systematic function.
Ethernet among the present invention and ATM layer Interworking Data conversion calibration equipment, comprise: the ether from Ethernet to ATM layer direction is with net sending module, transmission CRC generation module, ATM sending module and the ATM receiver module from the ATM layer to the Ethernet direction, reception CRC check module, Ethernet receiver module, and the ATM side sends, receives memory module and the Ethernet side sends, memory module;
Described Ethernet sending module is used for carrying out data communication with the dedicated bus of the network processing unit of Ethernet side, comprises the control of packet transmit status, and other signal of bus generates and sequential adjustment;
Described transmission CRC generation module is used for that whole packet is carried out CRC and calculates, and adds result of calculation to the packet end;
Described ATM sending module is used for communicating with the ATM physical layer, sends the packet of subsidiary CRC result of calculation;
Described ATM receiver module, reception CRC check module, Ethernet receiver module are finished corresponding function in the opposite direction of data flow;
Described ATM side sends, receives memory module and the Ethernet side sends, memory module, is used for buffer memory ATM cell relevant information;
At described CRC generation module (103) with receive and to have deposited CRC among the RAM of chip of CRC check module (107) and calculate corresponding form.The corresponding computation sheet of CRC has two of address and data.
When having two or more passages to transmit data, can be on the basis of said apparatus, increase the transmit port arbitration modules from Ethernet to ATM layer direction, increasing the receiving port arbitration modules from the ATM layer to the Ethernet direction, be used for the mean allocation Export resource.
Said apparatus of the present invention adopts multi-clock zone.Have three clocks in this device, two is the clock of outside two kinds of buses, and one is inner phase-locked loop clock.The external bus interface clock is that this device directly uses by the outside device input of this device.The module of every Ethernet side is all used Ethernet side external bus interface clock in the invention, and ATM side form piece all uses ATM side external bus interface clock; Installing inner phase-locked loop is the additional function that the device inside chip self is had, and the inner certain methods that adopts of device is called, and produces this frequency doubling clock voluntarily, only uses for the CRC module of both transmit and receive direction.That is: the work clock of CRC generation, verification module is selected the frequency doubling clock of device inside chip phase-locked loop output for use, Ethernet sends, receiver module adopts Ethernet side external bus interface clock, and ATM sends, receiver module adopts ATM side external bus interface clock.
Realize the method for Ethernet among the present invention, may further comprise the steps to transmission of ATM layer data and verification:
From the Ethernet side to the ATM layer:
A. the network processing unit of Ethernet is when the ATM layer sends packet, checkout gear corresponding ports state, and this port reports useful signal, and network processing unit sends packet;
B. Ethernet side sending module deposits the 32bit width data in this side storage FIFO;
C. detect among the Ethernet transmitter side storage FIFO and remain to be sent out packet, and judge that the ATM side sends storage FIFO and still has living space, then move transmitter side CRC generation module, the sense data bag, carry out 32bit and calculate, deposit ATM side FIFO in to 8bit bit width conversion and CRC;
D. detect among the ATM side FIFO and remain to be given out a contract for a project, this device continues to detect the PHY chip port state of ATM layer, if port is effective, starts ATM side sending module, sends after the 8bit width data is converted to 16bit, and is invalid if port detects, and continues to wait for;
From the ATM layer to Ethernet:
The E.ATM layer has packets need to send the ethernet network processor to, and corresponding port reported data is surrounded by the effect signal;
F. detect ATM receiver side fifo status, if still have living space, start receiver module, deposit FIFO successively in after the 16bit width data is converted to 8bit;
G. detect among the ATM reception FIFO packet is arranged, detecting Ethernet side joint receipts FIFO simultaneously still has living space, then operation receives the CRC check module, packet is carried out CRC to be calculated, and compare with the CRC byte that receives, judge in the transmission course whether make mistakes, the 8bit width is converted to deposits the Ethernet side joint behind the 32bit width in and receive FIFO;
H. the report network processor has packets need to receive, detect effective received signal after, start Ethernet receiver module (106), read data among the FIFO, give network processing unit.
Data carried out CRC calculate among above-mentioned steps C and the step G, be meant that the packet content that will read in the FIFO tables look-up as the address through after some specific calculation, just give RAM this address, provide other corresponding control signal then, RAM will export corresponding data, just obtains the CRC result calculated after these data being handled again.
If have two or more passages need transmit data simultaneously, then start transmit port arbitration modules and receiving port arbitration modules, make each passage take bus on an equal basis.
Beneficial effect:
Apparatus and method of the present invention have been adopted, compared with prior art, can realize that not only Ethernet changes to the bus between the ATM, the CRC that can also finish data synchronously calculates, do not need to take again the resource of network processing unit, reduce the network processing unit workload, improve systematic function greatly, test the performance requirement that four ports can satisfy each port line-speed fully at present.The present invention simultaneously adopts RAM storage lookup table mode in the CRC computing module, save a large amount of logical resources, reduces system cost.
Description of drawings
Fig. 1 is Ethernet and ATM Interworking Data conversion calibration mode block structure schematic diagram.
Fig. 2 is an Ethernet sending module workflow diagram.
Fig. 3 sends CRC generation module workflow diagram.
Fig. 4 is an ATM side sending module workflow diagram.
Embodiment
Further the present invention is described in detail below in conjunction with accompanying drawing.
As shown in Figure 1, one embodiment of the present of invention structure comprises following components altogether:
102 Ethernet sending modules, mainly the search request according to network processing unit reports the port ready message, and the packet of real-time testbus, transmit status machine (part of sending module) is triggered in beginning flag position with packet, the data of bus are buffered into corresponding stored FIFO by 32 bit widths, simultaneously initial, the end mark position of data cached bag.
103 send the CRC generation module, detect data cached bag among the Ethernet transmitter side FIFO, the FIFO of ATM side transmission does not simultaneously fill up, start CRC and generate state machine, the data of 32 bit widths are read from Ethernet transmission FIFO, handle because CRC calculates by byte, per four clock cycle of Ethernet side enable FIFO one time, and each cycle of ATM side all is pressed into a byte, and it is last that CRC result of calculation is embedded in packet, carries out the correctness verification for the packet recipient.
The 104ATM sending module sends existing data cached bag among the FIFO when detecting the ATM side, and the transmit port arbitration modules judges that this port is effective simultaneously, then starts ATM side transmit status machine, and sense data from FIFO is sent behind the processing data width.
105 transmit port arbitration modules, 109 receiving port arbitration modules have four ports to work simultaneously among the present invention, and in the shared cover outlet bus of ATM side, these two module functions are exactly the mean allocation Export resource, guarantee that the data of each passage are unimpeded.
The 108ATM receiver module when detecting the ATM layer and have packet to be transmitted, detects ATM receiver side FIFO, if also have memory space, enable ATM accepting state machine (part of receiver module), start one time receiving course, deposit FIFO in after 16 bit wide data are converted to 8 bit wides in proper order by high low level.
107 receive the CRC check module, detect among the ATM receiver side FIFO packet to be passed is arranged, and the Ethernet receiver side FIFO store data bag that still has living space starts the CRC check state machine, enables ATM and receives FIFO, the sense data bag, carry out CRC by byte and calculate, then 8 bit data are converted to and deposit Ethernet in behind 32 bit widths and receive FIFO, read whole packet after, the CRC byte that CRC result of calculation and packet carry is carried out verification, and report software to handle comparison result.
106 Ethernet receiver modules, this module regularly receives the port detection signal of network processing unit, when finding that certain port has packet to receive enable signal, start the accepting state machine, packet is read from Ethernet receiver side FIFO, and required to send after each control signal of arrangement according to sequential.
Memory module comprises that mainly the ATM side sends, receives data memory module, Ethernet side transmitting and receiving data memory module, and corresponding each data memory module is provided with the tag storage module, the information that the buffer memory ATM cell is relevant.The all memory modules of the present invention all adopt asynchronous FIFO to realize, take the RAM resource of device inside.The present invention realizes the four-way data-interface at present, can expand according to actual needs.Each passage sends and receives corresponding separate, stored FIFO, according to the CRC calculation requirement, inside modules data processing width is 8bit, externally and ATM layer and network processing unit interface be respectively 16bit and 32bit, Ethernet side storage FIFO width is 32bit, and ATM side storage FIFO width is defined as 8bit.
In an embodiment of the present invention, increase port number as required, add the reception sending module of corresponding port, and in the port arbitration modules, add the corresponding port state just can realize.
In communication system, equipment performance is very important.Data-bus width is respectively 8bit, 16bit and 32bit among the present invention, in order not influence performance, adopts multi-clock zone to handle, work clock comprises the external bus interface clock, install the frequency doubling clock that inner phase-locked loop generates,, eliminate performance bottleneck to mate different data processing width.This device provides 16 CRC computing functions, for economizing on resources, when design CRC is calculated corresponding form and is stored in the RAM.RAM (Random Access Memory) is random access memory (RAM), in the chip that this device adopts a lot of memory cell is arranged, and the user can be arranged to RAM or these dissimilar memories of FIFO with them according to the needs of oneself.In the present invention, the memory cell of some is arranged to a RAM uses, deposit CRC and calculate corresponding form.According to the algorithm requirement, must in a clock cycle, obtain the value of tabling look-up, and calculate the address of next time tabling look-up, therefore it is synchronous to calculate table look-up address and rising edge clock, and reads RAM and the clock trailing edge is synchronous.CRC calculates and is undertaken by byte, for guaranteed performance, the work clock of this module is selected the 66M clock of chip phase-locked loop output for use, and the time-constrain of this module just reaches 120M like this, require relatively strictness, the present invention adopts methods such as optimizing code and wiring to satisfy this constraint.Similar design generally adopts the function table look-at at present, need take a lot of register resources like this, must select for use jumbo device to realize, the method that the present invention adopts has effectively been saved logical resource, reduces chip cost.
Following 2 handling processes that describe the Ethernet sending modules in detail with reference to the accompanying drawings.
Whether 201: the Ethernet side has packet to be sent, and network processing unit sends request signal, detect can send.
202: conversion equipment judges among the corresponding data FIFO whether also have the space of a packet of buffer memory according to the count value of Ethernet side label F IFO, if do not have the space, reports invalid rdy signal, and network processing unit keeps query State.Otherwise report effective rdy signal.
203: after detecting effective rdy signal, network processing unit sends the transmission enable signal, and sends 32 bit data and header signal to data/address bus synchronously, after the Ethernet receiver module detects effective transmission enable signal, starts Ethernet transmit status machine.
204: the Ethernet sending module continues to detect packet frame head signal, when detecting useful signal, enters next handling process.
205: sending module enables this side and sends storage FIFO, and this FIFO width is 32, deposits the data on the external data bus in this FIFO.
206: sending module detects in real time frame end mark in receiving course, when detecting this signal when effective, finishes to receive.
207: close data FIFO, deposit in 8 label F IFO such as the corresponding length of this packet, parity information simultaneously, and begin to wait for next packet, the processing speed of this module is consistent with external interface bus, is 33M.
Accompanying drawing 3 is for sending CRC generation module flow chart.
301: send the count value that the CRC module detects Ethernet side label F IFO output in real time,, enter next flow process when reading Ethernet side label F IFO count value＞=1, promptly show when remaining in the data FIFO to send out packet.
302: detect if the ATM side sends FIFO still has living space, then start CRC transmit status machine, otherwise wait for.
303: enable Ethernet label F IFO, read the corresponding data packet-related information.
304: enable Ethernet side data FIFO, close FIFO after reading 32 bit data.
305:CRC16 need calculate by byte, and for guaranteed performance needs, the frequency multiplication 66M clock that adopts inner phase-locked loop output is as synchronised clock.According to high low level order, 32 bit data are split as byte carry out CRC16 calculating.
306: detect whether to count down to four clock cycle, because Ethernet side data FIFO once reads 32, and 8 of ATM side FIFO write-onces, therefore per four cycles are read Ethernet side FIFO one time, and write operation can carry out continuously.If not to four cycles, proceed CRC and calculate, if count down to four cycles, enter and read the FIFO operation next time.
307: calculate and to detect the frame end mark position simultaneously carrying out CRC,, illustrate that the notebook data bag has transmitted to finish if it is effective to read this signal.
308: CRC result of calculation is attached to the packet end, writes the ATM side and send FIFO, to satisfy the external arrangement checks requirement.Then close ATM side data FIFO.
309: corresponding informances such as this data packet length, port numbers are write ATM side label F IFO, then close FIFO, complete operation.
In this module, it is key component that CRC calculates.CRC16 generator polynomial=1+x
5+ x
12+ x
16, the algorithm of tabling look-up is based on this polynomial a kind of mapping algorithm, and for every 8bit data, the computing formula of tabling look-up is:
CRC＝(CRC＞＞8)^CRCTAB[(CRC^data)&0xFF]
Computational methods are: at first will calculate CRC the 8bit data and last time CRC result the least-significant byte XOR, then again with 16 system data FF with, the data that obtain are the address of tabling look-up, then with last time CRC result move to right 8, high-order with 0 filling, will just can obtain this CRC result of calculation behind these data and the CRC value of the tabling look-up XOR.Wherein:
() ﹠amp CRC^data; 0xFF: expression CRC and data XOR afterwards again with 0xFF with;
CRCTAB (): expression is tabled look-up with the least-significant byte of the value of trying to achieve above, gets a 16bit value;
CRC＞＞8: expression CRC move to right 8 (16 these spies, displacement back most-significant byte is 0);
Each frame calculates CRC=0xFFFF when initial, owing to need and clock synchronization, each clock be along can only calculating once, and calculated value to next clock along just available.Whenever read the 8bit data, by top step double counting.Occur as frame end mark, represent a frame end, CRC=NOT CRC (or CRC XOR0xFFFF), promptly get inverse one time, just obtain the CRC result of calculation of this packet, low byte is preceding then, high byte after, it is last to be attached to packet, writes to send FIFO.
Accompanying drawing 4 is an ATM sending module flow chart.
401:ATM side sending module detects among the ATM side transmission FIFO has packet to be passed, its enable port moderator.
402: if having only a port to have data cached bag to be sent, then need not arbitrate, directly give this port, otherwise, guarantee that each port is all consistent to the occupancy of bus according to the average principle distribution bus with the bus right to use.Sending module detects ATM layer device accepting state simultaneously, if this device temporarily can not receive, this module rests on query State, if can receive, and obtains the bus right to occupation by arbitration, just starts ATM side transmit status machine.
403: the transmit status machine enables corresponding label FIFO, and the relevant information of data cached bag is read, and judges, if this packet is an erroneous packets, then directly abandons, and does not give peripheral components, if normal data packet then begins to transmit.
404: enable data FIFO, read 8 bit width data, because the peripheral interface bus width is 16 bit wides, send again after according to the data sequencing 8 bit width data being converted to 16 highway widths, correspondence is sent each control signal on the bus simultaneously.
405: continue process of transmitting, and detect the frame end mark position in real time,, illustrate that this packet has transmitted to finish in case it is effective to read this signal.
406:ATM transmit status office closes ATM and sends data FIFO, discharges the peripheral bus right to use simultaneously, finishes the packet process of transmitting one time.
Opposite from the ATM layer to the data transmission of Ethernet process with above flow direction, basically identicals such as theory structure.Difference mainly is to have had the CRC byte from the packet end that the ATM layer is come, it is the same with the sending direction processing method to receive the CRC check module, but no longer add the CRC byte, but the CRC byte of calculating gained and packet with byte compare, report software after comparative result is attached to packet.
The present invention mainly finishes data communication and the verification from the ethernet network processor to the ATM layer.By using the present invention, except realizing the communication of Ethernet and ATM layer quickly and easily, also provide the data check function, avoid software to carry out CRC and calculate, save a large amount of system resources, improve the performance of communication apparatus.According to different demands, the present invention can also more convenient expanding, and need not change basic structure and handling process, just can adapt to multiple methods of calibration such as CRC32, perhaps realizes the conversion between other bus type, and the application space is extensive.
Claims (6)
1, a kind of Ethernet and ATM layer Interworking Data conversion calibration equipment, comprise: the ether from Ethernet to ATM layer direction is with net sending module (102), transmission CRC generation module (103), ATM sending module (104) and the ATM receiver module (108) from the ATM layer to the Ethernet direction, reception CRC check module (107), Ethernet receiver module (106), and the ATM side sends, receives memory module and the Ethernet side sends, memory module;
Described Ethernet sending module (102) is used for carrying out data communication with the dedicated bus of the network processing unit of Ethernet side, comprises the control of packet transmit status, and other signal of bus generates and sequential adjustment;
Described transmission CRC generation module (103) is used for that whole packet is carried out CEC and calculates, and adds result of calculation to the packet end;
Described ATM sending module (104) is used for communicating with the ATM physical layer, sends the packet of subsidiary CRC result of calculation;
Described ATM receiver module (108), reception CRC check module (107), Ethernet receiver module (106) are finished corresponding function in the opposite direction of data flow;
Described ATM side sends, receives memory module and the Ethernet side sends, memory module, is used for buffer memory ATM cell relevant information;
At described CRC generation module (103) with receive and to have deposited CRC among the RAM of chip of CRC check module (107) and calculate corresponding form.
2, described Ethernet of claim 1 and ATM layer Interworking Data conversion calibration equipment, it is characterized in that: also having transmit port arbitration modules (105) from Ethernet to ATM layer direction, also having receiving port arbitration modules (109) from the ATM layer to the Ethernet direction; Described transmit port arbitration modules (105) and receiving port arbitration modules when having two or more passages to transmit data, are used for the mean allocation Export resource.
3, claim 1 or 2 described Ethernets and ATM layer Interworking Data conversion calibration equipment, it is characterized in that: this device adopts multi-clock zone, the work clock of wherein CRC generation, verification module is selected the frequency doubling clock of device inside chip phase-locked loop output for use, Ethernet sends, receiver module adopts Ethernet side external bus interface clock, and ATM sends, receiver module adopts ATM side external bus interface clock.
4, realize the method for Ethernet, may further comprise the steps to transmission of ATM layer data and verification:
From the Ethernet side to the ATM layer:
A. the network processing unit of Ethernet (101) is when the ATM layer sends packet, checkout gear corresponding ports state, and this port reports useful signal, and network processing unit sends packet;
B. Ethernet side sending module (102) deposits the 32bit width data in this side storage FIFO;
C. detect among the Ethernet transmitter side storage FIFO and remain to be sent out packet, and judge that the ATM side sends storage FIFO and still has living space, then move transmitter side CRC generation module (103), the sense data bag, carry out 32bit and calculate, deposit ATM side FIFO in to 8bit bit width conversion and CRC;
D. detect among the ATM side FIFO and remain to be given out a contract for a project, this device continues to detect PHY chip (110) port status of ATM layer, if port is effective, start ATM side sending module (104), send after the 8bit width data is converted to 16bit, invalid if port detects, continue to wait for;
From the ATM layer to Ethernet:
The E.ATM layer has packets need to send ethernet network processor (101) to, and corresponding port reported data is surrounded by the effect signal;
F. detect ATM receiver side fifo status, if still have living space, start receiver module (108), deposit FIFO successively in after the 16bit width data is converted to 8bit;
G. detect among the ATM reception FIFO packet is arranged, detecting Ethernet side joint receipts FIFO simultaneously still has living space, then operation receives CRC check module (107), packet is carried out CRC to be calculated, and compare with the CRC byte that receives, judge in the transmission course whether make mistakes, the 8bit width is converted to deposits the Ethernet side joint behind the 32bit width in and receive FIFO;
H. the report network processor has packets need to receive, detect effective received signal after, start Ethernet receiver module (106), read data among the FIFO, give network processing unit (101).
5, the described realization Ethernet of claim 4 is to the method for transmission of ATM layer data and verification, it is characterized in that: data are carried out CRC calculate among step C and the step G, be meant that the packet content that will read in the FIFO gives RAM through calculating the back as the address, provide corresponding control signal then, RAM exports corresponding data, these data is handled obtaining the CRC result calculated again.
6, claim 4 or 5 described realization Ethernets are to the method for transmission of ATM layer data and verification, it is characterized in that: if having two or more passages need transmit data simultaneously, then start transmit port arbitration modules (105) and receiving port arbitration modules (109), make each passage take bus on an equal basis.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2003101118924A CN100473031C (en) | 2003-10-21 | 2003-10-21 | Ethernet and ATM tier joined data vonversion and correction device and method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2003101118924A CN100473031C (en) | 2003-10-21 | 2003-10-21 | Ethernet and ATM tier joined data vonversion and correction device and method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1529476A true CN1529476A (en) | 2004-09-15 |
| CN100473031C CN100473031C (en) | 2009-03-25 |
Family
ID=34304827
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2003101118924A Expired - Fee Related CN100473031C (en) | 2003-10-21 | 2003-10-21 | Ethernet and ATM tier joined data vonversion and correction device and method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100473031C (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2008006307A1 (en) * | 2006-07-03 | 2008-01-17 | Huawei Technologies Co., Ltd. | Method and device of an ethernet bearing atm cells |
| CN1798014B (en) * | 2004-12-20 | 2010-04-28 | 华为技术有限公司 | Method for fixing frame through cyclic redundancy code |
| CN101379777B (en) * | 2006-02-10 | 2011-08-17 | 松下电器产业株式会社 | Radio communication system |
| CN102346469A (en) * | 2011-08-12 | 2012-02-08 | 中国科学院光电技术研究所 | Control method and control system for large-scale photoelectric telescope lens mechanism distribution |
| CN101166082B (en) * | 2006-10-18 | 2012-03-28 | 特拉博斯股份有限公司 | Method and arrangement for synchronization |
| CN103546240A (en) * | 2013-09-24 | 2014-01-29 | 许继集团有限公司 | Ethernet CRC (cyclic redundancy check) checking method |
| CN105791777A (en) * | 2016-04-20 | 2016-07-20 | 安徽师范大学 | FPGA-based gigabit Ethernet video multipath acquisition and transmission system |
| CN107577636A (en) * | 2017-09-12 | 2018-01-12 | 天津津航技术物理研究所 | A kind of AXI bus interface datas Transmission system and transmission method based on SOC |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100319460B1 (en) * | 2000-02-02 | 2002-01-05 | 오길록 | High-end switched router system supporting ATM and ethernet traffic based on ATM cell switch |
| MXPA02011354A (en) * | 2001-03-21 | 2003-04-25 | Corecess Inc | Adsl access multiplexer connected to ethernet and adsl network system using the same. |
-
2003
- 2003-10-21 CN CNB2003101118924A patent/CN100473031C/en not_active Expired - Fee Related
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1798014B (en) * | 2004-12-20 | 2010-04-28 | 华为技术有限公司 | Method for fixing frame through cyclic redundancy code |
| CN101379777B (en) * | 2006-02-10 | 2011-08-17 | 松下电器产业株式会社 | Radio communication system |
| WO2008006307A1 (en) * | 2006-07-03 | 2008-01-17 | Huawei Technologies Co., Ltd. | Method and device of an ethernet bearing atm cells |
| US8279875B2 (en) | 2006-07-03 | 2012-10-02 | Huawei Technologies Co., Ltd | Method and apparatus for Ethernet to bear ATM cells |
| CN101166082B (en) * | 2006-10-18 | 2012-03-28 | 特拉博斯股份有限公司 | Method and arrangement for synchronization |
| CN102346469A (en) * | 2011-08-12 | 2012-02-08 | 中国科学院光电技术研究所 | Control method and control system for large-scale photoelectric telescope lens mechanism distribution |
| CN102346469B (en) * | 2011-08-12 | 2014-03-05 | 中国科学院光电技术研究所 | Control method and control system for large-scale photoelectric telescope lens mechanism distribution |
| CN103546240A (en) * | 2013-09-24 | 2014-01-29 | 许继集团有限公司 | Ethernet CRC (cyclic redundancy check) checking method |
| CN105791777A (en) * | 2016-04-20 | 2016-07-20 | 安徽师范大学 | FPGA-based gigabit Ethernet video multipath acquisition and transmission system |
| CN105791777B (en) * | 2016-04-20 | 2019-03-26 | 安徽师范大学 | Gigabit Ethernet multi-channel video acquiring and transmission system based on FPGA |
| CN107577636A (en) * | 2017-09-12 | 2018-01-12 | 天津津航技术物理研究所 | A kind of AXI bus interface datas Transmission system and transmission method based on SOC |
Also Published As
| Publication number | Publication date |
|---|---|
| CN100473031C (en) | 2009-03-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN1282339C (en) | A data frame buffer memory device and method for Ethernet passive optical network | |
| EP1202182B1 (en) | Apparatus and method for an interface unit for data transfer between a host processor and a digital signal processor in the asynchronous transfer mode | |
| CN1993687A (en) | Message administrator and method for controlling access to data of the message memory of a communications component | |
| CN1667965A (en) | Data transfer control device and electronic instrument | |
| CN103744811A (en) | Serial data transmission system and method | |
| CN1812317A (en) | Synchronous medium access controller | |
| CN1529476A (en) | Ethernet and ATM tier joined data vonversion and correction device and method | |
| CN101242284A (en) | Communication method and network device based on SPI bus | |
| CN1905558A (en) | Individualized ethernet exchange plate and data exchanging method | |
| CN1848715A (en) | Method, system and processing apparatus for realizing synchronous serial data transparent transmission in TDM network | |
| CN1949695A (en) | Method and system for giving-up error frame in frame data transmission | |
| CN1293739C (en) | High speed link control protocol transmission processing/module and data processing/method | |
| CN1825794A (en) | Network device and method for prediction of an optimal sampling phase | |
| CN101047447A (en) | Point-to-point industrial series real-time communication system based on optical fibre and its control method | |
| CN101039323B (en) | Multi-rate multi-protocol bit stream processor | |
| CN1929471A (en) | Device for dispatching and arbitration | |
| CN1863136A (en) | Method and system for transmitting ethernet data packet and multi-DSP serial slot data | |
| Lu et al. | Design and implementation of multi-channel high speed HDLC data processor | |
| TWI394050B (en) | Data transmission device and method based on serial peripheral interface | |
| CN101043437A (en) | Method and apparatus for transmitting quickly operation, management and maintenance cell | |
| CN102790663B (en) | Full-hardware network interface applied to very long baseline interferometry (VLBI) hardware related processor | |
| CN1901492A (en) | Communication method via bus interface in network and and system thereof | |
| CN1825795A (en) | Network device and method for prediction of an optimal sampling phase | |
| CN1738224A (en) | TDM data and frame format conversion circuit and method , transmission switching system and method | |
| CN100338910C (en) | Method of multi-port received and transmitted packet number statistic in network information exchange |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20090325 Termination date: 20141021 |
|
| EXPY | Termination of patent right or utility model |