CN1293739C - High speed link control protocol transmission processing/module and data processing/method - Google Patents
High speed link control protocol transmission processing/module and data processing/method Download PDFInfo
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- CN1293739C CN1293739C CNB02122997XA CN02122997A CN1293739C CN 1293739 C CN1293739 C CN 1293739C CN B02122997X A CNB02122997X A CN B02122997XA CN 02122997 A CN02122997 A CN 02122997A CN 1293739 C CN1293739 C CN 1293739C
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Abstract
The present invention belongs to the technical field of network interconnection devices, which relates to an HDLC protocol transmitting processing module and a data processing method thereof. The module comprises a port arbitration module, a transmitting HDLC protocol processor and a state memory module. The present invention has the data processing method that the port arbitration module receives data request signals from N ports and orderly transmits the request signals of the ports to the transmitting HDLC protocol processor according to priority grades, and the port arbitration module provides arbitration for N port sharing data processing production lines. The transmitting HDLC protocol processor reads out the unprocessed data from an FIFO, reads out the state date of an HDLC channel of the data from the state memory module and carries out pipeline processing to the data, and the transmitting HDLC protocol processor transmits the processed data to the corresponding ports. The transmitting HDLC protocol processor writes the new state date of the HDLC channel back to the state memory. The present invention has the advantages of high processing speed, no linear increase of chip area with port increase, and high versatility.
Description
Technical field
The invention belongs to the network interconnection apparatus, network interconnection technical field, be particularly related to structural design and data processing method thereof that high speed data link control (HDLC) agreement sends processing module.
Background technology
The serial communication control chip that in communication equipments such as router, switch, need use usually, and often need to control simultaneously multiport, multichannel data flow, also promptly mean and to carry out transmission/reception processing of high speed data link control (HDLC) agreement simultaneously to a plurality of passages of a plurality of ports.
The HDLC agreement is in the second layer of OSI(Open Systems Interconnection) seven layer network reference models: data link layer.The data frame structure of HDLC agreement as shown in Figure 1, among the figure: it is initial, the frame end mark of frame that the HDLC Frame is counted 7E (0x7E) with 16 systems, before the frame end symbol, also have a frame check field (FCS) to be used for carrying out the frame check (CRC) of data, this field is an Optional Field, can not have frame check.Fill with 0x7E or 0xFF between frame and the frame, two successive frames can be shared a 0x7E as frame initial sum frame end.In addition, mistake occurs during as if frame of transmission, then can send out frame abortion sign (0xFF), show that these frame data are wrong, find that when receiving the company 1 more than 7 just thinks that frame abortion identifies.When sending, owing in the data 0x7E may be arranged also, for fear of thinking the 0x7E in the data by mistake to be frame identification, need to use the zero insertion function: in data and frame check field,, just do not had frame identification in data and the frame check field like this if find to have 5 companies 1 just to insert one zero in the back of 5 companies 1.At this moment will use zero delete function at receiving terminal: in data and frame check field, have 5 companies 1 just zero of closelying follow later to be removed, thereby recover former data as if finding.
The structure of existing a kind of serial communication controller chip comprises as shown in Figure 2: PLIM, protocol process module, first-in first-out buffer (FIFO), direct memory visit (DMA) module and peripheral element extension interface (PCI) module; Wherein, the PLIM module is responsible for the interface with OSI Reference Model ground floor physical layer, the serial data that physical layer is received becomes the 8bit parallel data and gives protocol process module, or gives physical layer process with the data that the 8bit parallel data that protocol process module sends becomes serial.
Protocol process module comprises HDLC protocol process module and asynchronous serial port protocol process module, carries out the protocol processes of synchronous HDLC serial ports and asynchronous serial port respectively, and the protocol processes of asynchronous serial port and the present invention are irrelevant, no longer introduces.
The structure of HDLC protocol process module is made up of a reception HDLC protocol process module and a transmission HDLC protocol process module as shown in Figure 3.These two modules are separate, the data that handle to receive respectively and the data of transmission, the work that the system that makes can full duplex.
Wherein send the function that protocol process module will be finished:
1. support M HDLC passage;
2. support N port, each port can have a plurality of HDLC passages simultaneously;
3. support transparent transmission;
Frame begin, the automatic generation of frame end mark;
5. support that the frame of sharing begins and frame end mark;
6. data are filled automatically between two transmission frames, and it is able to programme to fill character;
7. support the zero insertion function;
8.16 position/32 CRC frame checks generate (CRC16 and CRC32);
9. the exchange of high low-order bit in the support byte;
10. support the port data negate;
11. support the Flow Control function.
The structure of existing transmission HDLC protocol process module as shown in Figure 4, it is made up of N transmission HDLC protocol processor, a status register, a state arbitration modules and the arbitration modules of fetching data.
Send the existing problem of HDLC protocol process module and data processing method thereof for convenience of explanation, the transmission of carrying out the HDLC agreement with 256 passages to 16 ports is treated to example below.
As can see from Figure 4, use existing serial HDLC protocol process module that the serial data of 16 ports is handled, need 16 (one of each port) and send the HDLC protocol processor, but because each HDLC passage has a large amount of intermediate data (about bit more than 100) to need to preserve, so must carry out the access of 256 HDLC passage intermediate data by 16 shared status registers of processor, therefore the action need of status register be arbitrated.Send the HDLC protocol processor simultaneously from being used for storing first-in first-out buffer circuit (FIFO) the reception data of each passage data to be sent owing to be 16 simultaneously, therefore also need here to arbitrate.The arbitration in these places becomes the bottleneck of system speed, so even improve the speed of each processor, the speed of port can not effectively improve.Use this scheme at master clock during as 33MHz, the maximum port speed of each port at most also can only reach about 8Mbps, and owing to will use 16 to send the HDLC protocol processors, the chip area that takies is also very big.
Summary of the invention
The objective of the invention is in order to overcome the weak point of prior art, propose a kind of high speed data link control protocol and send processing module and data processing method thereof, make that it has that processing speed is fast, area of chip can not increasing and linearly increase the advantage of highly versatile with port.
The present invention proposes a kind of high speed data link control protocol and sends processing module, it is characterized in that, is made up of a port arbitration modules, a transmission high speed data link control protocol processor and a status register module; Wherein, the input of said port arbitration modules links to each other with N port, the input of said transmission high speed data link control protocol processor links to each other with the output of this port arbitration modules output with the first-in first-out buffer circuit that is used for storing each passage data to be sent respectively, with said two-way connection of status register module, the output of this transmission high speed data link control protocol processor is connected with N port simultaneously.
The present invention also proposes a kind of data processing method that is used for above-mentioned module, it is characterized in that, may further comprise the steps:
1) the port arbitration modules receives the data request signal of N port, and the request signal of port is passed to transmission high speed data link control protocol processor successively according to priority level, and provides arbitration for N ports share data processing streamline;
2) this transmission high speed data link control protocol processor is read untreatment data from the first-in first-out buffer circuit that is used for storing each passage data to be sent, the status data of high speed data link control channel under these data is read from the status register module, its data are carried out pipeline processes, the data after handling are delivered to corresponding ports;
3) new state data of this high speed data link control channel is write back status register.
Characteristics of the present invention and good result:
1) uses the parallel transmission high speed protocol processor in the inventive method that the data flow of all of the port is handled, according to priority handle in proper order if port has data need handle then simultaneously.Employing makes the disposal ability of HDLC protocol process module improve greatly to the parallel and pipeline processes of data, and unidirectional throughput is 8 to multiply by clock rate.
2) the inner pipeline organization that adopts of high speed processor of the present invention, each clock can be handled the data of one 8 bit, if support chip one-way data throughput when clock 33MHz of 16 ports to reach 264Mbps, the maximum rate of port can reach 52Mbps, and average port speed is 16Mbps.
3) because the present invention only uses one to send the HDLC protocol processor and can handle N port data, the shared control chip area of protocol processes part not can with port increase and linear increase.And fact proved that it is big unlike single serial HDLC protocol processor that this sends the shared chip area of HDLC protocol processor.That is to say, if the port of supporting is 16, use the shared chip area of protocol process module of this HDLC protocol processor to have only about 1/16th of the existing serial HDLC protocol processor scheme of using, the port number of Zhi Chiing is more if desired, as 32,64, its advantage is unrivaled.
Description of drawings
Fig. 1 is a HDLC frame structure schematic diagram.
Fig. 2 is an existing serial communication controler chip structure block diagram.
Fig. 3 is existing HDLC agreement control module structured flowchart.
Fig. 4 is existing transmission HDLC protocol process module structured flowchart.
Fig. 5 is a transmission HDLC protocol process module structure of the present invention.
Fig. 6 is the structural representation of three class pipeline of the present invention.
Fig. 7 is the schematic diagram that HDLC agreement of the present invention sends the treatment state machine.
Embodiment
The present invention proposes, and a kind of high speed data link control protocol that is used to control the serial communication controller chip of the individual port of N (is embodiment with N=16) sends processing module and data processing method thereof, is described with reference to the accompanying drawings as follows:
The structure of the transmission HDLC protocol process module of present embodiment as shown in Figure 5, it sends the HDLC protocol processor by a port arbitration modules, one and a status register module is formed.Wherein, the input of said port arbitration modules links to each other with 16 ports, the input of said transmission high speed data link control protocol processor links to each other with the output of this port arbitration modules output with the FIFO that is used for storing each passage data to be sent respectively, with said two-way connection of status register module, the output of this transmission high speed data link control protocol processor is connected with 16 ports simultaneously.
The data processing method of the transmission HDLC protocol process module of present embodiment is: this port arbitration modules receives the data request signal of 16 ports, the request signal of port passed to successively according to priority level send the HDLC protocol processor, and provide arbitration for 16 ports share data processing streamlines; This sends the HDLC protocol processor from the FIFO sense data, the status data of HDLC passage under these data is read from the status register module, the data of reading from FIFO are carried out pipeline processes, data after handling are delivered to corresponding ports, and the new state data of this HDLC passage is write back status register.
In order to improve transmitting efficiency, the HDLC agreement transmission processor of present embodiment is provided with the L2 cache structure of being made up of data buffer register (first-level buffer) and data buffer register (level 2 buffering) data of reading from FIFO is carried out buffer memory, that is: the data of reading from FIFO are put into first-level buffer, second level buffering is fetched data from first-level buffer, sending protocol processor handles the data of second level buffering, when this protocol processor was handled the data that the second level is cushioned, first-level buffer can read the data of back from FIFO like this.
The specific implementation step of the data processing method of present embodiment is described in detail as follows respectively:
The above-mentioned method that 16 ports share data processing streamlines is provided arbitration, specifically may further comprise the steps: the data channel that speed is high in the request msg of 16 ports is placed on the little port of port numbers, the more little then priority of port numbers is high more during arbitration, be a plurality of ports simultaneously during request msg, first end for process slogan is low.Can be provided with during use that port speed is no more than maximum rate and the data total throughout is no more than maximum throughput.Because the request of data of each port is just to come data every (8 * processing clock frequency/port speed) individual processing clock, just the situation that the not processed and next request of data of previous request of data has been come can not occur.
Above-mentioned transmission HDLC protocol processor carries out the method for pipeline processes to data, concrete steps are: see whether the port arbitration modules has the passage request for data, if there is application just to start the protocol processes streamline, if do not have application then processing streamline free time that should the clock cycle.
Because the processing procedure more complicated to data was difficult to handle a clock cycle, so the processing streamline of present embodiment adopts three class pipeline to realize data processing, as shown in Figure 6, each clock can be handled one 8 bit parallel data.Each level production line is finished corresponding work, and data are latched with clock deliver to next stage and proceed to handle, the work of each level production line is parallel to be carried out, so might be simultaneously in the data of handling 3 passages, this three class pipeline carries out the method for data processing, specifically may further comprise the steps:
The first order
1. if port has application just to latch the channel number of institute's request for data, place port and mode of operation, Flow Control index signal;
2. send to status register and read enable signal;
The second level
1. latch the status data of reading from status register;
2. data to be sent to reading if current being in sends data or frame check state, are then carried out the detection of 5 companies 1, carry out zero insertion, obtain the data after the zero filling;
3. with these data to be sent and remaining data merging last time, obtain total data to be sent;
4. send the state redirect of treatment state machine according to status bit message;
5. obtain new data to be sent according to the state that sends the treatment state machine;
6. if data buffer register (first-level buffer) has been fed to data buffer register (level 2 buffering), then to sending the data that FIFO please look for novelty;
The third level
1. data to be sent are finished data turning operation (optional), and data are delivered to corresponding ports;
2. be in the transmission data mode if send the treatment state machine, then the data of current preparation carried out frame check and calculate;
3. effective if data buffer register (level 2 buffering) is got the data of sky and buffer register (first-level buffer), then the data in the first-level buffer are sent in the level 2 buffering, finish the bit-order selection function simultaneously;
4. if sending request msg to FIFO, the first order then the new data that obtains from the FIFO request is written to the buffer register; If the data of buffer register are sent, then empty buffer register, otherwise buffer register is constant;
5. send out and write enable information, new mode bit is written in the status register goes.
Used the HDLC agreement to send the treatment state machine in the above in the assembly line processing method of the second level, this state machine is used for controlling the processing procedure that the HDLC agreement sends.The state transition diagram of this state machine as shown in Figure 7.The state that sends the treatment state machine comprises: idle condition, interframe filling, abnormality processing, insertion frame head, transmission data, frame check and postamble insert;
Each redirect condition is explained as follows:
When not finding line errors, the condition of each state redirect comprises:
State machine is in idle condition when resetting (rst);
If in the a-data buffer register data are arranged, and being non-transparent transmission mode, is 0000 or 0001 if interframe fill to be selected bit, and the Flow Control register is when being high.Jump to frame head from idle condition and insert state;
When b-and Flow Control register were high, bit was not 0000 or 0001 if interframe is filled selection, jumps to the interframe occupied state from idle condition;
C-is unconditionally along the redirect of c path;
D-is if these frame data send, when working in non-transparent transmission mode and Flow Control open, when frame check is chosen as CRC16 or CRC32, jump to the frame check state from sending data mode;
E-is if these frame data send, and Flow Control opens, and when frame check is selected be not CRC32 or CRC16, jumps to postamble insertion state from sending data mode.
If the g-frame check is chosen as CRC16, then frame check send byte count be 2 o'clock along the redirect of g path; If CRC is chosen as CRC32, then sending byte count in frame check is to jump to postamble from the CRC state at 4 o'clock to insert state;
If the effective register of h-buffered data is high, and interframe fills that to select bit be 0000, and at this moment the frame identification of consecutive frame is multiplexing, and Flow Control opens, and leaps to the transmission data mode from postamble insertion state, and this moment, continuous Frame was shared flag of frame;
If the effective register of i-buffered data is high, and interframe fills that to select bit be 0001, then jumps to frame head from postamble insertion state and inserts state;
If the effective register of j-buffered data is high, and interframe fills that to select bit be not 0000 or 0001, jumps to the interframe occupied state from postamble insertion state;
If the effective register of k-buffered data is low, or the Flow Control register cuts out; Then jump to idle condition from postamble insertion state;
If r-has sent interframe and filled, then jump to frame head and insert state from the interframe occupied state;
Finding to have under the situation of line errors, if Flow Control is closed or when requiring to make a mistake always transmit frame end sign, then state machine is in the abnormality processing state always, otherwise jump condition is as follows:
If the effective register of f-buffered data is low (may be that mistake causes), and Frame jumps to the abnormality processing state from sending data mode when not finishing;
If the effective register of l-buffered data is high, and interframe fills that to select bit be 0000 or 0001, then jumps to frame head from the abnormality processing state and inserts state;
If the effective register of m-buffered data is high, and interframe fills that to select bit be not 0000 or 0001, then along the redirect of m path, jumps to the interframe occupied state from the abnormality processing state;
If the effective register of n-buffered data is low, then jump to idle condition from the abnormality processing state;
If mistake has taken place o-, then jump to the abnormality processing state from idle condition;
P-is if transparent transmission mode, and the effective register of buffered data is high, then directly jumps to the transmission data mode from the abnormality processing state;
As not satisfying above-mentioned each redirect condition, then state machine acquiescence hold mode is constant.
Because adopt 8 bit parallels to handle, the design and the serial process of zero insertion function just differ widely:
The method of zero insertion is:
To current 8bit data data to be sent (new_data) calculate its from lowest order upwards number connect 1 number (cur_count1_low) and from highest order downwards number connect 1 number (cur_count1_high), after this data processing cur_count1_high saved as from highest order downwards number connect 1 number (last_count1_high);
Order connects 1 counter count1=last_count1_high, data lowest order (new_data[0]) is judged whether to be 1 successively to data highest order (new_data[7]), if 1 company's 1 counter adds 1, and judge whether connect 1 counter equals 5, if equal 5 with one 0 of this bit back insertion, and will connect 1 counter reset to 0.
Zero insertion implementation method in the above-mentioned state machine can use for Do statement or the case statement in the hardware description language (as verilogHDL, VHDL language) to realize, only need take a clock cycle.Less with the circuit area that for Do statement is designed, and the circuit speed of designing with case statement is faster.
Because the realization of other function is fairly simple, available routine techniques means realize, just no longer set forth here.
Use high speed data link control protocol transmission processing module of the present invention and data processing method thereof can realize new high speed HDLC protocol module.And can organize formation serial communication controller chip structure as shown in Figure 2, and the performance of entire chip is improved like this, and chip area has also diminished simultaneously, makes cost lower.Because it is less that the HDLC protocol process module accounts for chip area, can also use programmable logic device to realize (as FPGA) easily, and be applied to any needs and carry out making product development rate improve greatly in the product of HDLC protocol processes, effectively shorten the construction cycle.
Claims (10)
1. a high speed data link control protocol sends processing circuit module, it is characterized in that, is made up of a port arbitration circuit module, a transmission high speed data link control protocol processor circuit module and a status register circuit module; Wherein, the input of said port arbitration circuit module links to each other with N port, the input of said transmission high speed data link control protocol processor links to each other with the output of this port arbitration modules output with the first-in first-out buffer circuit that is used for storing each passage data to be sent respectively, with said two-way connection of status register module, the output of this transmission high speed data link control protocol processor is connected with N port simultaneously.
2. the high speed data link control protocol of stating as claim 1 sends processing module, it is characterized in that said transmission high speed data link control protocol processor comprises the secondary register buffer circuit structure of being made up of one-level data buffer register and secondary data buffer register.
3. one kind is used for the data processing method that high speed data link control protocol sends processing module, it is characterized in that, may further comprise the steps:
3-1) the port arbitration modules receives the data request signal of N port, and the request signal of port is passed to transmission high speed data link control protocol processor successively according to priority level, and provides arbitration for N ports share data processing streamline;
3-2) this transmission high speed data link control protocol processor is read untreatment data from the first-in first-out buffer circuit that is used for storing each passage data to be sent, the status data of high speed data link control channel under these data is read from the status register module, its data are carried out pipeline processes, the data after handling are delivered to corresponding ports;
3-3) new state data of this high speed data link control channel is write back the status register circuit module.
4, data processing method as claimed in claim 3 is characterized in that, saidly provides the method for arbitration to N ports share data processing streamline, specifically may further comprise the steps:
4-1) port numbers with the port that data rate is the highest in N the port is made as 0, and the port numbers of the port that data rate takes second place is made as 1, and the like, the more little then priority of port numbers is high more when arbitration;
4-2) a plurality of ports are simultaneously during request msg, the data of the port that first transmission end slogan is minimum.
5, data processing method as claimed in claim 3 is characterized in that, said transmission high speed data link control protocol processor specifically may further comprise the steps processing method of data:
5-1) said transmission high speed data link control protocol processor is put into the one-level data buffer register to the data of reading from the first-in first-out buffer circuit that is used for storing each passage data to be sent, and second level data buffer register fetches data from the one-level data buffer register;
5-2) when the data of second level data buffer register are carried out pipeline processes, the one-level data buffer register can read the data of back from first-in first-out buffer.
6, data processing method as claimed in claim 5 is characterized in that, said transmission high speed data link control protocol processor carries out the method for pipeline processes to data, specifically may further comprise the steps:
6-1) see at first whether the port arbitration modules has the passage request for data, handle streamline if there is application just to start;
If 6-2) not application then handle the streamline free time.
7, data processing method as claimed in claim 6, it is characterized in that, saidly data are carried out pipeline processes adopt three class pipeline to handle, each level production line is finished corresponding work, and data are latched with clock deliver to next stage and proceed to handle, thereby make each clock can handle one 8 bit parallel data, the work of each level production line is parallel to be carried out, and handles the data of 3 passages simultaneously.
8, data processing method as claimed in claim 7 is characterized in that, the method that said three class pipeline is handled data specifically may further comprise the steps:
The first order
If 8-1-1) port has application just to latch the channel number of institute's request for data, place port and mode of operation, Flow Control index signal,
8-1-2) send to the status register circuit module and read enable signal;
The second level
8-2-1) latch the status data of reading from the status register circuit module,
If 8-2-2) the data to be sent to reading current data processing state or the frame check state of being in, carry out then that 5 bits are the detection of 1 situation continuously in the data, carry out zero insertion, obtain the data after the zero filling,
8-2-3), obtain total data to be sent with these data to be sent and remaining data merging last time,
8-2-4) send the redirect of treatment state machine according to status bit message,
8-2-5) obtain new data to be sent according to the state that sends the treatment state machine,
8-2-6) be fed to data buffer register, then the data that please look for novelty to first-in first-out buffer as if data buffer register;
The third level
8-3-1) data to be sent are delivered to corresponding ports,
8-3-2) be in the transmission data mode, then the data of current preparation carried out frame check and calculate if send the treatment state machine,
8-3-3) effective if data buffer register is got the data of sky and buffer register, then the data in the buffer register are sent in the data buffer register, finish the bit-order selection function simultaneously,
8-3-4) sending request msg to first-in first-out buffer as if the first order then is written to the new data that obtains from the first in first out buffer request the buffer register; If the data of buffer register are sent, then empty buffer register, otherwise buffer register is constant,
8-3-5) send out and write enable information, new mode bit is written in the status register circuit module goes.
9, data processing method as claimed in claim 8, it is characterized in that, with the process that said transmission treatment state machine control high speed data link control protocol sends, the state of this transmission treatment state machine comprises: idle condition, interframe filling, abnormality processing, insertion frame head, transmission data, frame check and postamble insert;
When not finding line errors, the condition of each state redirect comprises:
Send the treatment state machine when resetting and be in idle condition;
If the effective register of a-buffered data is high, and be non-transparent transmission mode, to select bit be 0000 or 0001 if interframe is filled, and the Flow Control register then jumps to frame head insertion state from idle condition when being high;
If the effective register of b-buffered data is high, and be non-transparent transmission mode, and the Flow Control register is when being high, and bit is not 0000 or 0001 if interframe is filled selection, then jumps to the interframe occupied state from idle condition;
C-unconditionally jumps to the transmission data mode from frame head insertion state;
D-is if these frame data send, when working in non-transparent transmission mode and Flow Control open, when frame check is chosen as CRC16 or CRC32, jump to the frame check state from sending data mode;
E-is if these frame data send, and Flow Control opens, and when frame check is selected be not CRC32 or CRC16, jumps to postamble insertion state from sending data mode;
If the g-frame check is chosen as CRC16, then frame check send byte count be 2 o'clock along the redirect of g path; If frame check is chosen as CRC32, then sending byte count in frame check is 4 o'clock, jumps to postamble from the frame check state and inserts state;
If the effective register of h-buffered data is high, and interframe fills that to select bit be 0000, and at this moment the frame identification of consecutive frame is multiplexing, and Flow Control opens, and then leaps to the transmission data mode from postamble insertion state, and this moment, continuous Frame was shared flag of frame;
If the effective register of i-buffered data is high, and interframe fills that to select bit be 0001, then jumps to frame head from postamble insertion state and inserts state;
If the effective register of j-buffered data is high, and interframe fills that to select bit be not 0000 or 0001, then jumps to the interframe occupied state from postamble insertion state;
If the effective register of k-buffered data is low, or the Flow Control register cuts out, and then jumps to idle condition from postamble insertion state;
If r-has sent interframe and filled, then jump to frame head and insert state from the interframe occupied state;
Finding to have under the situation of line errors, if Flow Control is closed or when requiring to make a mistake always transmit frame end sign, then sends the treatment state machine and be in the abnormality processing state always, otherwise jump condition is as follows:
If the effective register of f-buffered data is low, and Frame jumps to the abnormality processing state from sending data mode when not finishing;
If the effective register of l-buffered data is high, and interframe fills that to select bit be 0000 or 0001, then jumps to frame head from the abnormality processing state and inserts state;
If the effective register of m-buffered data is high, and interframe fills that to select bit be not 0000 or 0001, then jumps to the interframe occupied state from the abnormality processing state;
If the effective register of n-buffered data is low, then jump to idle condition from the abnormality processing state;
If mistake has taken place o-, then jump to the abnormality processing state from idle condition;
P-is if transparent transmission mode, and the effective register of buffered data is high, then directly jumps to the transmission data mode from the abnormality processing state;
As not satisfying said redirect condition, it is constant then to send treatment state machine acquiescence hold mode.
10, data processing method as claimed in claim 9 is characterized in that, said zero insertion specifically may further comprise the steps:
10-1) to current data data computation to be sent its from lowest order upwards number be 1 number of bits continuously and be 1 number of bits continuously from the downward number of highest order, after this data processing, will from highest order downwards number be that the number of 1 bit saves as the number that be 1 bit last time continuously from the downward number of highest order continuously;
10-2) the order value that connects 1 counter for last time of preserving from highest order downwards number be the number of 1 bit continuously, the data lowest order is judged whether to be 1 successively to the data highest order, if 1 company's 1 counter adds 1, and judge whether connect 1 counter equals 5, equal 5 as if the company's of discovery 1 counter when a certain bit and behind this bit, insert one 0, and will connect 1 counter reset to 0.
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| CN1984148B (en) * | 2006-05-15 | 2010-11-03 | 华为技术有限公司 | Device and method for controlling high-level data link |
| CN100471156C (en) * | 2007-03-07 | 2009-03-18 | 今创集团有限公司 | Data bus bridge and its working method |
| CN100542180C (en) * | 2007-04-12 | 2009-09-16 | 华为技术有限公司 | Method and device during a kind of bandwidth of advanced data link control channel is dynamically adjusted |
| CN101321038B (en) * | 2008-07-23 | 2010-12-08 | 杭州华三通信技术有限公司 | HDLC controller and HDLC controller report breaking method |
| CN102137086B (en) * | 2010-09-10 | 2013-09-11 | 华为技术有限公司 | Method, device and system for processing data transmission |
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