CN1984148B - Device and method for controlling high-level data link - Google Patents
Device and method for controlling high-level data link Download PDFInfo
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- CN1984148B CN1984148B CN2006100606708A CN200610060670A CN1984148B CN 1984148 B CN1984148 B CN 1984148B CN 2006100606708 A CN2006100606708 A CN 2006100606708A CN 200610060670 A CN200610060670 A CN 200610060670A CN 1984148 B CN1984148 B CN 1984148B
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Abstract
This invention relates to a kind of device of realizing high-level data link control. It includes: bus interface module that has outer interactive function through advanced high-performance bus, HDLC processing lane that connects with stated bus interface module. The stated HDLC processing lane includes core processing module and core control module, the stated core control module controls core processing module according to peripherals DMA request and reads data form peripherals to have HDLC processing through bus interface module. After the completion of core processing module handle, it informs related peripherals or CPU to read the completed data. This invention also provides a corresponding high-level data link control method. Through the providing DMA data movement function in the HDLC processing of this invention, it reduces CPU load and saves CPU processing resource.
Description
Technical field
The present invention relates to data communication field, more particularly, relate to a kind of device and method of realizing the high level data controlling links.
Background technology
HDLC (High-Level Data Link Control, high level data controlling links) is bit-oriented data link control protocol.Because the transmission controlled function of HDLC agreement is separated with processing capacity, and have transparent, the characteristics such as reliability is high, efficiency of transmission is high, flexibility height of transmission, it has been widely used in data communication field, is the important technology of guaranteeing the reliable intercommunication of data message.
As shown in Figure 1, complete HDLC frame is made up of flag sequence F, address field A, control field C, information field I and Frame Check Sequence field FCS.Wherein specify bit combination 01111110 as the flag of frame sequence in the HDLC frame, all frames must begin with F, and finish with F.For accomplishing transparent transmission, the method that adopts " 0 " bit to insert among the HDLC prevents that flag sequence F from occurring in comprising the whole bit sequence of A, C, I and FCS.Concrete grammar is: if any 5 companies " 1 ", then insert 1 " 0 " at transmitting terminal between flag sequence; Receiving terminal is checked the content of received frame, if 5 continuous " 1 " are arranged, then 1 " 0 " of back is left out, as shown in Figure 2 between the discovery flag sequence.The basic functional principle of HDLC agreement is as follows:
According to the HDLC data frame format, receive the high-rise information field that issues at transmitting terminal, insert address field information, link monitoring information is inserted control field, address field+control field+information field is carried out CRC check, additional CRC check bit.Isolate the HDLC Frame with 0x7e, and the HDLC data transaction that will walk abreast becomes serial data, " 0 " bit insertion.Whole data segment is issued sublevel.
Receive the HDLC frame that sublevel is uploaded at receiving terminal, check on the receive direction and carry out frame demarcation, string and conversion and CRC check, " 0 " bit removes.According to the HDLC frame format, carry out CRC and separate verification, extract information such as address field, control field, information field.Finish addressing and link monitoring function.Information field is uploaded high level.
At present, adopt the mode of software-hardware synergism to realize whole HDLC function usually.Specifically, adopt ASIC to realize that the framing of HDLC physical layer/tear open frame, CRC coding or decoding, information transparent transmission handle functions such as the transmission of (" 0 " bit inserts and deletion) and data and acceptance; Address field, control domain, information field etc. are handled and are then realized by software.
As shown in Figure 3, existing HDLC module is made up of 3 parts such as interface module 31, HDLC data transmission blocks 32, HDLC data reception module 33.Wherein, HDLC interface module 31 provides clock, and it is by data, address bus and read-write read-while writing data, and generation and handling interrupt signal.HDLC data transmission blocks 32 latchs transmission data that outer CPU writes and starts according to the sequential of appointment and sends; Add that before sending data segment " 7E " opens the beginning sign; Send after the data sending that data are by turn that CRC calculates and result of calculation being attached to; The data that comprise the CRC calculated value are carried out " zero insertion " operates and encloses " 7E " end mark and the result is sent.HDLC data reception module 33 is used for having or not " 7E " sign in the data flow detection that receives; When " 1F " signal is arranged, then data are carried out " deleting zero " operation in detecting data flow; To carrying out CRC check through the data after " deleting zero "; The data that receive are carried out serial/parallel conversion and deposited two-port RAM in; After receiving end mark, check whether the CRC check value is correct, and the notification interface module data receives.
Yet above-mentioned HDLC module does not provide the DMA function, so HDLC data read or transmission, all needs CPU to intervene, and need take valuable CPU and handle resource.In addition, above-mentioned HDLC module only provides cpu i/f, and bus interface is not provided, and makes it can't be integrated into SOC, thereby slightly inadequate at aspects such as area, power consumption, reliabilities.Above-mentioned HDLC module can't be carried out data block and be handled continuously, after 1 the HDLC data block that at every turn disposes, needing waiting for CPU to issue data (sending direction) or waiting for CPU again all takes away and uploads data (receive direction) afterwards, carry out the operation of HDLC physical layer protocol, efficient is relatively low.
Summary of the invention
The technical problem to be solved in the present invention is, carries out HDLC big and low defective of treatment effeciency of CPU operating load when handling at above-mentioned existing system, and a kind of device and method of new realization high level data controlling links is provided.
The technical solution adopted for the present invention to solve the technical problems is: construct a kind of device of realizing the high level data controlling links, include and be used for by Advanced High-performance Bus and peripheral hardware mutual bus interface module and the HDLC treatment channel that is connected with described bus interface module, described HDLC treatment channel includes core processing module and kernel control module, described kernel control module according to the DMA of peripheral hardware move request signal control core processing module by bus interface module from the peripheral hardware reading of data and carry out HDLC and handle, and core processing module finish dealing with back notice relevant outside if CPU reads the data of finishing dealing with.
In the device of realization high level data controlling links of the present invention, described HDLC handles and comprises that the initial data that will import is converted to the HDLC frame and maybe the HDLC frame of input is converted to initial data.
In the device of realization high level data controlling links of the present invention, described device also comprises the configuration DLL (dynamic link library), and described HDLC treatment channel receives by the configuration DLL (dynamic link library) and changes from the configuration parameter of CPU and to the CPU uploaded state.
In the device of realization high level data controlling links of the present invention, described HDLC treatment channel includes parameter configuration module, described parameter configuration module is resolved from the configuration parameter of CPU and is distributed to kernel control module and core processing module, and the state variation that described parameter configuration module of while also gathers from kernel control module and core processing module supplies the CPU retaking of a year or grade.
In the device of realization high level data controlling links of the present invention, described core processing module includes the FCS module that is used for FCS calculating and verification, the transparence processing module that is used for the transparence processing that connects successively, the flag sequence processing module that is used for insertion of flag of frame sequence and deletion.
In the device of realization high level data controlling links of the present invention, described HDLC treatment channel also includes purpose output buffering that is used to deposit the reception data that dispose and the source input buffering that is used to deposit the transmission data that do not have processing.
In the device of realization high level data controlling links of the present invention, the source input buffering that described kernel control module includes core processing module in the data-moving process is read in the input control module that core processing module is handled with the source peripheral data when empty, and the output control module that when the purpose output buffering of core processing module is full, the data of core processing module purpose output buffering is outputed to the purpose peripheral hardware, wherein said input control module is connected with core processing module respectively with output control module.
In the device of realization high level data controlling links of the present invention, described device includes arbitration modules, described HDLC treatment channel includes a plurality of, described a plurality of HDLC treatment channel is connected to bus interface module via arbitration modules, and described arbitration modules is used to use arbitration algorithm to select specific HDLC treatment channel to carry out bus access between a plurality of HDLC treatment channel.
In the device of realization high level data controlling links of the present invention, it is outer if the DMA of purpose peripheral hardware asks and described DMA is asked to be assigned to the synchronization module of each HDLC treatment channel that described device also includes reception sources.
In the device of realization high level data controlling links of the present invention, described kernel control module also includes the response interface that produces DMA request response or interrupt reporting according to the DMA request from synchronization module, and described response interface sends DMA request clear signal after core processing module is finished data transaction.
In the device of realization high level data controlling links of the present invention, described device also comprises to be removed the DMA from each HDLC treatment channel response and interrupts reporting the summarizing module that responds output.
The present invention also provides a kind of method that realizes the high level data controlling links, may further comprise the steps:
(a) the HDLC module is moved request signal from the peripheral hardware reading of data according to the DMA from peripheral hardware;
(b) the HDLC module will be carried out the HDLC processing from the data that peripheral hardware reads in data;
(c) the HDLC module handle read in data after notice relevant outside if CPU reads the data that dispose.
In the method for realization high level data controlling links of the present invention, the HDLC in the described step (b) handles and comprises: flag of frame detects, transparence is handled, FCS handles.
In the method for realization high level data controlling links of the present invention, the HDLC in the described step (b) handles the initial data that comprises input and is converted to the HDLC frame and/or the HDLC frame of importing is converted to initial data.
The device and method of realization high level data controlling links of the present invention by provide DMA data-moving function in HDLC handles, has alleviated the CPU operating load, has saved CPU and has handled resource.The present invention makes device of the present invention can be integrated into the SOC system also by the Advanced High-performance Bus interface module is provided.In addition, the present invention is by usage data buffer district and inquiry mechanism regularly, realized mutual with CPU, guarantees that the HDLC treatment channel satisfying under the prerequisite of data traffic, can realize continuous productive process, improved transmission process efficient.
Description of drawings
The invention will be further described below in conjunction with drawings and Examples, in the accompanying drawing:
Fig. 1 is the structural representation of HDLC frame;
Fig. 2 is the schematic diagram that transparence is handled;
Fig. 3 is the structured flowchart of existing HDLC module;
Fig. 4 is the structured flowchart that the present invention realizes the device of high level data controlling links;
Fig. 5 is the structured flowchart of HDLC treatment channel among Fig. 4;
Fig. 6 is the structured flowchart of core processing module among Fig. 5;
Fig. 7 is the data structure schematic diagram that the present invention realizes a buffering in the device of high level data controlling links;
As Fig. 8 is the flow chart that the HDLC module is carried out data-moving;
As Fig. 9 is the HDLC module is carried out data transaction when sending data flow chart;
As Figure 10 is the HDLC module is carried out data transaction when receiving data flow chart.
Embodiment
As shown in Figure 4, in one embodiment of the invention, realize that the device (being called for short the HDLC module) of high level data controlling links comprises HDLC treatment channel (Hdlc_Channel) 44, bus interface module (Ahb_Master) 46.Wherein (Advanced High-performance Bus AHB) is connected to peripheral hardware to HDLC treatment channel 44, thereby mutual with peripheral hardware via Advanced High-performance Bus by bus interface module 46.HDLC treatment channel 44 is used to realize DMA data-moving function and HDLC physical layer basic handling, for example initiates to be set to outside DMA request, the realization source that the HDLC module data is moved, HDLC basic handling flow process, realizes that the HDLC module moves to the purpose peripheral data.Bus interface module 46 connects Advanced High-performance Bus, be used to provide the business datum access way of HDLC agreement, bus interface module 46 was all passed through in data output after data were imported or handled before data output, up HDLC handled after data input or the processing before wherein descending HDLC handled.
HDLC of the present invention handles the initial data that comprises input and is converted to the HDLC frame and/or the HDLC frame of importing is converted to initial data.
As shown in Figure 5, be the structured flowchart of HDLC treatment channel 44 among Fig. 4.HDLC treatment channel 44 includes kernel control module 442 and core processing module 443.
Wherein, the FCS module is used for the calculating of FCS, and the scope that FCS calculates comprises address field, control field and the information field handled of transparence not.The transparence processing module is used for sending continuous 5 " 1 " at transmitting terminal and inserts 1 " 0 " afterwards, receives that " 0 " of 5 " 1 " deletion back continuously at receiving terminal; The scope that transparence is handled comprises address field, control field, information field, Frame Check Sequence.Thereby in a HDLC frame, only there are head and the tail to have 7E.The flag sequence processing module is used for carrying out at the HDLC frame gap insertion of flag of frame sequence (0X7E).
The state information of 32 data bufferings of output buffer status register record shows that CPU sends the home state of buffering: " 0 " expression CPU has the data buffering control, can write the HDLC data that will send; " 1 " expression HDLC has the data buffering control, can start the HDLC data and send.Send the data of a buffering as HDLC after, can be automatically that the buffer mark position of correspondence is clear 0, so that CPU writes.CPU need be with relevant position 1 behind the write operation of finishing a buffering.In write operation to register, can only establish 1 the position be set to 1, other the position be set to 0.The buffering at same this place also must be write in order.When kernel control module 442 carried out data-moving, if the source input buffering of core processing module 443 is empty, then the input control module of kernel control module 442 read in core processing module 443 with the source peripheral data and handles; If the purpose of core processing module 443 output buffering is full, then the output control module of kernel control module 442 outputs to the purpose peripheral hardware with the data of core processing module 443 purposes output buffering.
Be convenient control, in the present embodiment, as shown in Figure 5, HDLC treatment channel 44 also includes parameter configuration module 441.Parameter configuration module 441 is used to provide configuration interface, and all parameter configuration or state retaking of a year or grade are all finished via this parameter configuration module 441.Parameter configuration module 441 will be distributed to kernel control module 442 and core processing module 443 after will resolving from the configuration parameter of CPU, collect the state variation that gathers from kernel control module 442 and core processing module 443 simultaneously, in order to the need of CPU retaking of a year or grade.
As shown in Figure 4, for realizing the processing of larger data amount, in the present invention, HDLC treatment channel 44 also can include a plurality of, and the HDLC module also includes configuration DLL (dynamic link library) 41 (Ahb_Slave), arbitration modules (Ahb_Arbiter) 45, synchronization module (Req_Sync) 42 and summarizing module (Rsp_Route) 43.
Configuration DLL (dynamic link library) 41 is used to provide CPU configuration DLL (dynamic link library), and it resolves, is assigned to each independently HDLC treatment channel 44 with the HDLC configuration parameter, simultaneously with each independently HDLC treatment channel 44 information retakings of a year or grade, report CPU after gathering.Arbitration modules 45 is used for according to arbitration algorithms such as fixed priority or repeating queries, arbitrates between a plurality of HDLC treatment channel 44, to select specific HDLC treatment channel, authorizes its ahb bus access control power.
Synchronization module 42 is used for that DMA is moved request signal (hdlc_b/sreq) and carries out synchronization process (latching 2 clock cycle), and provide the DMA request interface being assigned to each autonomous channel from DMA (Direct Memory Access, the direct memory visit) request of source or purpose peripheral hardware.Synchronization module 42 can be 20 peripheral hardwares provides DMA to move request signal, is used for DMA and moves request, and it provides 4 kinds of dma request signal inputs for each peripheral hardware, is respectively:
Group (burst) transfer request signal (hdlc_breq), this signal cause once group transmission, and group length preestablishes;
Single transmission request signal (hdlc_sreq), this signal causes a single transmission, promptly from/to 1 data of peripheral hardware read/write.
Last group transfer request signal (hdlc_lbreq).
Last single transmission request signal (hdlc_lsreq).
Summarizing module 41 is used for that the DMA from each autonomous channel is removed response (hdlc_clrX (X=0～19)), DMA end of transmission response (hdlc_TcY (Y=0～19)) and interruption and reports response (hdlc_IntZ (Z=0～19)) to gather, and obtains unified DMA removing response (hdlc_clr) and interruption and reports response (hdlc_int) output.Wherein:
DMA removing response signal or confirmation signal are used to reply the dma request signal of peripheral hardware;
DMA end of transmission response signal is used to represent that the transmission of whole data block finishes;
HDLC interrupts reporting response signal notice CPU HDLC this moment to detect certain class and interrupts; CPU can determine interrupt source or interrupt type by the inquiry interrupt status register.
As shown in Figure 7, core processing module 442 input buffering (or output buffering) includes length field, status field and valid data territory.Wherein length field is 2 bytes, and expression HDLC frame data have how many bytes (remove the effective byte of length field, status field, do not comprise FCS); The status field is 2 bytes, the error message of indication frame, and flag bit all is 1.The HDLC frame definition that byte number between flag sequence 01111110 surpasses the 2K-4 byte is long; Byte number between flag sequence 01111110 is too short less than the frame definition of 4Byte; For the input from CPU, the status field is complete 0.The valid data territory is a subclass of HDLC frame, comprises address, control and information field.
Certainly, in the device of realization high level data controlling links of the present invention, the HDLC treatment channel also can be connected (for example only by cpu i/f etc.) by other modes with outer if CPU, and the DMA of realization data moves with HDLC and handles.
As shown in Figure 8, for realizing the device of high level data controlling links, the present invention carries out the flow chart of data-moving.
Step S81:HDLC module is carried out inputing or outputing of data, and this is moved can be group transmission means or single transmission mode.When the HDLC module is carried out between peripheral hardware and the peripheral hardware or during the data-moving between peripheral hardware and the external memory unit, the DMA data-moving is initiated by the request of moving of the DMA from peripheral hardware, the HDLC module receives DMA from peripheral hardware and moves the laggard line data of request and move; When the HDLC module was carried out data-moving between peripheral hardware memory cell and the external memory unit, the HDLC module was finished the data input and output voluntarily.
After step S82:HDLC module is whenever finished once group transmission or single transmission data-moving, this group transmission of notice peripheral hardware or single transmission data-moving finish when the data-moving between peripheral hardware and external memory unit (carry out between peripheral hardware or), perhaps automatically to configuration transmission length 1 (when the carrying out the data-moving between peripheral hardware memory cell and external memory unit) that successively decrease.
Step S83: after total data was moved end, the HDLC module discharged the DMA passage that this transmission takies by interrupting reporting CPU.
Carrying out between peripheral hardware or during the data-moving between peripheral hardware and external memory unit, the HDLC module also notifies this data-moving of peripheral hardware to finish; And when the data-moving that carries out between peripheral hardware memory cell and external memory unit, show that when configuration transmission length is decremented to 0 total data moves end.
As shown in Figure 9, when sending data, carry out the flow chart of data transaction for the HDLC module.
Step S91: ready in memory cell when HDLC transmission Frame, the HDLC module reads the HDLC frame data from designated memory locations, carries out FCS processing, transparence processing and flag of frame and inserts processing, all runs through up to data;
Step S92:HDLC module sends after 1 HDLC frame data, by the mode and the software interactive that interrupt or software is inquired about, notifies certain HDLC frame to send and finishes.
As shown in figure 10, when receiving data, carry out the flow chart of data transaction for the HDLC module.
Step S101: peripheral hardware (SPI, UART) is moved request signal by driving DMA, and notice HDLC module has the data input;
Step S102:HDLC module is read in data from peripheral hardware, carry out to reading in data that flag of frame detects, transparence is handled (auto zero deletion after continuous 5), FCS handles (CRC check processing) then, to handle the back data at last and write designated memory cell, handle 1 complete HDLC frame up to reception;
Step S103:HDLC module is after receiving 1 HDLC frame, and is mutual by interrupting with CPU, and notice CPU reads the HDLC frame that has disposed.
CPU is after reading the HDLC frame of the memory cell that finishes, and notice HDLC module HDLC receiving data frames has read in memory cell and finished.
The above; only for the preferable embodiment of the present invention, but protection scope of the present invention is not limited thereto, and anyly is familiar with those skilled in the art in the technical scope that the present invention discloses; the variation that can expect easily or replacement all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection range of claim.
Claims (11)
1. a device of realizing high level data controlling links HDLC is characterized in that, comprising:
Be used for the bus interface module mutual with peripheral hardware;
The HDLC treatment channel that is connected with described bus interface module, described HDLC treatment channel includes core processing module and kernel control module, described kernel control module reception sources peripheral hardware is moved request signal by the DMA of ahb bus input, described DMA moves request signal and comprises: group transfer request signal hdlc_breq, this hdlc_breq signal causes once group transmission, group length preestablishes, single transmission request signal hdlc_sreq, this hdlc_sreq signal causes a single transmission, last group transfer request signal hdlc_lbreq and last single transmission request signal hdlc_lsreq; Move request signal control core processing module by described DMA and carry out the HDLC processing from described source peripheral hardware reading of data and to data streams read, and notice purpose peripheral hardware reads the data of finishing dealing with by ahb bus output after core processing module is finished dealing with by bus interface module.
2. the device of realization high level data controlling links according to claim 1 is characterized in that described bus interface module is connected to peripheral hardware by Advanced High-performance Bus.
3. the device of realization high level data controlling links according to claim 1, it is characterized in that, described device also comprises the configuration DLL (dynamic link library), and described HDLC treatment channel receives by the configuration DLL (dynamic link library) and changes from the configuration parameter of CPU and to the CPU uploaded state.
4. the device of realization high level data controlling links according to claim 3, it is characterized in that, described HDLC treatment channel includes parameter configuration module, described parameter configuration module is resolved the configuration parameter of described configuration DLL (dynamic link library) transmission and is distributed to kernel control module and core processing module, described parameter configuration module also gathers the state variation from kernel control module and core processing module simultaneously, and supplies the CPU retaking of a year or grade by described configuration DLL (dynamic link library).
5. the device of realization high level data controlling links according to claim 1, it is characterized in that described core processing module includes the FCS module that is used for FCS calculating and verification, the transparence processing module that is used for the transparence processing that connects successively, the flag sequence processing module that is used for insertion of flag of frame sequence and deletion.
6. the device of realization high level data controlling links according to claim 5, it is characterized in that described core processing module also includes purpose output buffering that is used to deposit the reception data that dispose and the source input buffering that is used to deposit the transmission data that do not have processing.
7. the device of realization high level data controlling links according to claim 6 is characterized in that, described kernel control module comprises:
Input control module is used for when source input buffering described in the data-moving process is sky the source peripheral data being read in core processing module and handles;
Output control module, the data that are used for when described purpose output buffering is full described purpose output being cushioned output to the output control module of purpose peripheral hardware;
The output control module of wherein said input control module and kernel control module is connected with core processing module respectively.
8. the device of realization high level data controlling links according to claim 1, it is characterized in that, when described device comprises a plurality of HDLC treatment channel, described device also includes arbitration modules, described a plurality of HDLC treatment channel is connected to bus interface module via arbitration modules, and described arbitration modules is used to use arbitration algorithm to select specific HDLC treatment channel to carry out bus access between a plurality of HDLC treatment channel.
9. the device of realization high level data controlling links according to claim 1 is characterized in that, it is outer if the DMA of purpose peripheral hardware asks and described DMA is asked to be assigned to the synchronization module of each HDLC treatment channel that described device also includes reception sources.
10. the device of realization high level data controlling links according to claim 1, it is characterized in that, described kernel control module also includes the response interface that produces DMA request response or interrupt reporting according to the DMA request from synchronization module, and described response interface sends DMA request clear signal after core processing module is finished data transaction.
11. the device of realization high level data controlling links according to claim 10 is characterized in that, described device also comprises to be removed the DMA from each HDLC treatment channel response and interrupts reporting the summarizing module that responds output.
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| CN102957489B (en) * | 2008-02-03 | 2015-04-01 | 大唐移动通信设备有限公司 | Clock synchronization method and master-slave clock entity |
| CN102098333B (en) * | 2010-12-31 | 2013-04-24 | 北京中创信测科技股份有限公司 | High-level data link control (HDLC) data processing method and system |
| CN109446143B (en) * | 2018-10-16 | 2021-05-25 | 武汉精立电子技术有限公司 | FPGA-based data serial transmission control system and method |
| CN112559428A (en) * | 2020-12-21 | 2021-03-26 | 苏州易行电子科技有限公司 | HDLC controller's FPGA chip based on PCIe |
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| CN1223730A (en) * | 1996-06-27 | 1999-07-21 | 交互数字技术公司 | Parallel packatized intermodule arbitrated high speed control and data bus |
| CN1466348A (en) * | 2002-06-15 | 2004-01-07 | 华为技术有限公司 | High speed link control protocol transmission processing/module and data processing/method |
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| C06 | Publication | ||
| PB01 | Publication | ||
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