CN109446143B - FPGA-based data serial transmission control system and method - Google Patents
FPGA-based data serial transmission control system and method Download PDFInfo
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Abstract
The invention discloses a data serial transmission control system based on FPGA, which is used for data transmission and control between two FPGAs and is characterized in that the control system comprises a protocol module, an arbitration module and a sub-function module which are connected in sequence, wherein the sub-function module is used for carrying out data transmission function configuration on the data serial transmission control system; the arbitration module is connected with the sub-function modules through the expansion interface, and executes output data accessed to the sub-function modules of the arbitration module according to the transmission sequence of the arbitration protocol, or distributes input data received from the protocol module to the corresponding sub-function modules; the protocol module provides a uniform data transceiving protocol. Aiming at the conditions of complex FPGA data serial transmission structure, disordered transmission protocol and poor expansibility in the prior art, the technical scheme of the invention can ensure the ordered and stable execution of various data transmission requests by encapsulating different functions into different sub-modules and combining an arbitration module and a protocol module.
Description
Technical Field
The invention belongs to the field of data transmission control, and particularly relates to a data serial transmission control system and method based on an FPGA (field programmable gate array).
Background
An FPGA (Field-Programmable Gate Array), which is a product of further development based on Programmable devices such as PAL, GAL, CPLD, etc. The circuit is a semi-custom circuit in the field of Application Specific Integrated Circuits (ASIC), not only overcomes the defects of the custom circuit, but also overcomes the defect that the number of gate circuits of the original programmable device is limited. In the AOI automatic optical inspection industry, fpga is often used as a main control processing transmission unit of a camera for data transmission. However, in practice, due to the diversity of the actual situation, the number of cameras and fpga often changes with the demand, and in addition, the data amount increases day by day, the stability of parallel transmission and the rate far cannot meet the demand, so the architecture for serial data transmission by fpga is required to be built.
When the traditional FPGAs are interconnected, the proprietary protocol is usually built by itself after the transceivers are interconnected, and the proprietary protocol is built by itself between different FPGAs through the GT transceiver. However, the data transmission form of the self-established proprietary protocol still has many problems in practical use. For example, in the prior art, a form of direct use of a xilinx transceiver is generally adopted, a nonstandard interface with charrisk mask characters of 8b10b is adopted as a data stream interface, and the data stream interface has no blockage or handshake and is difficult to understand and control during use. . Data synchronization (channel bonding) between multiple lanes and clock correction (clock correction) between receive and transmit require manual synchronization. For another example, the transmission process uses a data signal without handshake, and if the transmission interval and transmission bandwidth are not well controlled, data loss is easily caused if the bandwidths of the front and rear stages are not matched. And an error monitoring mechanism is not provided, so that the problem of poor positioning can be solved. In addition, on the transmission protocol of the FPGA, protocols of each link layer are not clearly distinguished, information exchange between different functional regions is often in a disordered state, and effective data is lacked, which finally results in that when the coupling of multiple functions is too strong, clear order is lacked, and finally, the data transmission efficiency of the FPGA is low. Further, in the expansibility aspect, in the prior art, because the coupling of each function of the link layer is too strong, the increase and the cutting of any function are very complicated while the high integration is realized.
Therefore, there are many problems in the prior art for FPGA-based data transmission, especially for image data transmission, and the main focus is on: due to the non-standardization of a physical layer protocol, the scrambling code verification and the clock repair function in the communication principle are not used, and the stability of the physical layer is poor; the transmission data is lost due to different transmission flow sizes of different transmission modules; the module interface does not have the function of temporary blocking, and the data stream can only be continuously transmitted and cannot be suspended for waiting; various transmission control functions cannot be distinguished clearly, and the coupling of different functional modules is too strong, so that certain difficulty is brought to increasing and cutting off functions.
Disclosure of Invention
In view of the above-mentioned drawbacks and needs of the prior art, the present invention provides a system and method for controlling serial data transmission based on FPGA, which at least partially solves the above-mentioned problems. Aiming at the conditions of complex FPGA data serial transmission structure, disordered transmission protocol and poor expansibility in the prior art, the technical scheme of the invention can ensure the ordered and stable execution of various data transmission requests by encapsulating different functions into different sub-modules and combining an arbitration module and a protocol module.
In order to achieve the above object, according to one aspect of the present invention, there is provided a data serial transmission control system based on an FPGA, for controlling data serial transmission of the FPGA, wherein the control system includes a protocol module, an arbitration module, and a sub-function module, which are connected in sequence; the sub-function modules are used for carrying out data transmission function configuration on the data serial transmission control system, and each sub-function module preferably corresponds to a data transmission task of the FPGA;
the arbitration module is connected with the sub-function modules through the expansion interface, and executes output data of the sub-function modules accessed to the arbitration module according to the transmission sequence of the arbitration protocol, or distributes input data received from the protocol module to the corresponding sub-function modules;
the protocol module provides a uniform physical layer data transmission protocol for data transmission among different FPGAs, receives output data of the sub-function module according to the transmission sequence of the arbitration module and transmits the output data to the adjacent FPGA units, or receives input data from the adjacent FPGA units and transmits the input data to the arbitration module.
The protocol module is generally a specific transceiver, and after receiving the output data transmitted by the arbitration module, the protocol module sends the output data to the FPGA unit adjacent to the protocol module. Specifically, the protocol module (transceiver) transmits output data to the FPGA unit connected thereto. And the protocol module for receiving the data processes the data and distributes the data to the corresponding position of the current FPGA.
As a preferred embodiment of the present invention, the control system further includes a data flow control module, where the data flow control module is connected to the protocol module, and performs data flow control on the data serial transmission control system through a data interface on the protocol module, so as to ensure data flow balance between the data sending end and the data receiving end.
As a preferred embodiment of the present invention, the sub-function module includes one or more of a timing status transceiver module, a register configuration transceiver module, and an image transmission transceiver module;
the timing state transceiver module is used for receiving and/or transmitting a state register of the FPGA;
the register configuration transceiver module is used for configuring a state register in the FPGA;
the image transmission transceiver module is used for transmitting data and/or configuring parameters of transmission data streams.
As an optimization of the technical solution of the present invention, the bit width of the data stream sent by the sub-function module is preferably matched with the bit width of the data stream of the protocol module.
As a preferred embodiment of the present invention, the sub-function module is preferably connected to the arbitration module through a bidirectional interface, so as to transmit data to the arbitration module and receive data from the arbitration module.
Specifically, the timing state transceiver module, the register configuration transceiver module, and the image transmission transceiver module can actively control and manage the data transmission process of the FPGA where the timing state transceiver module, the register configuration transceiver module, and the image transmission transceiver module are located, and can also receive parameters of other FPGAs to control and manage the data transmission process of the FPGA. Therefore, the sub-function module according to the present invention is preferably connected to the arbitration module by using a bidirectional interface, and can transmit data (output data) to the arbitration module and receive data (input data) from the arbitration module.
As a preferred embodiment of the technical solution of the present invention, the arbitration module receives output data from the sub-function modules, adds sub-module marks to the output data of each sub-function module, and transmits the output data to the adjacent FPGA units through the protocol module; or receiving input data from the protocol module, identifying the sub-module marks of the input data, and then respectively transmitting the sub-module marks to the corresponding sub-function modules.
As an optimization of the technical scheme of the invention, each FPGA controls the data transmission in the current FPGA through a data serial transmission control system, and adjacent FPGA units are preferably connected through the data serial transmission control system.
According to an aspect of the present invention, there is provided a data serial transmission control method based on the data serial transmission control system according to any one of claims 1 to 7, including a data serial input and a data serial output, wherein the data serial output is performed as follows,
s1, selecting at least one sub-function module according to the data serial transmission control requirement and configuring the parameters of the sub-function module, wherein the sub-function module is connected with the arbitration module by adopting an expansion interface;
s2 the arbitration module receives the output data of the sub-function module according to the arbitration protocol, and adds sub-module mark on the received output data to identify the category of the sub-function module;
s3 sending the marked output data to the protocol module, and forwarding the output data to the adjacent FPGA unit through the protocol module.
As a preferred embodiment of the present invention, the data serial input process is as follows,
the S1' protocol module receives the input data of the adjacent FPGA unit and sends the input data to the arbitration module; s2' arbitration module analyzes the input data, obtains the sub-module mark of the input data and identifies it;
s3' unloads the sub-module tag of the input data and sends it to the corresponding sub-function module.
As a preferred embodiment of the present invention, the arbitration module performs arbitration sequencing on the data transmission requests of the sub-function module according to an arbitration protocol, and performs data transmission according to the arbitration sequencing, so as to ensure the ordered execution of a plurality of data transmission requests.
Generally, compared with the prior art, the above technical solution conceived by the present invention has the following beneficial effects:
1) according to the technical scheme, aiming at the problems that in the prior art, a private protocol is built among different FPGAs through a GT transceiver, so that a data serial transmission structure is complex, the operation difficulty is high during use and the like, a stable and consistent data transmission protocol is provided for the whole FPGA data transmission structure by adopting the same protocol module (such as Aurora6466 or other alternative structures with the same function in the embodiment), and the data is ensured not to generate larger errors due to disorder of the transmission protocol when passing through a plurality of FPGAs.
2) According to the technical scheme, aiming at the problems that protocols of a link layer are not clearly distinguished and different functionalities cause too strong coupling of multiple functionalities in the prior art, the functions are distinguished in the form of sub-modules through an arbitration module (such as a stream arbiter or other alternative structures with the same function in the embodiment), any two sub-modules are not interfered with each other, and the sub-modules are respectively communicated with the arbitration module to execute data transmission tasks, so that the high efficiency and the accuracy of data analysis are ensured.
3) The technical scheme of the invention aims at the problems of interface disorder, easy data loss and inaccurate positioning in the transmission process in the prior art, and can adjust the data transmission speed according to the requirement and track and position the transmission data by using the AXI-STREAM interface with the block and carrying out crc check on the data under the action of the data flow control module.
Drawings
Fig. 1 is a structural diagram of a data serial transmission control system in an embodiment of the present invention;
fig. 2 is a data transmission structure diagram of the output data of the timing state transceiver module after being marked in the embodiment of the technical solution of the present invention;
fig. 3 is a data transmission structure diagram of a register configuration transceiver module after output data is marked according to an embodiment of the present invention;
fig. 4 is a data transmission structure diagram of an image transmission transceiver module after output data is marked according to an embodiment of the present invention;
fig. 5 is a structural diagram of individual interconnection of FPGAs by using a data serial transmission control system in the embodiment of the technical solution of the present invention;
fig. 6 is a structural diagram of a plurality of interconnected FPGAs by using a data serial transmission control system in the embodiment of the technical solution of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention. In addition, the technical features involved in the embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other. The present invention will be described in further detail with reference to specific embodiments.
The technical scheme of the invention provides a data serial transmission control system and method based on FPGA, aiming at the problems of complex design structure, poor stability, disordered transmission protocol, poor expansibility and the like existing in the serial transmission of image data by using FPGA in the prior art, and the system and method have simple structure and higher transmission stability and transmission efficiency.
Specifically, in this embodiment, a data serial transmission control system is used to control and manage the data transmission process of the FPGA. The data serial transmission control system of the embodiment comprises a protocol module, an arbitration module, a sub-function module, a data flow control module and the like.
The sub-function modules belong to a class of sub-modules, and each sub-module has a specific function, such as a timing state transceiver module for transmitting a state register at a timing, a register configuration transceiver module for configuring an FPGA register, an image transmission transceiver module for executing a specific data transmission task, and the like, which are collectively called as sub-function modules. Each sub-function module independently executes the function task without mutual interference. And the sub-function module is connected with the arbitration module through an expansion interface. In other words, the arbitration module of this embodiment is provided with at least one expansion interface, and the sub-function module is connected to the arbitration module through the expansion interface. Therefore, data of each sub-function module independently enters the arbitration module, the problem of mutual interference between the data of each sub-function module and other sub-function modules is avoided, and the function singleness, stability and accuracy of each sub-function module are guaranteed.
In a specific embodiment, the timing status transceiver module preferably sends the current status of the FPGA and the camera to inform other FPGAs of the current status by a fixed time. Furthermore, the bit width and the number of the reported status registers can be set through parameters, so that the status registers are convenient for developers to use, and a slave register interface and a master register interface are preferably arranged on the status registers, so that the status registers can be sent and received.
When the FPGA is controlled, the register needs to be configured. The register configuration transceiver module in this embodiment can configure various parameters of the register, such as bit width and depth, by self-defining the parameters, so as to facilitate adapting the user interface. Preferably, the module has a slave interface and a master interface, and can be configured with other FPGAs actively and also can accept the configuration of other modules, thereby ensuring the bit width stability in the data transmission process to the maximum extent (the data transmission bit width is matched between different modules).
The image transmission transceiving module is a submodule specially used for transmitting a large amount of data in the FPGA, and can transmit data streams with corresponding bit widths according to parameter configuration. Further, it can configure the length of the transmission data stream according to the requirement. The data stream is automatically split according to the length of the data requested to be transmitted, and the split data stream is sent to other FPGAs for multiple times, so that the phenomenon that the length of the transmitted data is too large and the whole data transmission channel (the arbiter of the arbitration module in the embodiment) is occupied is avoided.
The protocol module provides a uniform transmission protocol for the data transmission process of the FPGAs, and in a data transmission structure in which two or more FPGAs are independently interconnected or a plurality of FPGAs are interconnected (as shown in fig. 5 and 6, imgserrdes is a short for fgpa-based image serial transmission control module), because the data transmission protocols used by each FPGA are consistent, the stability and accuracy of data transmission are ensured to a certain extent. The protocol module receives the data from the arbitration module and forwards the data to the adjacent FPGA unit, namely the FPGA unit directly connected with the protocol module.
In one particular embodiment, Aurora6466 is preferably employed as the protocol module. Briefly, Aurora6466 is a data transceiver that provides a uniform physical layer data transmission protocol for controlling data transmission between FPGAs. The adjacent cells are preferably FPGA cells directly connected to the data transceiver. Specifically, in this embodiment, the module is a xilinx official IP, and the physical layer is a xilinx transceiver to ensure data transmission, and the xlinx transceiver is interconnected through an optical fiber or other high-speed signal lines. Further, the link layer transmission protocol is an aurora protocol, 64b/66b coding is internally integrated, and clock correction and channel coding are used for preventing data underflow or overflow caused by different tx/rx clock sources and the problem of rate mismatch among multiple groups of lanes. In this embodiment, Aurora6466 is preferably connected to other structures through an Axi-stream interface to facilitate block operations.
The arbitration module is an important role of the FPGA in the data transmission process of the embodiment, and at least undertakes two functions of channel arbitration allocation and sub-function module identification. In this embodiment, the arbitration module is provided with one or more expansion interfaces to meet the expansion requirements of the plurality of sub-function modules. Meanwhile, because each expansion submodule and each expansion interface are independent, the situation that coupling of different functions is too strong and data analysis is disordered instead can be avoided. In this embodiment, when the arbitration module is integrated with a plurality of sub-function modules, and each sub-function module operates independently, it is necessary to arbitrate data transmission requests of the plurality of sub-function modules. Specifically, when data output from the sub-function module to the outside (other FPGA) is performed (i.e., data output), it is necessary to determine the weight of each arbitration sub-module, execute data transmission requests of the plurality of sub-function modules according to the weights, and determine the data transmission order of the plurality of sub-function modules. For example, when the timing status transceiver module, the register configuration transceiver module, and the image transmission transceiver module simultaneously transmit data streams to be transmitted, and these data transmission requests reach the arbitration module, the arbitration module needs to sequence the data transmission requests according to an arbitration protocol, reasonably allocate data transmission channels to the sub-function modules for data transmission, and perform mark identification on output data. That is, a sub-module mark symbol is added on the output data of each sub-function module to indicate which sub-module the output data comes from for the receiving end to identify.
In addition, when receiving data transmitted from the outside to the current FPGA, the data input to the FPGA (i.e., input data) is transmitted to the arbitration module through the protocol module, and the arbitration module needs to analyze and identify the data according to the sub-module tag symbol, determine which sub-function module the input data originates from, and transmit the input data without the sub-module tag symbol to the sub-function module corresponding to the current data serial transmission control system.
Further, in the embodiment, the data stream control module is further provided in the data serial transmission control system, and in this embodiment, the data stream control module controls the data stream by controlling an ncf interface of aurora, so as to ensure that the receiving fifo at the back end of the data can timely notify the transceiver at the transmitting end to stop transmitting under the condition of prog _ full without affecting the whole data stream (the data stream interface only pulls down ready, which indicates that data transmission cannot be performed), so as to ensure stable transmission of the data stream.
In a specific embodiment, the arbitration module is preferably an Axi Stream Arbiter, that is, an Arbiter of a Stream interface, and the Arbiter adopts a parameterized design, and can customize any bit width and any channel number. Furthermore, each expansion interface is provided with a slave interface and a master interface, so that the expansion interfaces support simultaneous transceiving in the sub-function modules under the condition that the sub-function modules are not interfered with each other. The arbitration module preferably adopts round robin mechanism for arbitration, so as to ensure fairness of arbitration among channels.
Since the StreamArb module can be set to any channel through parameters, any sub-function module (submodules such as TimedReg, ConfigReg, imgcream, etc.) can be added according to the function requirement, and the interface between the submodules and the StreamArb is preferably AXI-Stream. When data transmission is carried out, the streamerb adds an ArbHeader to input data, the ArbHeader is unloaded after the input data are received, the ArbHeader is simultaneously sent to the sub-modules, and own protocols can be designed in the sub-modules.
As a preferred form of this embodiment, fig. 2 to 4 show a specific form of data stream transmission of the sub-module in this embodiment. As shown in fig. 2, in the data transmission process of the timing status transceiver module (TimeReg), the arbitration module adds an ArbHeader to the TimeReg requested to be transmitted by the timing status transceiver module itself for identifying the data source. Correspondingly, when receiving the TimeReg with the ArbHeader, the arbitration module identifies the TimeReg corresponding to the timing state transceiver module according to the ArbHeader thereon, and sends the TimeReg to the sub-function module corresponding to the current data serial transmission control system after removing the ArbHeader.
Similarly, fig. 3 and 4 are data stream transmission forms of the register arrangement transceiver module (ConfigReg) and the image transmission transceiver module (ImgStream) in the present embodiment. In this embodiment, it is preferable that the register configuration transceiver module packages data into a WR _ PKG data stream by a write operation, packages a read operation into an RD _ PKG data stream by a read operation, packages read data into the RD _ PKG data stream by the read operation, packages the read data into the RD _ ACK _ PKG data stream above, and then sends the packaged data stream to StreamArb (i.e., an arbitration module), where the StreamArb adds an ArbHeader as a flag in front of the data stream and sends the ArbHeader to another FPGA. If the received data packet is StreamArb, the data packet is distinguished according to the ArbHeader and is sent to the corresponding submodule.
For the image transmission transceiver module, when receiving a Data transmission request, such as an image, the Master part of the module firstly packages an ImgHeader Pkg to notify the receiving Slave, an image is coming and acquires Src information and Len information, and then the Master packages the Data into Data Pkg and Data last Pkg (the last Data packet is Data last Pkg). StreamArb will add an ArbHeader as a flag before the data stream and send it to another block Fpga. After receiving the data packet, StreamArb will distinguish which channel according to ArbHeader and then send to the corresponding channel.
It will be understood by those skilled in the art that the foregoing is only a preferred embodiment of the present invention, and is not intended to limit the invention, and that any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (10)
1. A data serial transmission control system based on FPGA is used for controlling the data serial transmission of FPGA and is characterized in that the control system comprises a protocol module, an arbitration module and a sub-function module which are connected in sequence; the sub-function modules are used for carrying out data transmission function configuration on the data serial transmission control system, and each sub-function module corresponds to one data transmission task of the FPGA;
the arbitration module is connected with the sub-function modules through the expansion interface, and executes output data of the sub-function modules accessed to the arbitration module according to the transmission sequence of the arbitration protocol, or distributes input data received from the protocol module to the corresponding sub-function modules; specifically, when the data of the executed sub-function modules are output to the outside, the weight of each sub-function module is determined, the data transmission requests of a plurality of sub-function modules are executed according to the weight, and the data transmission sequence of the plurality of sub-function modules is determined;
the protocol module provides a uniform physical layer data transmission protocol for data transmission among different FPGAs, receives output data of the sub-function module according to the transmission sequence of the arbitration module and transmits the output data to the adjacent FPGA units, or receives input data from the adjacent FPGA units and transmits the input data to the arbitration module.
2. The FPGA-based data serial transmission control system of claim 1, further comprising a data flow control module, wherein the data flow control module is connected to the protocol module, and performs data flow control on the data serial transmission control system through a data interface on the protocol module, so as to ensure data flow balance between the data sending end and the data receiving end.
3. The FPGA-based data serial transmission control system of claim 1 or 2, wherein the sub-function modules comprise one or more of a timing status transceiver module, a register configuration transceiver module, an image transmission transceiver module;
the timing state transceiver module is used for receiving and/or transmitting a state register of the FPGA;
the register configuration transceiver module is used for configuring a state register in the FPGA;
the image transmission transceiver module is used for transmitting data and/or configuring parameters of transmission data streams.
4. The FPGA-based data serial transmission control system of claim 1 or 2, wherein the data stream bit width transmitted by the sub-function module matches the data stream bit width of the protocol module.
5. The FPGA-based data serial transmission control system of claim 1 or 2, wherein the sub-function module is connected to the arbitration module via a bidirectional interface so as to send data to and receive data from the arbitration module.
6. The FPGA-based data serial transmission control system as claimed in claim 1 or 2, wherein the arbitration module receives the output data from the sub-function modules, adds sub-module marks to the output data of each sub-function module, and then transmits the output data to the adjacent FPGA unit through the protocol module; or receiving input data from the protocol module, identifying the sub-module marks of the input data, and then respectively transmitting the sub-module marks to the corresponding sub-function modules.
7. The FPGA-based data serial transmission control system of claim 1 or 2, wherein each FPGA controls data transmission in the current FPGA through the data serial transmission control system, and adjacent FPGA units are connected through the data serial transmission control system.
8. A data serial transmission control method based on the data serial transmission control system according to any one of claims 1 to 7, comprising a data serial input and a data serial output, wherein the data serial output is performed as follows,
s1, selecting at least one sub-function module according to the data serial transmission control requirement and configuring the parameters of the sub-function module, wherein the sub-function module is connected with the arbitration module by adopting an expansion interface;
s2 the arbitration module receives the output data of the sub-function module according to the arbitration protocol, and adds sub-module mark on the received output data to identify the category of the sub-function module;
s3 sending the marked output data to the protocol module, and forwarding the output data to the adjacent FPGA unit through the protocol module.
9. The data serial transmission control method according to claim 8, wherein the data serial input process is as follows,
the S1' protocol module receives the input data of the adjacent FPGA unit and sends the input data to the arbitration module;
s2' arbitration module analyzes the input data, obtains the sub-module mark of the input data and identifies it;
s3' unloads the sub-module tag of the input data and sends it to the corresponding sub-function module.
10. The data serial transmission control method according to claim 8 or 9, wherein the arbitration module arbitrates and orders the data transmission requests of the sub-function module according to an arbitration protocol, and performs data transmission according to the arbitration order, so as to ensure the ordered execution of the plurality of data transmission requests.
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