CN100338910C

CN100338910C - Method of multi-port received and transmitted packet number statistic in network information exchange

Info

Publication number: CN100338910C
Application number: CNB031320775A
Authority: CN
Inventors: 宋海华; 顾金舵; 刘衡祁
Original assignee: ZTE Corp
Current assignee: ZTE Corp
Priority date: 2003-07-15
Filing date: 2003-07-15
Publication date: 2007-09-19
Anticipated expiration: 2023-07-15
Also published as: CN1571346A

Abstract

The present invention relates to a statistic method of a multi-port received and transmitted packet number in the network information exchange, and a field programmable gate array circuit FPGA is used for packet cache and classified counting in the process of bus conversion. A random access memory RAM is arranged in the FPGA, and particularly, the present invention adopts a result of RAM storage and classified counting in the FPGA. The present invention uses an RAM resource to replace a trigger resource to preserve a counting value of a counter, and thereby, the problem of reducing excess statistics consumption triggers is reached. Finally, resources of a plurality of RAM blocks can replace a large number of consumptive trigger resources, the purpose that an FPGA device with low price can finish the design is reached, and thereby, the cost is reduced.

Description

Multiport transmitting-receiving bag number statistical method in the network information exchange

Technical field:

The present invention relates to a kind of method of in network information exchange, the transmitting-receiving bag number of multiport being carried out statistical counting, relate in particular to the method for when when network processing unit docks with interface chip, needing field programmable gate array circuit FPGA (Field Programmable Gate Array) to carry out the bus conversion transmitting-receiving bag number of multiport being carried out statistical counting.

Background technology:

The bus interface of present most network processing unit does not form unified standard, like this with unavoidably to carry out the bus conversion when interface chip docks.For example the network processing unit IXP1200 of INTEL Corp. has the bus specification IXBUS of oneself, and the bus interface of processor IXP2400 of future generation changes the POSPHY bus interface into.Though and 10/100M Ethernet interface chip has some chips to support above-mentioned bus, support IXBUS as IXF400.But because the design of chip itself, outnumber eight when above in craft port, some indexs can not well meet the demands, and are too much as the mistake bag.

Fig. 1 provides the technical scheme that network processing unit docks with ten six road Ethernets in the prior art.Wherein network processing unit 101 is used to wrap processing, programmable logic device FPGA 102 is used for the bus conversion, ethernet controller MAC 103 is used for physical frame being carried out buffer memory and uploading, and ethernet physical layer chip PHY104 is used to finish the function that physical frame is extracted from physical layer signal.

PHY inserts into ten six road ethernet signals, docks with MAC by RMII bus interface or MII bus interface.MAC converges 16 road Ethernets and docks with FPGA to one tunnel bus interface, and IXFF440 is the IXBUS bus interface.FPGA inside converts this road bus interface to bus that network processing unit is suitable for.At the FPGA place, can carry out the bag buffer memory of some, to replenish the hypodynamic shortcoming of MAC layer buffer capacity.

Need wrap the number statistics to 16 ports at the FPGA place, comprise counting number, the differential counting of packet length and an erroneous packets differential counting.For example, count at type of error, type of error is divided into four kinds of a, b, c, d, and traditional count mode as shown in Figure 2.Counting module 201,202,203 and 204 is respectively a class, b class, c class, the counting unit of d class mistake.Decoder 205 translates the permission count signal of four counters according to the counting type signal of input.Each bag disposes, and all can send to allow count signal and counting type signal, and unify decoding or respectively decoding by decoder this moment, produces the permission count signal of type separately, and each counter is all according to allowing count signal to count.

Fig. 3 has provided the basic model of one 32 digit counter.Label 301 is adders, and label 302 is triggers, Cnt[31:0] and a counting permission position addition, at the rising edge of each clock CLK, Cnt[31:0 is once upgraded in output].In the model of this 32 digit counter, 32 d type flip flop resources have been used.If need add up for four kinds of type of errors of 16 passages in the FPGA design, every kind of type of error has eight kinds of mistakes, needs the resource of 16 * 4 * 8 * 32=16384 trigger so.These resources are to carry out the bus conversion and the resource of consumption, and this just must select the higher FPGA of price, has increased cost.Owing to be the statistics of carrying out at packet, between bag and the bag certain interval is arranged, that is to say that counting is not to add 1 continuously, but several clock just adds 1.Do-nothing operation is too many in the prior art, and the wasting of resources is big; The resource of FPGA inside mainly is LUT (look-up table), trigger, three kinds of resources of RAM.And RAM resource, particularly RAM piece resource all can all not used up in general design.Untapped RAM piece is fallen by unnecessary waste in the bus transformation applications of prior art.

Summary of the invention:

To the objective of the invention is that statistics consumes and slack resources is too much in order overcoming in the prior art, to cause and add up the too high weak point of cost, propose a kind of enhancing hardware resource utilization, the method for increasing work efficiency, reducing cost.After taking all factors into consideration the FPGA resource situation, provided a kind of method that can effectively save trigger resources.

Basic imagination of the present invention is exactly to replace trigger resources to preserve the count value of counter with the RAM resource, reduces the too much problem of trigger that consumes of adding up thereby reach.Finally, can reach and replace largely-consumed trigger resources and being, only reach and promptly can finish the purpose of design, thereby reduce cost with the lower FPGA device of price with several RAM block resources.

Purpose of the present invention can adopt following measure to reach:

Multiport transmitting-receiving bag number statistical method uses field programmable gate array circuit FPGA to wrap buffer memory and differential counting in the bus transfer process in design, a kind of network information exchange of employing; In described FPGA inside random access memory ram is set; It is characterized in that: adopt the RAM among the FPGA to deposit the result of differential counting.

Compare according to design of the present invention, as hardware, and compile with supporting with it ISE4.2 software with the XC2V2000FF896-4 chip of XILING company.Original design needs 16384 triggers to account for 76% trigger resources.Present design is only used less than 200 triggers and 2 RAM pieces, takies 0.93% trigger resources and 3.5% RAM piece resource respectively.By relatively, find to adopt this patent method can save resource greatly.Select for use the XC2V1000FF896-4 of XLINIX company just to finish original design objective at last, the cost savings of FPGA half.When port is too much, use this method can effectively save inner trigger resources.

Description of drawings:

Fig. 1 is the scheme schematic diagram that network processing unit docks with Ethernet;

Fig. 2 is a tradition transmitting-receiving bag counting scheme schematic diagram;

Fig. 3 is the basic composition mode schematic diagram of 32 digit counters;

Fig. 4 is a multiport transmitting-receiving package counting facility scheme schematic diagram in the network information exchange of the present invention;

Fig. 5 is the flow chart of kernel state machine;

Fig. 6 is based on the structural representation of a kind of 16 port counters of the present invention.

Embodiment: embodiments of the invention are described in detail in detail below in conjunction with accompanying drawing.

Multiport transmitting-receiving bag number statistical method uses field programmable gate array circuit FPGA to wrap buffer memory and differential counting in the bus transfer process in a kind of network information exchange; In described FPGA inside random access memory ram is set; It is characterized in that: adopt the RAM among the FPGA to deposit the result of differential counting.

RAM among the FPGA that is adopted both can be centralized random asccess memory (Block RAM), also can be distributed random memory (Distributed RAM).

Allow signal and counting type signal to be translated as the address ram sign indicating number counting that produces in the bus transfer process, and should allow signal to latch;

The address code of described RAM is pointed to the current state buffer that needs the type of counting.

Cpu i/f is set reads described statistical value;

The read signal of described cpu i/f and described address signal are latched respectively, and described address signal is converted into the needed address of RAM.The address field that reads count results in the cpu i/f is corresponding one by one with the address field of count results storing place (RAM), carries out address transition when CPU reads.

This method is provided with the selection mode machine, and the counting of receiver decoder allows the permission information of reading of information and cpu i/f respectively;

Described selection mode machine is distinguished control counter, the RAM among latch and the described FPGA again.

The selection mode facility of described statistical method setting have following job step:

S1, reset and described RAM zero clearing;

S2, judge whether cpu i/f reads; If do not read, change execution in step S4;

S3, read the data among the RAM and latch; Remove the sign that reads of CPU, carry out S2 then;

The counting that produces in S4, the transfer process allows signal need to judge whether counting, if do not need counting, then changes execution in step S2;

S5, from RAM reading of data, promptly former count results;

S6, deposit back among the RAM again after above-mentioned data of reading are added 1;

Remove this count flag, change execution in step S2.

Below technical scheme is described:

The structure of the counter based on RAM of the present invention as shown in Figure 4.Wherein:

Decoder 401 allows signal according to counting, and the current type of counting that needs is translated into address ram.

The current operation of kernel state machine 402 unifieds allocation of resources is finished the CPU reading or is counted.

A RAM 403 is used to keep count status, can deposit count value.

Cpu i/f 404 is used for reading statistical value by cpu i/f.

The data that the signal latch RAM that latch 405 provides according to state machine 402 sends out are so that cpu i/f reads.

After adding 1, the data that the signal that counter 406 provides according to state machine 402 is sent out RAM send among the RAM again.

The operating process of the counter based on RAM of the present invention is as follows:

At first, the counting of coming from the bus conversion allows signal and counting type signal to be translated into the address of RAM, and will allow signal to latch.The state buffer of the type that current needs count is pointed in the address of RAM.For example should translate four addresses for four types according to a, b, c, d.

Because the count status value is to be read out certainly, so must consider the problem that cpu i/f reading of data and counting carry out simultaneously.Here the cpu i/f read signal and the address signal of coming is latched respectively, and address signal will be converted into the needed address of RAM.

More than be preprocessing process, existing in conjunction with Fig. 5, continue to introduce flow process from the angle of state machine 402.

1). after electrification reset finishes, at first need value zero clearing with RAM.

2). judge then whether cpu i/f reads,, continue if read.Do not read, jump to the 4th) step.

3). reading of data from RAM.

Latch current data, supply with cpu i/f and finish read operation.Remove CPU and read sign, turn back to the 2nd) step.

4). judge whether to count, if counting continues.Counting does not turn back to the 2nd) step.

5). reading of data from RAM.

6). data are added 1;

Data after calculating are deposited among the RAM.Remove current count flag, turn back to the 2nd) step.

Wherein RAM can select to use the Block Ram or the DistributedRam of FPGA inside as requested.

Describe the counting that how ethernet frame of 16 ports is carried out two types in detail below in conjunction with Fig. 6, every type is subdivided into eight types.Because it is the 96bit time that ethernet frame requires spacing, so meet the principle that parallel counting is transformed into the serial counting fully.Programming device is selected the XC2V2000 of the VirtexII series of XILINX company for use.The RAM piece uses inner Block Ram, is set to 512 * 32 modes, dual port RAM, two sets of data lines.

Ten six

tunnel decoder

601 and 602 is finished counting permission and the counting type brought for 16 ports and is deciphered, and converts address ram to.

Cpu i/f 603 is used to read the count status value.

State machine 604, dispatch two types respectively its inside.Under each counting type, the mutual repeating query of each port and cpu i/f, selecting current by state machine is who can carry out read-write operation.And each read-write operation all can only be with two clock cycle.

Dual port RAM 605 has two cover address bus and two sets of data buses.

Counter

606 and 607 is counted the data of a port and b port respectively.

Latch 608 is finished read-write operation in order to latch data to cpu i/f.

The scheduling of state machine is described similar with Fig. 5, and only the repeating query port increases.

Claims

1, multiport transmitting-receiving bag number statistical method in a kind of network information exchange uses field programmable gate array circuit FPGA to wrap buffer memory and differential counting in the bus transfer process; In described FPGA inside random access memory ram is set; It is characterized in that:

Decoder allows signal and counting type signal to be translated as the address ram sign indicating number counting that produces in the bus transfer process, deposits the result of differential counting in the described random access memory ram of described address ram sign indicating number correspondence.

2, multiport transmitting-receiving bag number statistical method according to claim 1 is characterized in that: further comprise:

The random access memory ram of described FPGA inside both can be centralized random asccess memory, also can be the distributed random memory.

3, multiport transmitting-receiving bag number statistical method according to claim 2 is characterized in that: further comprise:

Decoder allows signal and counting type signal to be translated as the address ram sign indicating number counting that produces in the bus transfer process, and should allow signal to latch;

The address code of described RAM is pointed to the state buffer of the described random access memory ram of the current type that need count.

4, multiport transmitting-receiving bag number statistical method according to claim 3 is characterized in that:

The data that cpu i/f is used for reading RAM are set;

Described cpu i/f carries out counting operation to the data read among the RAM when reading when finishing;

Described cpu i/f receives cpu address signal and CPU read signal, sends to be converted into the needed address of RAM accordingly and to read to allow signal.

5, multiport transmitting-receiving bag number statistical method according to claim 4 is characterized in that:

The selection mode machine is set, and what the counting of receiver decoder allowed signal and cpu i/f respectively reads to allow signal;

Described selection mode machine is distinguished the RAM among control counter, latch and the described FPGA again.

6, multiport transmitting-receiving bag number statistical method according to claim 5 is characterized in that:

S1, reset and described RAM zero clearing;

S2, judge whether cpu i/f reads; If do not read, change execution in step S4;

S3, read the data among the RAM and latch; Cpu i/f is finished read operation, removes the sign that reads of CPU, and carries out S2 then;

S4, judge whether counting, if counting, if execution in step S5 no count, changes execution in step S2;

S5, from RAM reading of data;

S6, described sense data is added 1 deposit back among the RAM again;

Remove this count flag, change execution in step S2.