CN102404222B - Statistical system of network data messages capable of supporting multiple ports - Google Patents
Statistical system of network data messages capable of supporting multiple ports Download PDFInfo
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- CN102404222B CN102404222B CN201110383669.XA CN201110383669A CN102404222B CN 102404222 B CN102404222 B CN 102404222B CN 201110383669 A CN201110383669 A CN 201110383669A CN 102404222 B CN102404222 B CN 102404222B
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Abstract
The invention provides a statistical system of network data messages capable of supporting multiple ports, comprising a message triggering circuit and a statistical output circuit. The statistical system comprises a piece of statistical equipment. The message triggering circuit, the statistical equipment and the statistical output circuit are connected in turn. The message statistical system adopts an FPGA chip of which the type is 1x130t. The statistical system of the network data messages capable of supporting multiple ports provided by the invention can make a statistic without missing for the data message.
Description
Technical field
The invention belongs to network data transmission field, specifically relate to a kind of network data counting messages system of supporting multiport.
Background technology
Various types of statistics of message are a kind of basic functions of network access equipment.By the various measurement types to message, and convection current quantitative analysis, can the design of discovering network equipment the place of unreasonable or performance bottleneck, be also conducive to some function of optimized network equipment, meet the requirement of client to service quality.For example: network access equipment is processed too much exception message and caused its service performance to reduce, if there are various statistical functions in the key modules of equipment, can find out the place of abnormal cause, and the performance of lifting means meets client's demand.
In the prior art, the most direct message statistical method is the type difference counters design for each port, if there are 24 network ports, and need statistics to receive message total, bad bag number, bag long message, need 24x3x32=2304 trigger resources, this can cause the wasting of resources and the very difficult problem of convergence sequential.
The patent No. be ZL03132077.5, name is called a kind of method that has disclosed counting messages in the invention of " multiport transmitting-receiving bag number statistical method in network information exchange ", it can add up the quantity of 16 port ethernet messages; But there is following drawback in its implementation:
That first with the ram that blockram generates, take is xilinx fpga 18KBRAMs, and this resource only exists in the specify columns of fpga inside, if limit with statistical function in this position around, timing closure that will certainly docking port end brings serious problems;
Secondly, after the data that the signal that the counter 406 of this invention provides according to state machine 402 is sent RAM add 1, send into again in RAM, be that this invention can only once trigger the type of skill in address, but in network insertion, if the input of each port data bag is random when 16 ports are when the clock cycle has counting demand in the same time at a time, can not count a plurality of ports simultaneously.
Finally, this invention limits it and uses objective network to be divided into the Ethernet of 96bit for interframe, if the encapsulation format of objective network is PPP frame, namely interframe is divided into minimum 8bit, there will be the problem that can not count.
Summary of the invention
For overcoming above-mentioned defect, the invention provides a kind of network data counting messages system of supporting multiport, can exhaustively add up data message.
For achieving the above object, the invention provides a kind of network data counting messages system of supporting multiport, it comprises: message circuits for triggering and statistics output circuit, its improvements are, described statistical system comprises statistics equipment, and described message circuits for triggering, described statistics equipment and described statistics output circuit are connected successively.
In optimal technical scheme provided by the invention, described message circuits for triggering, comprising: and the 1bit of network access port coupling controls trigger CtrlTrig and connected N bit data trigger DataTrig; Wherein, N is less than or equal to 16 natural number.
In the second optimal technical scheme provided by the invention, described statistics equipment, comprising: cpu address decoding circuit, address latch change-over circuit, CPU read pulse register circuit, triggering accumulative total circuit, counter wheel shifting circuit and memory buffer; Described cpu address decoding circuit, described address latch change-over circuit and described triggering accumulative total circuit are connected successively; Described CPU read pulse register circuit, described triggering accumulative total circuit, described counter wheel shifting circuit are connected successively with described memory buffer; Described triggering accumulative total circuit is connected with described message circuits for triggering, and described CPU read pulse register circuit sends CPU to described statistics output circuit and reads valid data.
In the 3rd optimal technical scheme provided by the invention, the N value of described N bit data trigger DataTrig is set at 1 o'clock, and accounting message type is counted; Otherwise accounting message byte is counted.
In the 4th optimal technical scheme provided by the invention, described cpu address decoding circuit is that triggering signal is read in described statistics equipment generation.
In the 5th optimal technical scheme provided by the invention, described memory buffer is dual port RAM, and described dual port RAM adopts LUT RAM structure.
In the 6th optimal technical scheme provided by the invention, described counter wheel shifting circuit is stored the decode results of the address bus RdAddress of described memory buffer, and after the data that event memory and current period are read are added, in next cycle, write described LUT RAM; Described counter wheel shifting circuit is corresponding one by one with the address bus RdAddress of described memory buffer.
In the 7th optimal technical scheme provided by the invention, described counting messages system is used the fpga chip that model is lx130t.
Compared with the prior art, a kind of network data counting messages system of supporting multiport provided by the invention, can save the memory source of fpga inside, and the position of statistical circuit can arbitrarily move with interface position, has avoided restraining serious problem in sequential; And be not limited to certain procotol, not only can, for Ethernet, can also, for SDH system, go for the Frame of different size encapsulation; Moreover, can exhaustively add up data message; Finally, can to the data message of a plurality of ports, add up simultaneously.
Accompanying drawing explanation
Fig. 1 is the structural representation of network data counting messages system.
Fig. 2 is the sequential chart that CPU reads address n.
Fig. 3 is the parcel sequential chart that 20 ports of network receive 28bytes simultaneously.
Embodiment
As shown in Figure 1, support the network data counting messages system of multiport, it comprises: message circuits for triggering and statistics output circuit, and described statistical system comprises statistics equipment, described message circuits for triggering, described statistics equipment and described statistics output circuit are connected successively.Described counting messages system is used the fpga chip that model is lx130t.
In the second optimal technical scheme provided by the invention, described statistics equipment, comprising: cpu address decoding circuit, address latch change-over circuit, CPU read pulse register circuit, triggering accumulative total circuit, counter wheel shifting circuit and memory buffer; Described cpu address decoding circuit, described address latch change-over circuit and described triggering accumulative total circuit are connected successively; Described CPU read pulse register circuit, described triggering accumulative total circuit, described counter wheel shifting circuit are connected successively with described memory buffer; Described triggering accumulative total circuit is connected with described message circuits for triggering, and described CPU read pulse register circuit sends CPU to described statistics output circuit and reads valid data.
The network data counting messages system of described support multiport, utilize the memory buffer of the inner distributed ram resource construction of fpga, design a kind of support objective network and transplant simple, function of unity and exhaustively install, its structure comprises message circuits for triggering, cpu address decoding circuit, statistical circuit and statistics output circuit.
Described message circuits for triggering, for each network access port design, a 1bit controls trigger CtrlTrig and a N bit data trigger DataTrig, wherein, 1 <=N <=16; When CtrlTrig is effective, namely during high level, mean that DataTrig data are effectively, namely the outer principle of controlling of band simultaneously; When statistical function module is only carried out certain number of types statistics of message, DataTrig is 1bit data trigger, namely N=1; When statistical function needs accounting message byte, N ≠ 1, for example 16, can statistical length be 65535 bag is long, for this counting step of all-network environment, be satisfiable, design can be according to the value of the restriction simple modification N of maximum message size in own network environment;
Described cpu address decoding circuit, produces the triggering signal of reading of statistical function module utilization;
Described statistical circuit is the core of supporting the network data counting messages system of multiport:
1), its function can realize the statistics of single triggering signal and the statistical function of data/address bus, the situation of DataTrig register N > 1 namely;
2), memory buffer adopts dual port RAM to realize, the realization of RAM adopts the LUT of fpga to build, for example realize the RAM piece of a width 48bit, the degree of depth 32,48 Iut resources have only been used, more to one's profit than tens blockram resources of resource-constrained, and the Iut resource of fpga can reach even hundreds thousand of ranks up to ten thousand;
3), described CPU read pulse register circuit, make CPU read enable signal and for certain statistical function module, only have the pulse of a clock cycle, we carry out this pulse to deposit use twice, are designated as ReadDly0, ReadDly1; When output valid reading certificate is ReadDly1 high level, CPU is the statistics of current output;
4), as shown in Figure 2, when having read pulse Read to occur, CPU read pulse register circuit is latched into address ram bus RdAddress the address register value CpuRdAddr that reads of address decoding circuitry input, at ReadDly0, constantly " adding one " operation is carried out in the address in cycle on address bus RdAddress, and other cycles RdAddress repeats " adding one " operation; Meanwhile, address ram write decoder latch cicuit clock for multiport is in running order, namely utilize a counter wheel shifting circuit to store according to the decode results of RdAddress current measurement type pulse, the data that event memory and current period are read are carried out " add operation ", in next cycle, write RAM, the object of doing is like this while preventing that the read cycle from occurring, occurs leaking the phenomenon of statistics; The number of PktTypeCnt register is namely set according to the quantity of the network port, as 24 network interfaces, design 24 PktTypeCnt registers, the corresponding PktTypeCnt register of each address ram, when having type statistics to trigger and when ReadDly0 is invalid, carries out " putting one " operation according to RdAddress address to it, if triggering, type lost efficacy, carry out " zero setting " operation, if during without read request, carry out " adding one " operation;
5), all statistics of RAM of this device are all the basic operations based on RAM, core is exactly a plurality of counter wheel shifting circuits of design and being used in conjunction with of RdAddress address decoding circuitry; When an accounting message type is counted, the N value of DataTrig is set to 1 and does " with operation " with CtrlTrig, when carrying out the comprehensive step of fpga, has naturally saved the register resources of half like this; That when handover network, only need consider to exist in this network environment plays bag long most, for example, when access SDH system, suppose the minimum 28Byte of being of minimum PPP frame, if during 20 mouthfuls of port numbers, exhaustively statistics that can linear speed, Fig. 3 is the sequential charts of a kind of 20 ports when receiving the parcel of 28bytes simultaneously and triggering type of message counting in a certain clock cycle simultaneously.
Need statement, content of the present invention and embodiment are intended to prove the practical application of technical scheme provided by the present invention, should not be construed as limiting the scope of the present invention.Those skilled in the art inspired by the spirit and principles of the present invention, can do various modifications, be equal to and replace or improve.But in the protection range that these changes or modification are all awaited the reply in application.
Claims (6)
1. a network data counting messages system of supporting multiport, it comprises: message circuits for triggering and statistics output circuit, it is characterized in that, described statistical system comprises statistics equipment, and described message circuits for triggering, described statistics equipment and described statistics output circuit are connected successively;
Described message circuits for triggering, comprising: and the 1bit of network access port coupling controls trigger CtrlTrig and connected N bit data trigger DataTrig; Wherein, N is less than or equal to 16 natural number;
Described statistics equipment, comprising: cpu address decoding circuit, address latch change-over circuit, CPU read pulse register circuit, triggering accumulative total circuit, counter wheel shifting circuit and memory buffer; Described cpu address decoding circuit, described address latch change-over circuit and described triggering accumulative total circuit are connected successively; Described CPU read pulse register circuit, described triggering accumulative total circuit, described counter wheel shifting circuit are connected successively with described memory buffer; Described triggering accumulative total circuit is connected with described message circuits for triggering, and described CPU read pulse register circuit sends CPU to described statistics output circuit and reads valid data.
2. counting messages system according to claim 1, is characterized in that, the N value of described N bit data trigger DataTrig is set at 1 o'clock, and accounting message type is counted; Otherwise accounting message byte is counted.
3. counting messages system according to claim 1, is characterized in that, described cpu address decoding circuit is that triggering signal is read in described statistics equipment generation.
4. counting messages system according to claim 1, is characterized in that, described memory buffer is dual port RAM, and described dual port RAM adopts LUT RAM structure.
5. counting messages system according to claim 1, it is characterized in that, described counter wheel shifting circuit is stored the decode results of the address bus RdAddress of described memory buffer, and after the data that event memory and current period are read are added, in next cycle, writes LUT RAM; Described counter wheel shifting circuit is corresponding one by one with the address bus RdAddress of described memory buffer.
6. counting messages system according to claim 1, is characterized in that, described counting messages system is used the fpga chip that model is lx130t.
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| CN201110383669.XA CN102404222B (en) | 2011-11-28 | 2011-11-28 | Statistical system of network data messages capable of supporting multiple ports |
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| CN107977327A (en) * | 2017-11-24 | 2018-05-01 | 中国航空工业集团公司西安航空计算技术研究所 | The circuit of multi-port memory cells is realized in a kind of FPGA using two-port RAM |
| CN108833203B (en) * | 2018-05-23 | 2021-04-30 | 新华三信息安全技术有限公司 | Message statistical method and device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0895376A2 (en) * | 1997-08-01 | 1999-02-03 | Hewlett-Packard Company | Method and apparatus for collecting information on use of a packet network |
| CN1571346A (en) * | 2003-07-15 | 2005-01-26 | 中兴通讯股份有限公司 | Method of multi-port received and transmitted packet number statistic in network information exchange |
| CN1601975A (en) * | 2004-09-29 | 2005-03-30 | 重庆邮电学院 | Packet-switcher flow monitoring and inquiry method and line card picker |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0895376A2 (en) * | 1997-08-01 | 1999-02-03 | Hewlett-Packard Company | Method and apparatus for collecting information on use of a packet network |
| CN1571346A (en) * | 2003-07-15 | 2005-01-26 | 中兴通讯股份有限公司 | Method of multi-port received and transmitted packet number statistic in network information exchange |
| CN1601975A (en) * | 2004-09-29 | 2005-03-30 | 重庆邮电学院 | Packet-switcher flow monitoring and inquiry method and line card picker |
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