CN102377660A - Cell transmission method and device - Google Patents
Cell transmission method and device Download PDFInfo
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- CN102377660A CN102377660A CN2010102604351A CN201010260435A CN102377660A CN 102377660 A CN102377660 A CN 102377660A CN 2010102604351 A CN2010102604351 A CN 2010102604351A CN 201010260435 A CN201010260435 A CN 201010260435A CN 102377660 A CN102377660 A CN 102377660A
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Abstract
The invention discloses a cell transmission method and a cell transmission device. The method comprises the following steps of: acquiring first abnormal information from a cell to be transmitted; acquiring second abnormal information of the cell in a process that an asynchronous first in first out (FIFO) channel transmits the cell; and determining whether to abandon the cell according to the first abnormal information and the second abnormal information. By the method and the device, stable, reliable and asynchronous FIFO transmission is realized.
Description
Technical field
The present invention relates to the communications field, in particular to a kind of information element transmission method and device.
Background technology
In router chip design, very high to the stability requirement of system, this just requires data error in data in inter-process and transmission course, can not occur to cause systemic breakdown.The interface of exchange chip all is to adopt high-speed interface usually, like the SerDes interface etc., and usually the inter-process clock of chip go up the clock that uses with interface IP can be different, this just relates to cross clock domain handling problem of data.And normally be that unit is operated with the cell in the data of exchange, how to guarantee the correct transmission of data, and how to eliminate this mistake under the situation about making a mistake the influence of system level is seemed particularly important.
FIFO (First In First Out abbreviates FIFO as) or random access device (Random Access Memory abbreviates RAM as) are used in the router chip in a large number.There is error probability in this RAM in the process of read-write.Though probability of errors is very little, and it is littler to occur the probability of many bits (bit) mistake simultaneously, for the equipment of router, owing to require system works highly stable, thus it is also extremely low to require unusual probability to occur.For this reason, just must consider that the bit mistake takes place RAM and influence that system is caused.Through adopting error-checking code (Error Correction Code; Abbreviating ECC as) the RAM mode corrects a spot of bit mistake; Perhaps monitor the generation (the ECC mode also can be used as a kind of monitoring means and uses) of bit mistake with parity check; Through processing, avoid factor to cause influence according to mistake to system to monitoring result.From the design level of chip, mostly is to evade problem from design level.
Fig. 1 is the sketch map according to the common form of the bag of correlation technique or cell; As shown in Figure 1; Router class chip for transmitting with the form of cell (being not limited to cell, to wrapping same being suitable for) all can relate to the information that header carries cell usually; And cell all can have polytype to exist usually, and their information all embodies in header.Therefore, correct header is the key of correctly cell being handled.
In RAM, in the access, if send bit mistake (it is more limited to carry the wrong influence of payload transmission, can not pay close attention to) in the header position, cause the information misjudgment to cell at cell data, this will produce the influence that can not estimate to system.This influence is little to be abandoned to a plurality of cells, arrives flow sudden change even cutout greatly.
Said as the front, all can relate to the cross clock domain problem usually at the outlet side of chip, so inevitable introducing an asynchronous FIFO.
In the read-write control of asynchronous FIFO; Usually can face some problems: might be in the cross clock domain process after the Gray code conversion of address in the asynchronous FIFO because sequence problem causes sampling unusual; Thereby cause asynchronous FIFO sky, full or with empty, will completely indicate can not be promptly and accurately the reaction fifo status, this also is all only to use sky usually in the design, will expire to come design circuit.And if FIFO is read sky, if judge with empty sign, it is too poor that then reliability is gone up in design.
Transmit because data all are with bag or cell is as a whole, because the data bus bandwidth problem needs clap could transmit a bag or cell usually.This just means that a bag or cell are divided into several groups and are stored among the RAM.How can accurately complete packet or the cell of a RAM be read; Usually the method that adopts is: read after the head of cell; Judge that according to information in the header this bag or cell have much; Thereby reading side counting, wait for and promptly think that a complete packet reads after count, thereby whether judgement is continuing the read operation of a new bag or cell at the back.
The inventor finds, if the cell error of transmission, the transport address pointer that will cause transmitting in the asynchronous FIFO passage of this cell is out of order, can't recover, and then will cause follow-up all errors of transmission of all cells through this asynchronous FIFO channel transfer.
Summary of the invention
Main purpose of the present invention is to provide a kind of information element transmission method and device, with follow-up all cells through the asynchronous FIFO channel transfer of solving that above-mentioned cell error of transmission causes problem of error of transmission all.
To achieve these goals, according to an aspect of the present invention, a kind of information element transmission method is provided.
Information element transmission method according to the present invention comprises: obtain first abnormal information in the cell waiting for transmission; In the process of cell being transmitted through asynchronous FIFO FIFO passage, obtain second abnormal information of cell; According to first abnormal information and second abnormal information, determine whether cell is abandoned.
Further, it is effective that first abnormal information and second abnormal information are high level, according to first abnormal information and second abnormal information, cell abandoned comprises: first abnormal information and second abnormal information are carried out or calculated, obtain the 3rd abnormal information; According to the 3rd abnormal information, cell is abandoned.
Further, according to the 3rd abnormal information, cell abandoned comprise: first check information that generates cell; According to the 3rd abnormal information first check information is carried out scrambling; Judge whether first check information after the scrambling is correct, if judged result then abandons cell for not.
Further, according to the 3rd abnormal information first check information being carried out scrambling comprises: according to the 3rd abnormal information to the first check information negate.
Further; First abnormal information of obtaining cell waiting for transmission comprises: obtain second check information of importing simultaneously with cell waiting for transmission, judge whether second check information is correct, if judged result is for denying; Then, obtain first abnormal information according to second check information; If judged result judges then for being whether the type of cell waiting for transmission is correct, if judged result then obtains first abnormal information for not; If judged result judges then for being whether the form of cell waiting for transmission is identical with the form of the type that is provided with in advance,, then obtain first abnormal information if judged result is not.
Further, second abnormal information of obtaining cell comprises: judge whether presence bit mistake of random access device RAM; If judged result for being, then according to bit-errors, is obtained second abnormal information.
Further, said method also comprises: use cell, the unlatching of control asynchronous FIFO passage or close.
Further, it is characterized in that after obtaining first abnormal information of cell waiting for transmission, said method also comprises: first abnormal information and cell are transmitted through the asynchronous FIFO passage jointly.
Further, after obtaining first abnormal information of cell waiting for transmission, said method also comprises: head sign and the afterbody sign of obtaining cell; Head sign and afterbody sign are transmitted through the asynchronous FIFO passage with cell jointly.
Further, the afterbody sign is placed second that begins from the highest order of cell, and transmit through the asynchronous FIFO passage jointly with cell.
To achieve these goals, according to another aspect of the present invention, a kind of cell transmitting device is provided.
Cell transmitting device according to the present invention comprises: pretreatment module is used for obtaining first abnormal information of cell waiting for transmission; Asynchronous FIFO fifo module, be used for through the asynchronous FIFO passage to the process that cell transmits, obtain second abnormal information of cell; Processing module is used for according to first abnormal information and second abnormal information cell being abandoned.
Through the present invention; Employing is according to the abnormal information in cell and the transmission course thereof; It is abandoned, and follow-up all cells through the asynchronous FIFO channel transfer that solved that the cell error of transmission causes are the problem of error of transmission all, and then realizes reliable and stable asynchronous FIFO transmission.
Description of drawings
Accompanying drawing described herein is used to provide further understanding of the present invention, constitutes the application's a part, and illustrative examples of the present invention and explanation thereof are used to explain the present invention, do not constitute improper qualification of the present invention.In the accompanying drawings:
Fig. 1 is the sketch map according to the common form of the bag of correlation technique or cell;
Fig. 2 is the flow chart according to the information element transmission method of the embodiment of the invention;
Fig. 3 is the header information (soc) according to the embodiment of the invention, the sketch map of the position relation of trailer information (eoc) and abnormal information (err) and cell;
Fig. 4 is the structured flowchart according to the cell transmitting device of the embodiment of the invention;
Fig. 5 is the structured flowchart of cell transmitting device according to the preferred embodiment of the invention;
Fig. 6 is a sketch map of importing the sequential of cell according to the preferred embodiment of the invention;
Fig. 7 is the sketch map of bus bit width conversion according to the preferred embodiment of the invention;
Fig. 8 is the sketch map that unusual according to the preferred embodiment of the invention cell generates the sequential of check information;
Fig. 9 is the sketch map of the data output of check information generation module according to the preferred embodiment of the invention.
Embodiment
Hereinafter will and combine embodiment to specify the present invention with reference to accompanying drawing.Need to prove that under the situation of not conflicting, embodiment and the characteristic among the embodiment among the application can make up each other.
The objective of the invention is in the asynchronous clock domain transmission course, to cause the switching system paralysis because of error in data takes place in the RAM read-write in order to overcome bag or cell; Provide a kind of reliable and stable realization to the asynchronous FIFO read/writing control method, also provide a kind of simple simultaneously effectively to the implementation of the discard processing of unusual bag or cell.
According to embodiments of the invention, a kind of information element transmission method is provided.Fig. 2 is the flow chart according to the information element transmission method of the embodiment of the invention, and is as shown in Figure 2, and this method comprises that following step S202 is to step S206.
Step S202 obtains first abnormal information in the cell waiting for transmission.
Step S204 in the process of cell being transmitted through the asynchronous FIFO passage, obtains second abnormal information of cell.
Step S206 according to first abnormal information and second abnormal information, determines whether cell is abandoned.
In the correlation technique, if the cell error of transmission, the transport address pointer that will cause transmitting in the asynchronous FIFO passage of this cell is out of order, and then will cause follow-up all errors of transmission of all cells through this asynchronous FIFO channel transfer.In the embodiment of the invention; First abnormal information can be used for judging whether this cell exists mistake in the data processing of up-stream module; Second abnormal information can be used for judging whether this cell exists mistake in the process through the asynchronous FIFO passage; Then cell is abandoned, can avoid this cell, and then realize reliable and stable asynchronous FIFO transmission the follow-up influence of passing through all cells of this asynchronous FIFO channel transfer.
Preferably, it is effective that first abnormal information and second abnormal information are high level, according to first abnormal information and second abnormal information, cell abandoned comprises: first abnormal information and second abnormal information are carried out or calculated, obtain the 3rd abnormal information; According to the 3rd abnormal information, cell is abandoned.
In this preferred embodiment; Because it is effective that first abnormal information and second abnormal information are high level; The 3rd abnormal information of therefore first abnormal information and second abnormal information being carried out or calculating can embody the information in first abnormal information and second abnormal information simply and easily.
Need to prove; Above-mentioned first abnormal information and second abnormal information are set and obtain the 3rd abnormal information can also adopt other method; First abnormal information and second abnormal information for example are set, and to be low level effective; Corresponding simultaneously, first abnormal information and second abnormal information are carried out and the 3rd abnormal information that calculates.Therefore, in the practical application, the method that any realization abnormal information that can embody design philosophy of the present invention is handled all should be included protection scope of the present invention in.
Preferably, according to the 3rd abnormal information, cell abandoned comprise: first check information that generates cell; According to the 3rd abnormal information first check information is carried out scrambling; Judge whether first check information after the scrambling is correct, if judged result then abandons cell for not.
First check information can be used for upstream device and receive after the cell, judges whether this cell is correct.In this preferred embodiment; Through first check information is carried out scrambling, can the abnormal information of cell be embodied in this first check information, like this; It is incorrect that the verification meeting that upstream device carries out cell first check information obtains check results, and this cell can abandon in downstream like this.This method that abandons unusual cell in the outlet side unification can be wasted resource hardly, and is effectively simple.
Preferably, according to the 3rd abnormal information first check information being carried out scrambling comprises: according to the 3rd abnormal information to the check information negate.
In this preferred embodiment, after first check information that generates cell, with this first check information negate.This implementation is simple, reliable.
Preferably; First abnormal information of obtaining cell waiting for transmission comprises: obtain second check information of importing simultaneously with cell waiting for transmission, judge whether second check information is correct, if judged result is for denying; Then, obtain first abnormal information according to second check information; If judged result judges then for being whether the type of cell waiting for transmission is correct, if judged result then obtains first abnormal information for not; If judged result judges then for being whether the form of cell waiting for transmission is identical with the form of the type that is provided with in advance,, then obtain first abnormal information if judged result is not.
The process of obtaining first abnormal information has been described in this preferred embodiment.Comprise in second check information of importing simultaneously with cell waiting for transmission and be used for judging whether this cell exists the information of mistake in the data processing of up-stream module; Therefore obtain first abnormal information according to second check information, fully taken into account the influence of up-stream module the cell transmission.Simultaneously, whether this locality has been preserved the form of type and the type of cell in advance, correct through type and the form thereof of judging cell waiting for transmission, thereby on each transmission link, has guaranteed the correctness and the reliability of the transmission of cell asynchronous FIFO.
Preferably, second abnormal information of obtaining cell comprises: judge whether presence bit mistake of RAM; If judged result for being, then according to bit-errors, is obtained second abnormal information.
This preferred embodiment has been described in the process of said cell being transmitted through the asynchronous FIFO passage, obtains the process of second abnormal information.If RAM presence bit mistake is then obtained second abnormal information according to bit-errors, can guarantee in time to obtain the error of transmission of cell, thereby guarantee the correct transmission of cell.
Preferably, said method also comprises: use the unlatching of this cell control asynchronous FIFO passage or close.
In this preferred embodiment, the unlatching through control asynchronous FIFO passage or close can be controlled reading of asynchronous FIFO passage, reads empty problem thereby solved this asynchronous FIFO passage.
Preferably, after obtaining first abnormal information of cell waiting for transmission, first abnormal information and cell are transmitted through the asynchronous FIFO passage jointly.
Preferably, after obtaining first abnormal information of cell waiting for transmission, obtain the head sign and the afterbody sign of cell; Head sign, afterbody sign, first abnormal information and cell are transmitted through the asynchronous FIFO passage jointly.
In this preferred embodiment, generate the head sign (soc) and the afterbody sign (eoc) of cell, then this head sign (soc), afterbody sign (eoc) and first abnormal information (err) companion data are write FIFO together.Like this, the reading side and can judge whether to begin cell is read of asynchronous FIFO through judging this head sign (soc), and through judging that this afterbody identifies (eoc) and judges whether cell has read and finish, thereby the correct transmission of assurance cell.
Need to prove,, can on the bit wide of cell, increase 3bit in order to transmit above-mentioned head sign (soc), afterbody sign (eoc) and first abnormal information (err).Simultaneously, preferably, with above-mentioned head sign (soc), afterbody sign (eoc) and first abnormal information (err) as the part of cell data together computation of parity bits or ECC.
Preferably, the afterbody sign is placed second that begins from the highest order of cell, and transmit through the asynchronous FIFO passage jointly with cell.
Because read data reads to enable a late beat, read by the time afterbody sign (eoc) afterwards next time read data read enable to provide.In this preferred embodiment, afterbody sign (eoc) is placed on the penult position of cell, can avoids above-mentioned read data to read to enable late problem.Fig. 3 is the header information (soc) according to the embodiment of the invention, the sketch map of the position relation of trailer information (eoc) and abnormal information (err) and cell is as shown in Figure 3, has just described the locational situation of penult that afterbody sign (eoc) is placed on cell.
Preferably, based on the design philosophy of this preferred embodiment, can also eoc sign be placed on third from the bottom the position or a fourth from the last position of cell.
In the correlation technique,,, the number beat judges whether complete reading of bag thereby bringing with empty or obtain cell length through the header type.In this preferred embodiment; Can judge whether complete reading of bag accurately through eoc sign, generate and lag behind and header itself makes a mistake when reading and causes judging by accident the problem that causes the FIFO pointer out of order thereby broken away from empty that Gray code causes because of sequence problem.
The embodiment of the invention provides a kind of cell transmitting device, and this cell transmitting device can be used to realize above-mentioned information element transmission method.Fig. 4 is according to the structured flowchart of the cell transmitting device of the embodiment of the invention, comprises pretreatment module 42, asynchronous FIFO module 44 and processing module 46.Be described in detail in the face of its structure down.
Pretreatment module 42 is used for obtaining first abnormal information of cell waiting for transmission; Asynchronous FIFO module 44, be used for through the asynchronous FIFO passage to the process that cell transmits, obtain second abnormal information of cell; Processing module 46 is connected to pretreatment module 42 and asynchronous FIFO module 44, and second abnormal information that first abnormal information that is used for obtaining according to pretreatment module 42 and asynchronous FIFO module 44 are obtained abandons cell.
In the correlation technique, if the cell error of transmission, the transport address pointer that will cause transmitting in the asynchronous FIFO passage of this cell is out of order, and then will cause follow-up all errors of transmission of all cells through this asynchronous FIFO channel transfer.In the embodiment of the invention; First abnormal information can be used for judging whether this cell exists mistake in the data processing of up-stream module; Second abnormal information can be used for judging whether this cell exists mistake in the process through the asynchronous FIFO passage; Then cell is abandoned, can avoid this cell, and then realize reliable and stable asynchronous FIFO transmission the follow-up influence of passing through all cells of this asynchronous FIFO channel transfer.
Need to prove that the cell transmitting device of describing among the device embodiment is corresponding to above-mentioned method embodiment, its concrete implementation procedure had been carried out detailed description in method embodiment, repeat no more at this.
In order to help to understand the foregoing description, further describe other a plurality of preferred embodiments of the present invention below.
Cell transmitting device of the present invention is made up of six parts, is respectively: pretreatment module (pre_process), asynchronous FIFO module (async_fifo), FIFO control module (fifo_ctrl), check information production module (check_gen), link form generation module (format_gen) and coding module (encode).Four parts in front key component that is apparatus of the present invention wherein.The functional description of each module is following:
1, pretreatment module has realized the extraction to control information, generates soc, eoc and err signal, prepares for cell data writes async_fifo.
So-called extraction to control information comprises the extraction of front about the abnormal information of cell, and inner integral body to cell detects judgement, guarantees that the cell that writes does not have illegal cell.
2, the asynchronous FIFO module promptly realizes the translation function of cross clock domain.
3, the FIFO control module has realized the control to FIFO, and the data of output are handled, and controls the opening and closing of reading to enable according to the information of sense data, is the pith of whole contrive equipment.
4; Check information production module has realized the generation to the check information of output cell; The unusual cell sign that provides according to the prime module simultaneously carries out scrambling to the check information of the cell of accomplishing verification, makes unusual cell realize abandoning indirectly unusual cell because of check errors in downstream.
5, link form generation module has realized sending the generation of the link form of cell.Mainly be the control signal that provides according to prior module, realize the conversion of link form.
6, it can be a universal standard module to sending the coding of data that coding module is realized.Make the DC level of the data of sending on the SerDes link reach balance through coding.
Because clock frequency; The characteristic of data/address bus broadband and transmit cell is different; The size of employed asynchronous FIFO is different with various threshold setting meetings, and present embodiment is intended to introduce soc, the eoc utilization in design, and the dynamic-configuration that how to realize cell number on the link.
In view of the design consideration frequency and the bandwidth of asynchronous FIFO has much relations, they are directly connected to the key technology points such as the degree of depth and threshold setting of FIFO.
Be elaborated below in conjunction with preferred embodiment and accompanying drawing implementation procedure to the foregoing description.
Preferred embodiment one
Because clock frequency; The characteristic of data/address bus broadband and transmit cell or bag is different; The size of employed asynchronous FIFO is different with various threshold setting meetings; This preferred embodiment one is intended to introduce soc, the eoc utilization in design, and the dynamic-configuration that how to realize cell number on the link.
Present embodiment is with the description of sending of cell, and wherein cell relates to polytype, is not isometric on the length of cell.The clock of writing side of async_fifo is designated as sys_clk, and frequency is 250MHz, and the bus broadband is 32bit, and a cell writes and all needs a plurality of clock cycle to accomplish., suppose cell divided data cell and two kinds of control cells here, size is respectively 144 bytes and 24 bytes, promptly needs 36 clock cycle and 6 clock cycle to accomplish respectively.Suppose that can send a kind of special cell under the valid cell situation that ought need not send transmits effective information, thereby fill the cell on the link, promptly the data of input are continual for async_fifo.The clock of reading side of async_fifo is designated as ref_clk, and frequency is 312.5MHz, and the output bus broadband of fifo_ctrl module is 16bit.Related standard asynchronous FIFO size is 64wx35b, has called the RAM (the big or small 64wx36b of RAM, it is parity check bit that 1bit is wherein arranged) of a tape parity check function.FIFO's is 4 with sky (almost_empty) thresholding, and will expire (almost_ful) thresholding is 16.The writing of FIFO overflows that to evade be that the signal of will expiring through FIFO comes back-pressure prime module, makes it stop to export cell.The mode of prime module responds back-pressure is to come back-pressure by cell, promptly writes under the situation of a part when receiving back-pressure at cell, waits cell to write and just responds back-pressure afterwards.
Describe with regard to the performing step of various piece below:
1. data to be transmitted is delivered to this device portal through handling.Because the up-stream module of this device possibly also have resources such as using RAM when data processing, can exist RAM to produce the problem of bit mistake, certainly, can also comprise the state information in other processing procedures, whether identify this cell unusual.
Fig. 6 is a sketch map of importing the sequential of cell according to the preferred embodiment of the invention; After receiving such cell and relevant information thereof; Through dat_vld signal shown in Figure 6 is extracted rising edge pulse and trailing edge pulse; Carry out suitable time-delay through register pair pulse and data again, can obtain the phase relation (soc aligns with header, the penult alignment of data of eoc and cell) of soc, eoc sign and expectation.
In the header position, header information is judged, judged result is merged abnormal information that cell carries together, generate the err sign.
2. soc, eoc and the err of front generation are placed on the high 3bit position of data, together write asynchronous FIFO as wr_data.In asynchronous FIFO inside, call the RAM of a tape parity check, generate corresponding check digit according to write data, together write RAM with data; Simultaneously the data of RAM output are carried out parity check, produce the check results indication.
3. in the side of reading of asynchronous FIFO, at first according to the enabling signal that idle cell almost_empty is used as reading side of FIFO.This signal only triggers once under current embodiment, because it is wide less than writing port band width to read blanking bar, reads empty situation (because the prime module can produce special cell and fill the cell that sends on the link) so for reading mouth, occur FIFO never.Enabling signal triggers the FIFO control module and starts working.
4.FIFO what control module produced FIFO reads to enable rd_en.Because the bus bit wide becomes 16bit by original 32bit, so read operation is to read just to read next time at a distance from a bat after the bat.
5. the next clock cycle after reading to enable to provide, data fifo is read.Consider that the data fifo time-delay of coming out is bigger, so as triggering data fifo is played a bat with register with the time delayed signal of reading to enable (rd_en_dly1), the clooating sequence of writing side according to FIFO is then separated soc, eoc, err and cell data.At the ref_clk clock zone, the credit data of separating is designated as cell_data_dly, and soc that separates and eoc are designated as soc_rd and eoc_rd respectively, and these two signs all are processed into pulse signal.
6. Fig. 7 is the sketch map of bus bit width conversion according to the preferred embodiment of the invention, and data cell_data_dly through processing shown in Figure 7, is become bus 16bit with the data transaction of bus 32bit, obtains the data output cfo_data of cfo_data.
Fig. 8 is the sketch map that unusual according to the preferred embodiment of the invention cell generates the sequential of check information; The err sign that RAM parity check result and FIFO read mutually or; Generate a new error flag; With the data same path of becoming deformed, whether companion data output has (like the dat_err among Fig. 8) unusually as the sign current data.Soc, eoc sign follow cfo_data to export together through handling as the index signal of the real head and tail of exporting cell, are designated as cell_hd and cell_tail respectively.
7. the verification mode of supposition check information production module is to come verification through generating the CRC position, and wherein the bit number of CRC is 16bit.The check information generation module is delimited cell according to cell_hd and cell_tail, accomplishes crc and generates, and be filled into the crc position of cell.The wherein zero clearing of header information cell_hd control CRC, the insertion in cell of cell tail information cell_tail control CRC.In check information generation module dateout; If it is effective to detect dat_err; Then data are carried out all bits and overturn as exporting to back level module, receive the result that will draw the crc check errors when cell carries out the crc verification in downstream module like this, cell can be dropped; Thereby realized that indirect cell abandons, can the additional waste resource.
Fig. 8 is the sketch map that unusual according to the preferred embodiment of the invention cell generates the sequential of check information; Fig. 9 is the sketch map of the data output of check information generation module according to the preferred embodiment of the invention, and this Fig. 8, Fig. 9 just show the process that above-mentioned cell abandons.
Control informations such as cell_vld, cell_hd and cell_tail continue to transmit with data backward, bring convenience for the control of other logics.
8. after the processing of cell through production of link form and coding module, cell sends through interface.
In the foregoing description, change 16bit, make that reading to enable is intermittent providing, promptly read a bat and stop a bat, and then read a bat because the sense data of asynchronous FIFO need be carried out 32bit.Very well-to-do of processing time when response eoc signal.For reading to enable is situation about providing continuously, lags behind the situation of reading to enable in order to avoid eoc, also can this label of eoc be beaten on a third from the bottom or fourth from the last data of cell or bag in the side of writing of asynchronous FIFO, and the thought of design is the same.
When position that parity check makes a mistake is on soc or eoc bit; Cause soc or eoc to lose; This device meeting generation cell is unusual in this case, and two adjacent cells all can abandon because crc verification failure, but correct cell more sternward can not be affected.Rely on soc and information bits such as eoc and err to control the mode of realization like this, have good error correcting capability.
Preferred embodiment two
The adjustment relevant parameter is following on the basis of preferred embodiment one:
The survey of writing of asynchronous FIFO does not have special cell to fill link, and promptly there is the situation that long-time no cell writes in write port, and FIFO can occur and read sky this moment.
Concrete performing step only needs to do following adjustment in the step 3 (FIFO control module processing logic) of embodiment 1 can accomplish embodiment 2.
A design flag bit (ready) in the FIFO control module, this flag bit be initialized as 0 FIFO with sky (almost_empty) from effectively become invalid in, ready becomes effectively and (is high level), begins to start read operation; When almost_empty is effective, detect after the eoc, ready is dragged down, stop read operation.Guarantee that like this FIFO is read sky.After next cell write, ready drew high, and continued new read operation.
Other performing step is identical with preferred embodiment one.
In preferred embodiment two, FIFO reads the empty sky sign empty that does not rely on FIFO and judges, but utilize sky is indicated that almost_empty and eoc indicate the control of accomplishing read operation, guarantees the complete FIFO of reading of cell.Because eoc is placed on the penult data of cell, has reserved time margin, has guaranteed that like this FIFO can not produce the operation of misreading.
Utilization with empty, will expire and the control of the incompatible realization of the information sets FIFO of soc, eoc; Well evaded in the asynchronous FIFO lattice address in thunder sign indicating number conversion back because the sequential reason causes the state information inaccurate problem of FIFO, for transfer of data reliable and stable provides guarantee.
Need to prove that the design philosophy of the invention described above is not limited to the processing to cell, suitable equally to the processing of bag.
In sum; According to the abovementioned embodiments of the present invention; Employing is according to the abnormal information in cell and the transmission course thereof; It is abandoned, and follow-up all cells through the asynchronous FIFO channel transfer that solved that the cell error of transmission causes are the problem of error of transmission all, and then realizes reliable and stable asynchronous FIFO transmission.
Obviously, it is apparent to those skilled in the art that above-mentioned each module of the present invention or each step can realize with the general calculation device; They can concentrate on the single calculation element; Perhaps be distributed on the network that a plurality of calculation element forms, alternatively, they can be realized with the executable program code of calculation element; Thereby; Can they be stored in the storage device and carry out, and in some cases, can carry out step shown or that describe with the order that is different from here by calculation element; Perhaps they are made into each integrated circuit modules respectively, perhaps a plurality of modules in them or step are made into the single integrated circuit module and realize.Like this, the present invention is not restricted to any specific hardware and software combination.
The above is merely the preferred embodiments of the present invention, is not limited to the present invention, and for a person skilled in the art, the present invention can have various changes and variation.All within spirit of the present invention and principle, any modification of being done, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (11)
1. an information element transmission method is characterized in that, comprising:
Obtain first abnormal information in the cell waiting for transmission;
In the process of said cell being transmitted through asynchronous FIFO FIFO passage, obtain second abnormal information of said cell;
According to said first abnormal information and said second abnormal information, determine whether said cell is abandoned.
2. information element transmission method according to claim 1 is characterized in that, it is effective that said first abnormal information and said second abnormal information are high level, according to said first abnormal information and said second abnormal information, said cell abandoned comprises:
Said first abnormal information and said second abnormal information are carried out or calculated, obtain the 3rd abnormal information;
According to said the 3rd abnormal information, said cell is abandoned.
3. information element transmission method according to claim 2 is characterized in that, according to said the 3rd abnormal information, said cell abandoned comprises:
Generate first check information of said cell;
According to said the 3rd abnormal information said first check information is carried out scrambling;
Judge whether first check information after the said scrambling is correct, if judged result then abandons said cell for not.
4. information element transmission method according to claim 3 is characterized in that, according to said the 3rd abnormal information said first check information is carried out scrambling and comprises: according to said the 3rd abnormal information to the said first check information negate.
5. information element transmission method according to claim 1 is characterized in that, first abnormal information of obtaining said cell waiting for transmission comprises:
Obtain second check information of importing simultaneously with said cell waiting for transmission, judge whether said second check information is correct, if judged result then according to said second check information, obtains said first abnormal information for not;
If judged result judges then for being whether the type of said cell waiting for transmission is correct, if judged result then obtains said first abnormal information for not;
If judged result judges then for being whether the form of said cell waiting for transmission is identical with the form of the said type that is provided with in advance,, then obtain said first abnormal information if judged result is not.
6. information element transmission method according to claim 1 is characterized in that, second abnormal information of obtaining said cell comprises:
Judge whether presence bit mistake of random access device RAM;
If judged result for being, then according to said bit-errors, is obtained said second abnormal information.
7. information element transmission method according to claim 1 is characterized in that, also comprises:
Use said cell, control the unlatching of said asynchronous FIFO passage or close.
8. according to each described information element transmission method in the claim 1 to 7, it is characterized in that after obtaining said first abnormal information of said cell waiting for transmission, said method also comprises:
Said first abnormal information and said cell are transmitted through said asynchronous FIFO passage jointly.
9. information element transmission method according to claim 8 is characterized in that, after obtaining said first abnormal information of said cell waiting for transmission, said method also comprises:
Obtain the head sign and the afterbody sign of said cell;
Said head sign and said afterbody sign are transmitted through said asynchronous FIFO passage with said cell jointly.
10. information element transmission method according to claim 9 is characterized in that, said afterbody sign is placed second that begins from the highest order of said cell, and transmit through said asynchronous FIFO passage jointly with said cell.
11. a cell transmitting device is characterized in that, comprising:
Pretreatment module is used for obtaining first abnormal information of cell waiting for transmission;
Asynchronous FIFO fifo module, be used for through the asynchronous FIFO passage to the process that said cell transmits, obtain second abnormal information of said cell;
Processing module is used for according to said first abnormal information and said second abnormal information said cell being abandoned.
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| CN101039323A (en) * | 2007-04-27 | 2007-09-19 | 华中科技大学 | Multi-rate multi-protocol bit stream processor |
| JP2007310534A (en) * | 2006-05-17 | 2007-11-29 | Fujitsu Ltd | Shared buffer management device and shared buffer management method |
| CN101286873A (en) * | 2008-05-05 | 2008-10-15 | 电子科技大学 | Error frame extracting interface arrangement for Ethernet |
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| CN1547358A (en) * | 2003-12-02 | 2004-11-17 | 烽火通信科技股份有限公司 | A data frame buffer memory device and method for Ethernet passive optical network |
| JP2007310534A (en) * | 2006-05-17 | 2007-11-29 | Fujitsu Ltd | Shared buffer management device and shared buffer management method |
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