CN217135512U - Embedded type Stm32 authentication circuit for verifying communication - Google Patents
Embedded type Stm32 authentication circuit for verifying communication Download PDFInfo
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- CN217135512U CN217135512U CN202220875968.9U CN202220875968U CN217135512U CN 217135512 U CN217135512 U CN 217135512U CN 202220875968 U CN202220875968 U CN 202220875968U CN 217135512 U CN217135512 U CN 217135512U
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- 238000004891 communication Methods 0.000 title claims abstract description 18
- 238000007405 data analysis Methods 0.000 claims abstract description 16
- 238000012795 verification Methods 0.000 claims abstract description 13
- 238000004458 analytical method Methods 0.000 claims description 6
- 230000005540 biological transmission Effects 0.000 description 4
- 238000001514 detection method Methods 0.000 description 3
- 238000012986 modification Methods 0.000 description 2
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Abstract
The utility model relates to an authentication circuit, specifically speaking relates to an embedded Stm32 carries out the authentication circuit that verifies to communication. The device comprises a data control circuit and a checking module, wherein the checking module comprises a data input circuit and a data analysis circuit, the data input circuit receives data sent by equipment and transmits the data to the data analysis circuit; the data analysis circuit analyzes and judges the received data, the embedded Stm32 verifies the communication in the verification circuit, the data can be detected by a plurality of data through connecting a plurality of verification modules in parallel, and the embedded Stm32 can be matched with the indicator lamps X1 and X2, so that the specific position of an error in the data can be quickly generated, and the problem that four parity checkers are connected in parallel and are used for calculation at the same time is solved.
Description
Technical Field
The utility model relates to an authentication circuit, specifically speaking relates to an embedded Stm32 carries out the authentication circuit that verifies to communication.
Background
During data communication transmission, no matter how perfect the design of the transmission system is, errors always exist, and such errors may cause one or more frames transmitted on a link to be corrupted (bit errors occur, 0 becomes 1, or 1 becomes 0), so that the receiver receives wrong data.
In order to improve the correctness of the data received by the receiver, the data needs to be detected by error before the receiver receives the data, and the receiver actually receives the data if and only if the detection result is correct, and currently, the communication data is usually verified by parity check.
Most of the existing parity checks adopt a four-bit data detection mode, namely four data transmitted at a time are detected, however, along with the development of communication technology, the data transmission quantity is more gradual, so that the four-bit detection mode can influence the data transmission efficiency.
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to provide an embedded Stm32 carries out the verification circuit that verifies to communication to solve the problem that proposes among the above-mentioned background art.
In order to achieve the above object, the present invention provides an embedded Stm32 verification circuit for communication, including a data control circuit and a verification module, the verification module includes a data input circuit and a data analysis circuit, wherein:
the data input circuit receives data sent by the equipment and transmits the data to the data analysis circuit;
the data analysis circuit receives the data and then analyzes and judges the data to obtain an analysis result;
and the data control circuit outputs and displays the analysis result obtained by the verification module.
As a further improvement of the technical scheme, the check module is provided with a plurality of, data input circuit data receiving terminal A, B, C and D, the output of data receiving terminal A, B, C and D all is provided with relay KA1, the output of data receiving terminal A and B is connected with exclusive-OR gate U1 behind relay KA1, the output of data receiving terminal C and D is connected with exclusive-OR gate U2 behind relay KA 1.
As a further improvement of the present technical solution, the data analysis circuit includes a nand gate U3, an output of the xor gate U1 is connected to an input of the nand gate U3, and an output of the xor gate U2 is connected to an input of the nand gate U3.
As a further improvement of the technical scheme, the data control circuit comprises an exclusive-or gate U6, U7 and U8, the input end of the exclusive-or gate U6 is connected with the output ends of NAND gates U3 in the first two check modules, the input end of the exclusive-or gate U7 is connected with the output ends of NAND gates U3 in the last two check modules, the output ends of the exclusive-or gates U6 and U7 are connected with the input end of the exclusive-or gate U8, the output end of the exclusive-or gate U6 is connected with a relay KA2 in parallel, the output end of the relay KA1 is connected with an indicator lamp X1, the output end of the exclusive-or gate U7 is connected with a relay KA3 in parallel, the output end of the relay KA3 is connected with an indicator lamp X2, the output end of the exclusive-or gate U8 is connected with a chip U9, and the output end of the chip U9 is connected with a display module.
As a further improvement of the technical scheme, the output end of the relay KA2 is connected with a diode D1 through an indicator lamp X1, and the output end of the relay KA3 is connected with a diode D2 through an indicator lamp X2.
As a further improvement of the technical solution, a resistor R1 is connected to each of the output ends of the plurality of relays KA1, and the output end of the resistor R1 is grounded.
Compared with the prior art, the beneficial effects of the utility model are that:
in the verification circuit for verifying communication by the embedded Stm32, a plurality of verification modules are connected in parallel, so that data can be detected by a plurality of data at the same time, and the specific positions of errors in the plurality of data can be quickly generated by matching with the indicator lamps X1 and X2, so that the problem that the positions of the wrong data are not convenient for people to know by connecting four parity checkers in parallel and calculating at the same time is solved.
Drawings
FIG. 1 is a schematic view of the overall working principle of the present invention;
FIG. 2 is a schematic view of the operation principle of the calibration module of the present invention;
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.
In the description of the present invention, it is to be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and to simplify the description, but do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore should not be construed as limiting the present invention.
Referring to fig. 1-2, the present embodiment provides an embedded Stm32 authentication circuit for verifying communication, including a data control circuit and a verification module, where the verification module includes a data input circuit and a data analysis circuit, where:
the data input circuit receives data sent by the equipment and transmits the data to the data analysis circuit;
the data analysis circuit receives the data and then analyzes and judges the data to obtain an analysis result;
and the data control circuit outputs and displays the analysis result obtained by the verification module.
In addition, the check module is provided with a plurality of, data input circuit data receiving terminal A, B, C and D, the output of data receiving terminal A, B, C and D all is provided with relay KA1, data receiving terminal A and B's output is connected with exclusive-OR gate U1 behind relay KA1, data receiving terminal C and D's output is connected with exclusive-OR gate U2 behind relay KA 1.
Further, the data analysis circuit comprises a nand gate U3, an output end of the xor gate U1 is connected with an input end of the nand gate U3, an output end of the xor gate U2 is connected with an input end of the nand gate U3, when the data analysis circuit is used for generating data, for example, 1000 times, after data receiving ends A, B, C and D receive the data, a current is generated, at this time, the relay KA1 is powered on and pulled, the data current is transmitted to the xor gate U1 and the xor gate U2 through the relay KA1, according to a sequence relation, the xor gate U1 analyzes the first two-bit data current, the xor gate U2 analyzes the second two-bit data current, at this time, the xor gate U1 outputs a high level, the xor gate U2 outputs a low level, and then outputs the high level through the nand gate U3.
Further, the data control circuit comprises exclusive-or gates U6, U7 and U8, the input end of the exclusive-or gate U6 is connected with the output end of the NAND gate U3 in the first two check modules, the input end of the exclusive-or gate U7 is connected with the output end of the NAND gate U3 in the last two check modules, the output ends of the exclusive-or gates U6 and U7 are both connected with the input end of the exclusive-or gate U8, the output end of the exclusive-or gate U6 is connected with a relay KA2 in parallel, the output end of the relay KA1 is connected with an indicator lamp X1, the output end of the exclusive-or gate U7 is connected with a relay KA3 in parallel, the output end of the relay KA3 is connected with an indicator lamp X2, the output end of the exclusive-or gate U8 is connected with a chip U9, the output end of the chip U9 is connected with a display module, the results of the first two NAND gates U3 are output to the exclusive-or gate U6, the results of the last two NAND gates U3 are output to the exclusive-or gate U7, the results are output of the exclusive-or gate U6 and the exclusive-or gate U7 according to the level or gate U6 or gate U7 or level, if the voltage is high level, the relay KA2 and the relay KA2 do not work, a high level signal is directly output to the XOR gate U8, the XOR gate U8 compares and analyzes the output results of the XOR gate U7 and the XOR gate U6 to obtain high level or low level, then the high level or the low level is output to the chip U9, and the chip U9 outputs and displays the high level or the low level through the display module; if the power is low level, the relay KA2 and the relay KA2 are electrified and attracted to conduct the circuit, the indicator lamp X1 and the indicator lamp X2 are electrified and lighted, at the moment, the error party can be judged according to the lighting state,
the chip U9 preferably adopts a single chip microcomputer with the model STM32, the programs of the single chip microcomputer are all modularized, the interfaces are relatively simple, the single chip microcomputer has multiple functions, and the working speed is high; meanwhile, the single chip microcomputer is high in integration level, so that the output efficiency of results is improved.
In addition, the output end of the relay KA2 is connected with a diode D1 through an indicator lamp X1, the output end of the relay KA3 is connected with a diode D2 through an indicator lamp X2, and the diodes D1 and D2 have the function of one-way conduction and can prevent current from reversely flowing to electrify the indicator lamps X1 and X2.
Furthermore, the output ends of the relays KA1 are connected with resistors R1, the output end of the resistor R1 is grounded, and the current is stabilized through the resistor R1, so that the working stability of the circuit is improved.
The foregoing shows and describes the general principles, essential features, and advantages of the invention. It should be understood by those skilled in the art that the present invention is not limited by the above embodiments, and the description in the above embodiments and the description is only preferred examples of the present invention, and is not intended to limit the present invention, and that the present invention can have various changes and modifications without departing from the spirit and scope of the present invention, and these changes and modifications all fall into the scope of the claimed invention. The scope of the invention is defined by the appended claims and equivalents thereof.
Claims (6)
1. An embedded Stm32 authentication circuit for verifying communications, comprising: including data control circuit and check-up module, the check-up module includes data input circuit and data analysis circuit, wherein:
the data input circuit receives data sent by the equipment and transmits the data to the data analysis circuit;
the data analysis circuit receives the data and then analyzes and judges the data to obtain an analysis result;
and the data control circuit outputs and displays the analysis result obtained by the verification module.
2. The embedded Stm32 authentication circuit for verifying communications according to claim 1, wherein: the check-up module is provided with a plurality ofly, data input circuit data receiving terminal A, B, C and D, the output of data receiving terminal A, B, C and D all is provided with relay KA1, the output of data receiving terminal A and B is connected with exclusive-OR gate U1 behind relay KA1, the output of data receiving terminal C and D is connected with exclusive-OR gate U2 behind relay KA 1.
3. The embedded Stm32 authentication circuit for verifying communications according to claim 2, wherein: the data analysis circuit comprises a NAND gate U3, the output end of the XOR gate U1 is connected with the input end of a NAND gate U3, and the output end of the XOR gate U2 is connected with the input end of a NAND gate U3.
4. The embedded Stm32 authentication circuit for verifying communications according to claim 3, wherein: the data control circuit comprises an exclusive-or gate U6, a gate U7 and a gate U8, the input end of the exclusive-or gate U6 is connected with the output end of a NAND gate U3 in the first two check modules, the input end of the exclusive-or gate U7 is connected with the output end of a NAND gate U3 in the second two check modules, the output ends of the exclusive-or gate U6 and the gate U7 are connected with the input end of an exclusive-or gate U8, the output end of the exclusive-or gate U6 is connected with a relay KA2 in parallel, the output end of the relay KA1 is connected with an indicator lamp X1, the output end of the exclusive-or gate U7 is connected with a relay KA3 in parallel, the output end of the relay KA3 is connected with an indicator lamp X2, the output end of the exclusive-or gate U8 is connected with a chip U9, and the output end of the chip U9 is connected with a display module.
5. The embedded Stm32 authentication circuit for verifying communications according to claim 4, wherein: the output end of the relay KA2 is connected with a diode D1 through an indicator lamp X1, and the output end of the relay KA3 is connected with a diode D2 through an indicator lamp X2.
6. The embedded Stm32 authentication circuit for verifying communications according to claim 2, wherein: the output ends of the relays KA1 are connected with resistors R1, and the output end of the resistor R1 is grounded.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202220875968.9U CN217135512U (en) | 2022-04-15 | 2022-04-15 | Embedded type Stm32 authentication circuit for verifying communication |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202220875968.9U CN217135512U (en) | 2022-04-15 | 2022-04-15 | Embedded type Stm32 authentication circuit for verifying communication |
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| Publication Number | Publication Date |
|---|---|
| CN217135512U true CN217135512U (en) | 2022-08-05 |
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|---|---|---|---|
| CN202220875968.9U Expired - Fee Related CN217135512U (en) | 2022-04-15 | 2022-04-15 | Embedded type Stm32 authentication circuit for verifying communication |
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| CN (1) | CN217135512U (en) |
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- 2022-04-15 CN CN202220875968.9U patent/CN217135512U/en not_active Expired - Fee Related
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Address after: 211112 No. 3601 Hongjing Avenue, Jiangning District, Nanjing City, Jiangsu Province Patentee after: NANJING XIAOZHUANG University Address before: 210017 No. 41 North Wei Road, Jiangsu, Nanjing Patentee before: NANJING XIAOZHUANG University |
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