CN103533045A - Method for high-performance fault tolerance of PCIE (Peripheral Component Interface Express) data link layer - Google Patents
Method for high-performance fault tolerance of PCIE (Peripheral Component Interface Express) data link layer Download PDFInfo
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Abstract
The invention relates to a method for high-performance fault tolerance of a PCIE (Peripheral Component Interface Express) data link layer. On the basis of original CRC (Cyclic Redundancy Check) error checking of PCIE, error checking and correcting (ECC) codes are added to realize real-time error correction and self-repair functions; the error can be corrected while the error is checked; the calculation speed is extremely high. An error packet which can be corrected is not required to be retransmitted, so that the error tolerance of the link is increased, meanwhile, the bandwidth and the time can be saved, and the link transmission efficiency is improved.
Description
Technical field
The present invention relates to a kind of for the fault-tolerant method of PCIE data link layer high-performance.
Background technology
PCIE is for interconnecting such as the third generation high-performance I/O bus of calculating and communications platform application ancillary equipment.Data link layer is positioned at the intermediate layer of PCIE master control core, and major function is link management and reliability and the integrality that guarantees the transmission of data.Data link layer is used integrality and consistency fault-tolerant and that retransmission mechanism assurance data transmit.At present the fault-tolerance of PCIE data link layer is very low, can only error detection, and can not error correction.According to the present Research of current PCIE, learn, the error rate of transmitting in data link in order to reduce data, PCIE uses cyclic redundancy check (CRC) to carry out error detection, and CRC is a kind of error control coding very widely of applying in data communication, has stronger error detecing capability.Introduce in detail CRC below in the error detection process of data link layer.
The transmitting terminal of data link layer receives the data TLP from transaction layer, before sending TLP, first TLP is encapsulated, and adds sequence number prefix and CRC suffix, and CRC suffix is according to the content of TLP packet, the check code that uses CRC algorithm to generate.Packaged TLP copy is left in retransmission buffer, this TLP is sent simultaneously.The receiving terminal of data link layer receives TLP from physical layer, now in this TLP, contain sequence number prefix and CRC suffix, receive after TLP, according to the data except crc field in TLP packet, with the same CRC algorithm of transmitting terminal, calculate expectation crc value, the CRC that expectation crc value is carried with TLP compares, if coupling, illustrates that CRC check is correct, proceed other inspection.If do not mate, CRC check mistake, illustrate link error occurs in data transmission procedure, to transmitting terminal, reply NAK data link layer packets (DLLP), transmitting terminal is to the corresponding whole TLP of the NAK DLLP receiving, retransmit operation is carried out in capital, to guarantee that each TLP packet can transmit correctly.
The existing fault-toleranr technique of PCIE data link layer only can check the mistake that data occur in link transmission process, but can not correct it.Meanwhile, due to can not error correction, the packet of all generation link transmission mistakes all will be retransmitted, and has not only increased the burden of link transmission, has also reduced the efficiency of transfer of data, causes bandwidth and waste of time.
Summary of the invention
The object of the invention is to overcome above-mentioned deficiency, provide a kind of for the fault-tolerant method of PCIE data link layer high-performance, can increase the fault-tolerance of link, can save bandwidth and time, improve the efficiency of link transmission simultaneously.
The object of the present invention is achieved like this: a kind of for the fault-tolerant method of PCIE data link layer high-performance, on the original CRC error detection of PCIE basis, add ECC real-time error and self-repair function, detecting in wrong and can correct it, and computational speed is very fast.
Its further technical scheme is: concrete steps are as follows:
1) at data link layer transmitting terminal, add ECC coding circuit, coding circuit is responsible for coding, generates the initial ECC check code of TLP packet;
2) in receiving terminal circuit structure, add ECC decoding circuit, decoding circuit is responsible for generating new ECC check code, and new ECC check code and the entrained initial ECC check code of data are carried out to XOR EDC error detection and correction;
3) when decoding circuit detects wrong but in the time of can not correcting to it (the error correction scope that surpasses encryption algorithm), can generate a wrong id signal that occurs, to show to have not repairable wrong generation, according to ACK/NAK agreement, not repairable wrong bag is retransmitted;
4) at data link layer transmitting terminal, receive after the TLP packet from transaction layer, according to protocol contents, encapsulate, on the existing fault-toleranr technique basis of (adding CRC redundancy cyclic check code), the present invention generates ECC check code by ECC coding circuit, ECC check code is added in to the bag tail of packet after waiting complete TLP to receive;
5) at the receiving terminal of data link layer, receive the TLP data from physical layer, the TLP packet of receiving is carried out to error detection, first carry out CRC check, if CRC check is errorless, illustrate without link transmission mistake, do not need to carry out ECC error correction.If CRC check mistake, carries out ECC error correction.At present conventional ECC coding is Hamming code, can error correction one, and 2 of error detections, if it is not there is multi-bit error to be, repairable, provide error identification signal, so that notice transmitting terminal is retransmitted the TLP makeing mistakes.
Described ECC verification error correction is based on Hamming decoding method, and the data block of every 512 bytes will generate the ECC check code of 3 byte lengths.
Compared with prior art, the invention has the beneficial effects as follows:
The present invention has improved the fault freedom of PCIE data link, can realize error correction, on the fault-toleranr technique basis in existing data link, add ECC real-time error and self-repair function, making originally can only error detection, tolerant system that can not error correction, can realize error correction, thereby strengthens the fault-tolerance of link.
Accompanying drawing explanation
Fig. 1 is data link layer ECC fault-toleranr technique frame diagram of the present invention.
Fig. 2 is the ECC coding circuit of data link layer transmitting terminal of the present invention.
Fig. 3 is ECC parity information generation table of the present invention.
Fig. 4 is the ECC decoding circuit of data link layer receiving terminal of the present invention.
Fig. 5 is ECC checking process figure of the present invention.
Embodiment
The present invention is a kind of for the fault-tolerant method of PCIE data link layer high-performance, said method comprising the steps of:
1) at data link layer transmitting terminal, add ECC coding circuit, coding circuit is responsible for coding, generates the initial ECC check code of TLP packet.In receiving terminal circuit structure, add ECC decoding circuit, decoding circuit is responsible for generating new ECC check code, and new ECC check code and the entrained initial ECC check code of data are carried out to XOR EDC error detection and correction.When decoding circuit detect wrong but in the time of can not correcting to it (the error correction scope that surpasses encryption algorithm), can generate a wrong id signal that occurs, to show to have not repairable wrong generation, according to ACK/NAK agreement, not repairable wrong bag is retransmitted.Scheme overall framework figure is shown in accompanying drawing 1;
2) at transmitting terminal, add ECC coding circuit, generate ECC check code.The Main Function of the ECC coding circuit module of input data is, before data send to physical layer, data are carried out to ECC coding, and the ECC error correcting code of generation is added in TLP packet.TLP data packet length from transaction layer is indefinite, take double word as unit, and minimum length is 4 double words.The TLP receiving from transaction layer is cached to FIFO, by the time after a complete TLP packet receives, not only in TLP, add sequence number and CRC check code according to what stipulate in agreement, also to further encapsulate TLP, bag tail at TLP adds ECC check code, and ECC check code is that ECC coding circuit can be according to fixedly algorithm generation.Packaged TLP copy is deposited in retransmission buffer and to be retransmitted when needing.First judgement before packaged TLP is sent, whether receive the retransmission flag signal from the upper TLP packet of correspondence of opposite end, if do not had, packaged TLP can be sent to lower floor, if needed, retransmit, stop and continue to receive the TLP from transaction layer, and preferentially retransmit.Idiographic flow is shown in as accompanying drawing 2:
In the present invention, ECC coding adopts Hamming EDC error detect correction technology.Take below 512 byte datas are carried out to hamming code as example, generate the Error correction and detection of 3 bytes.
2a) the generation of ECC check code: the ECC checking algorithm that this programme adopts is based on Hamming decoding method, the data block of every 512 bytes will generate the ECC check code of 3 byte lengths.The initial data of 512 bytes forms a matrix that size is 512x8.Initial data be take to byte by row to be produced row check code ，An Lie Yiweiwei unit and calculates generation row check code as unit calculates.Its constituent is the row parity check code of 6 and the row parity check code of 18.The generation of ECC check code is as shown in Figure 3: wherein P1～P4 is row parity check codes, and P8～P2048 is row parity check code.
P1?=?Bit7⊕Bit5⊕Bit3⊕Bit1
P1’?=?Bit6⊕Bit4⊕Bit2⊕Bit0
P2?=?Bit7⊕Bit6⊕Bit3⊕Bit2
P2’?=?Bit5⊕Bit4⊕Bit1⊕Bit0
P4?=?Bit7⊕Bit6⊕Bit5⊕Bit4
P4’?=?Bit3⊕Bit2⊕Bit1⊕Bit0
P8?=?512th?byte⊕510th?byte…4th?byte⊕2nd?byte
P8’?=?511th?byte⊕509th?byte…3rd?byte⊕1st?byte
………………
P2048?=?512th?byte⊕511th?byte…258th?byte⊕257th?byte
P2048’?=?256th?byte⊕255th?byte…2nd?byte⊕1st?byte
Wherein, Bit0～Bit7 is this XOR value that is listed as all data, and 1st byte～512th byte is the XOR value of all data of this row.
2b) the distribution of ECC code: the distribution of ECC check code is as shown in table 1, wherein p1 ~ p4 is row check code, p8 ~ p1024 is row check code.
The allocation table of table 1:ECC check code
Error bit location positioning: Error Offset={ P1024, P512, P256, P128, P64, P32, P16, P8, P4, P2, P1}.Wherein P1024, and P512, P256, P128, P64, P32, P16, P8} is for determining wrong byte location, and { P1} is for determining wrong bit position for P4, P2.
3) when data link layer receiving terminal is from physical layer receives TLP, according to unwrapping, begin and end mark, TLP packet is resolved, parse TLP and wrap entrained initial ECC check code, ECC decoder module, uses with the same ECC encryption algorithm of transmitting terminal simultaneously, generates new ECC check code.Then initial ECC check code is carried out to XOR with newly-generated ECC check code, according to the result of XOR, judge whether wrongly, and whether can correct.If inerrancy or the mistake that can correct, using this TLP packet as correct processing data packets, reply ACK DLLP packet to opposite end; If not repairable mistake can produce error flag signal, to opposite end, reply NACK DLLP packet, inform the transmitting terminal repeating transmission TLP packet corresponding with this NACK DLLP.Detailed process is shown in accompanying drawing 4.
4) ECC check code error-detection error-correction is that initial ECC check code and newly-generated ECC check code are compared, and judges whether data make mistakes in transmitting procedure.The ECC check code of twice generation is carried out to step-by-step XOR, determine thus byte offsets and a position side-play amount for error bit, carry out notifying correction module to carry out negate error correction after the definition of error bit.
5) ECC check code error-detection error-correction flow process is that transmitting terminal data are generated to initial ECC check code by ECC coding circuit, with data, by link, send to data link layer receiving terminal together, the decoding circuit of receiving terminal generates new ECC check code with identical encryption algorithm, then initial ECC check code and newly-generated ECC check code are carried out to XOR, according to the result of XOR, whether be 0, judge whether wrong.If XOR result total data position is 0, explanation does not have mistake; If having general data bit in XOR result is 1, illustrate and only have a data mistake, can correct; If not above two kinds of situations, illustrate that data are wrong and exceeded ECC error correction scope, can produce wrong packet generation sign, notice transmitting terminal is retransmitted this packet.ECC check code error-detection error-correction flow chart as shown in Figure 5.
512 bytes of take describe ECC error-detection error-correction process as example.
ECC verification is to utilize ECC check code step-by-step XOR newly-generated while being stored in the ECC check code in redundant storage space and read block, according to the result of XOR, judges whether data block makes mistakes and carry out error correction.If XOR result is:
A) 24 bit data are that 0 this data block of expression is not made mistakes entirely.
B) there are 12 bit data to be 1 and represent that this data block has 1 bit data to make a mistake, and can utilize XOR result to correct this mistake.
C) only a data is that 1 ECC check code that represents this data block is wrong.
D) remove above three kinds of situations, represent the wrong generation of this data block, and the data bits making a mistake is greater than 1, cannot utilize XOR result to correct this place's mistake.
The present invention is that the fault-toleranr technique in existing data link is (fault-tolerant by CRC cyclic redundancy check (CRC), can only error detection, can not error correction) on basis, add ECC real-time error and self-repair function, to improve the fault-tolerance of data link layer, improve data transmission efficiency simultaneously.
Above-described is only the preferred embodiment of the present invention, the invention is not restricted to above embodiment.Be appreciated that the oher improvements and changes that those skilled in the art directly derive or associate without departing from the spirit and concept in the present invention, within all should thinking and being included in protection scope of the present invention.
Claims (3)
1. for the fault-tolerant method of PCIE data link layer high-performance, it is characterized in that: on the original CRC error detection of PCIE basis, add ECC real-time error and self-repair function, detecting in wrong and can correct it, and improving computational speed.
2. a kind of for the fault-tolerant method of PCIE data link layer high-performance according to claim 1, it is characterized in that concrete steps are as follows:
1) transmitting terminal in data link layer adds ECC coding circuit, and ECC coding circuit is responsible for coding, generates the initial ECC check code of TLP packet;
2) in the receiving terminal circuit structure of above-mentioned data link layer, add ECC decoding circuit, ECC decoding circuit is responsible for generating new ECC check code, and new ECC check code and the entrained initial ECC check code of data are carried out to XOR EDC error detection and correction;
3) when ECC decoding circuit, detect wrong but in the time of can not correcting it, can generate a wrong id signal that occurs, to show to have not repairable wrong generation, according to ACK/NAK agreement, not repairable wrong bag is retransmitted;
4) transmitting terminal in data link layer receives after the TLP packet from transaction layer, according to protocol contents, encapsulate, on the basis of existing fault-toleranr technique, by ECC coding circuit, generate ECC check code, ECC check code is added in to the bag tail of packet after waiting complete TLP to receive;
5) receiving terminal in data link layer receives the TLP packet from physical layer, and the TLP packet of receiving is carried out to error detection, first carries out CRC check, if CRC check is errorless, illustrate without link transmission mistake, do not need to carry out ECC error correction, if CRC check mistake, carries out ECC error correction.
3. a kind of for the fault-tolerant method of PCIE data link layer high-performance according to claim 2, it is characterized in that: described ECC verification error correction is based on Hamming decoding method, the data block of every 512 bytes will generate the ECC check code of 3 byte lengths.
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