CN105634653A

CN105634653A - Method for high-performance fault tolerance of data link layer

Info

Publication number: CN105634653A
Application number: CN201410583655.6A
Authority: CN
Inventors: 李东
Original assignee: QINGDAO JINXUN NETWORK ENGINEERING Co Ltd
Current assignee: QINGDAO JINXUN NETWORK ENGINEERING Co Ltd
Priority date: 2014-10-27
Filing date: 2014-10-27
Publication date: 2016-06-01

Abstract

The invention relates to a method for the high-performance fault tolerance of a PCIE (Peripheral Component Interface Express) data link layer. On the basis of the original CRC (Cyclic Redundancy Check) error checking of the PCIE, error checking and correcting (ECC) codes are added to realize real-time error correction and self-repair functions. Therefore, an error can be corrected while the error is checked. Meanwhile, the calculation speed is extremely high.

Description

The method that data link layer high-performance is fault-tolerant

Technical field

The present invention relates to a kind of method fault-tolerant for PCIE data link layer high-performance.

Background technology

PCIE is for interconnecting the third generation high-performance I/O bus such as calculated with communications platform application peripheral devices. Data link layer is positioned at the intermediate layer of PCIE master control core, and major function is reliability and the integrity of link management and the transmission ensureing data. Data link layer uses fault-tolerant integrity and the concordance ensureing data transmission with retransmission mechanism. The fault-tolerance of current PCIE data link layer is very low, can only error detection, it is impossible to error correction. Present Research according to current PCIE is learnt, in order to reduce the bit error rate that data are transmitted in data link, PCIE uses cyclic redundancy check (CRC) to carry out error detection, and CRC is that one applies error control coding very widely in data communication, has stronger error detecing capability. CRC detection process in data link layer is described in detail below.

The transmitting terminal of data link layer receives the data TLP from transaction layer, before sending TLP, is first packaged by TLP, adds serial number prefix and CRC suffix, and CRC suffix is the content according to TLP packet, uses the check code that CRC algorithm generates. Packaged TLP copy is left in retransmission buffer, this TLP is sent simultaneously. The receiving terminal of data link layer receives TLP from physical layer, now containing serial number prefix and CRC suffix in this TLP, after receiving TLP, according to data except crc field in TLP packet, by the CRC algorithm same with transmitting terminal, calculate expectation crc value, expectation crc value is compared with the TLP CRC carried, if coupling, then illustrate that CRC check is correct, proceeds other inspection. If not mating, CRC check mistake, generation link error in data transmission procedure is described, then reply NAK data link layer packets (DLLP) to transmitting terminal, whole TLP corresponding to the transmitting terminal NAKDLLP to receiving, capital carries out retransmitting operation, to ensure that each TLP packet can transmit correctly.

The existing fault-toleranr technique of PCIE data link layer is only capable of the mistake checking that data occur in link transmission process, but can not it be corrected. Simultaneously as can not error correction, the packet of all generation link transmission mistakes will be retransmitted, and not only increases the burden of link transmission, also reduce data transmission efficiency, cause bandwidth and waste of time.

Summary of the invention

It is an object of the invention to overcome above-mentioned deficiency, it is provided that a kind of method fault-tolerant for PCIE data link layer high-performance, by increasing capacitance it is possible to increase the fault-tolerance of link, bandwidth and time can be saved simultaneously, improve the efficiency of link transmission.

The object of the present invention is achieved like this: a kind of method fault-tolerant for PCIE data link layer high-performance, on PCIE original CRC error detection basis, add ECC real-time error and self-repair function, it can be corrected while detection mistake, and calculate speed quickly.

Detailed description of the invention

Its further technical scheme is: specifically comprise the following steps that

1) at data link layer transmitting terminal plus ECC coding circuit, coding is responsible for by coding circuit, generates the initial ECC check code of TLP packet;

2) adding ECC decoding circuit in receiving terminal circuit structure, decoding circuit is responsible for generating new ECC check code, and with the initial ECC check code entrained by data, new ECC check code is carried out XOR EDC error detection and correction;

3) when decoding circuit detects mistake but it can not correct (the error correction scope exceeding encryption algorithm), a mistake can be generated id signal occurs, to show to have not repairable mistake to produce, then according to ACK/NAK agreement, not repairable wrong bag is retransmitted;

4) receive after the TLP packet of transaction layer at data link layer transmitting terminal, it is packaged according to protocol contents, on the basis of existing fault-toleranr technique (adding CRC redundant cyclic check code), the present invention is generated ECC check code by ECC coding circuit, and ECC check code is added in after waiting complete TLP to receive the bag tail of packet;

5) at the receiving terminal of data link layer, receive the TLP data from physical layer, the TLP packet received is carried out error detection, first carries out CRC check, if CRC check is errorless, then illustrates without link transmission mistake, be then made without ECC error correction. If CRC check mistake, then carry out ECC error correction. At present conventional ECC coding is Hamming code, it is possible to error correction one, error detection 2, if there being the multi-bit error to be, not repairable, then provide error identification signal, in order to the TLP made mistakes is retransmitted by notice transmitting terminal.

Described ECC check error correction is based on Hamming decoding method, and the data block of every 512 bytes will generate the ECC check code of 3 byte lengths.

Compared with prior art, the invention has the beneficial effects as follows:

The present invention improves the fault freedom of PCIE data link, it is capable of error correction, by on the fault-toleranr technique basis of existing data link, add ECC real-time error and self-repair function, making originally can only error detection, can not the tolerant system of error correction, it is possible to realize error correction, thus strengthening the fault-tolerance of link.

Claims

1. one kind is used for the method that PCIE data link layer high-performance is fault-tolerant, it is characterised in that: on PCIE original CRC error detection basis, add ECC real-time error and self-repair function, it can be corrected while detection mistake, and improve calculating speed.

2. a kind of method fault-tolerant for PCIE data link layer high-performance according to claim 1, it is characterised in that specifically comprise the following steps that

1) at the transmitting terminal of data link layer plus ECC coding circuit, coding is responsible for by ECC coding circuit, generates the initial ECC check code of TLP packet;

2) adding ECC decoding circuit in the receiving terminal circuit structure of above-mentioned data link layer, ECC decoding circuit is responsible for generating new ECC check code, and with the initial ECC check code entrained by data, new ECC check code is carried out XOR EDC error detection and correction;

3) when but ECC decoding circuit detects mistake can not it be corrected, a mistake can be generated id signal occurs, to show to have not repairable mistake to produce, then according to ACK/NAK agreement, not repairable wrong bag be retransmitted;

4) receive after the TLP packet of transaction layer at the transmitting terminal of data link layer, it is packaged according to protocol contents, on the basis of existing fault-toleranr technique, ECC coding circuit generate ECC check code, after waiting complete TLP to receive, ECC check code is added in the bag tail of packet;

5) receive the TLP packet from physical layer at the receiving terminal of data link layer, the TLP packet received is carried out error detection, first carries out CRC check, if CRC check is errorless, then illustrates without link transmission mistake, be then made without ECC error correction, if CRC check mistake, then carry out ECC error correction.

3. a kind of method fault-tolerant for PCIE data link layer high-performance according to claim 2, it is characterised in that: described ECC check error correction is based on Hamming decoding method, and the data block of every 512 bytes will generate the ECC check code of 3 byte lengths.