CN1166134C - Stream line-type R/W method for shared memory - Google Patents
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Abstract
The present invention relates to a stream line type R/W method for a shared memory, which comprises the following steps: a cell shared memory composed of N memories according to the N ports of a switching network is arranged; all the data of a cell is divided into N equal parts; a writing-in period and a reading-out period are also divided into N time slots; data buses of the cell shared memory are switched to write N parts of data of the cell at the N ports in the same address block of the corresponding N memories in a mode which is similar to streamline operation, and the N parts of data of the cell is read out and output from an output port. The present invention can shorten the time delay of the switching network, and particularly can obviously reduce the scale and the cost of a system when the number of ports is small.
Description
Technical field
The present invention relates to a kind of ATM switching technology, relate to the implementation method of shared storage read-write control in a kind of atm switching fabric or rather.
Background technology
The characteristics of shared memory architecture are: by the address of diode-capacitor storage, realize indirectly to being temporarily stored in the management of cell in the shared storage, to guarantee that cell is in the clog-free exchange of the inner realization of switching network.Shared memory architecture becomes ATM switching fabric commonly used with the advantage of its low cost and exchange capacity aspect.
Fig. 1 illustrates the implementation method of traditional shared storage, comprises string and conversion and writes control unit 101, shared storage memory manage unit 102, output queue management unit 103, also string conversion and the cell shared storage 105 of reading control unit 104 and being made of N sheet memory.The switching network that has 4 input ports 106 and 4 output ports 107 shown in the figure, 108 is idle address wire, 109 for reclaiming address wire, 110 is the incoming line of cell routing iinformation, 114 is the cell addresses line, and 111 is cell addresses, and the output 1 in output queue management unit 103 frames to output 4 is respectively cell-queue, the corresponding address of record cell in cell shared storage 105 in different cell-queues, 112 and 113 are the wide parallel data bus line of cell.
String and conversion become parallel form with string and modular converter 8 or 16 bit width cell flow data transaction that input port 106 is imported in writing control unit 101, cell (the numeral 1 in the cell in the white box of each input port 106 input, 2,3,4 expression cell routing tags, dash box is partly represented cell load) at fixing time slot, by string and conversion and write and write control module by the idle address write-once shared buffer memory device that reads from shared storage memory manage unit 102 in the control unit 101, simultaneously this address is write in the corresponding cell-queue in the output queue management unit 103 by the routing tag of cell, promptly in each cell-queue, write down the corresponding address of cell in shared storage, the output work queue that realizes cell.And string conversion is then read cell addresses in each output queue in certain sequence with the control module of reading in the control unit 104 of reading from output queue management unit 103, and cell is read from cell shared storage 105 by this address, again by and string conversion with read the cell data stream that parallel serial conversion module in the control unit 104 converts thereof into 8 or 16 bit widths, and from output port 107 outputs.Be recycled in the shared storage memory manage unit 102 through reclaiming address wire 109 for reading the shared address of cell.
In the cell shared storage 105 cell to write and read all be by time slot, carry out in the mode of port poll.Among Fig. 1, corresponding four port ones 06 will be divided into four time slots to the read-write sequence of cell shared storage 105.As writing end at cell shared storage 105, from port one, routing tag is that 2 cell takies time slot 1, from port 2, routing tag is that 4 cell takies time slot 2, from port 3, routing tag is that 1 cell takies time slot 3, is that 3 cell takies time slot 4 etc. from port 4, routing tag.Corresponding 4 output ports in output queue management unit 103 also have 4 set of queues, queue for storing be the address of each cell in the cell shared storage 105.When cell data is exported, also be the corresponding time slot of each port, take time slot 1 as output port 1, be used to export routing tag and be 1 cell data; Output port 2 takies time slot 2, is used to export routing tag and is 2 cell data; Output port 3 takies time slot 3, is used to export routing tag and is 3 cell data; Output port 4 takies time slot 4, is used to export routing tag and is 4 cell data.Through above-mentioned storage repeating process, just can realize the clog-free exchange of cell.
By as can be known to the analysis of Fig. 1, the implementation method of common shared storage read-write control is: elder generation goes here and there to the cell of input and changes, with the input 8 (or 16) bit width (input data width be example with 8 or 16 bits, it is fixed that this is come by existing UTOPIAI and UTOPIAII interface standard, may have many in the practical application or few situation) serial data stream is transformed into parallel data stream, if cell format is that the parallel data stream that 53 bytes then change is 424 bit widths (53 * 8), if cell format is that the parallel data stream that 64 bytes then change is 512 bit widths (64 * 8); With the read-write operation object of this parallel data stream as the cell shared storage, parallel data stream is written in parallel in the cell shared storage again; The cell data of each port appears on the data/address bus of cell shared storage in time-multiplexed mode.
Require the data width of cell shared storage must be consistent in the method with the width of parallel data stream, as cell format is 53 bytes, parallel data stream width after string and the conversion is 424 bits, in order to satisfy this width requirement, even use the wideest memory chip of 36 bits, also will be with 12 (32 * 12=432 be greater than 424).Because the memory chip number relevant with the form of cell (promptly relevant) that uses with the width of parallel data, and with the scale of switching network irrelevant (promptly irrelevant) with port number, therefore no matter be 4 * 4 switching network or 32 * 32 switching network, as long as adopt the cell format of 53 bytes, all must select 12 memory chips concerning the memory chip of 36 bit widths for use, this obviously is uneconomic for small-scale switching network.Simultaneously, string and conversion and the conversion of also going here and there all will be carried out buffer memory to cell data, and this will take a large amount of logical resources, and can the drawing-in system time-delay.
Summary of the invention
The objective of the invention is to design a kind of stream line-type R/W method for shared memory that is used for atm switching fabric, go here and there and the conversion and the logical resource occupancy of changing of also going here and there with minimizing, the system delay that shortening is introduced by string and conversion and the conversion of also going here and there, more after a little while, very help reducing the hardware size of shared storage at the port number of switching network.
The object of the present invention is achieved like this: a kind of stream line-type R/W method for shared memory that is used for atm switching fabric is characterized in that comprising:
A. in the both sides that write and read of cell shared storage input data wire switch unit and output data wire switch unit are set respectively, between input data wire switch unit and output data wire switch unit, shared storage memory manage unit and output queue management unit are set;
B. by the input of switching network, the piece number that the output port number is provided with the cell shared storage, the cutting umber of each cell data and the timeslot number of write cycle and readout interval;
C. by input data wire switch unit, each piece of data of one port input cell is write in each piece cell shared storage in the corresponding address block in proper order by time slot;
D. from the shared storage memory manage unit, read idle address by input data wire switch unit, it is distributed to each input cell, and when each piece of data of input cell writes the shared storage piece, its address is write corresponding OPADD formation in the output queue management unit by the routing tag in the header, carry out the output work queue of cell;
E. output data wire switch unit divides time slot to read cell addresses from each OPADD formation of output queue management unit, and from each shared storage piece, read each part cell data by this address, when read operation is carried out, this cell addresses is recovered in the shared storage memory manage unit.
Also be provided with and write the sequential generation unit and write the sequential delay unit, read the sequential generation unit and read the sequential delay unit; When each piece shared storage is carried out read-write operation, only need produce the reading and writing sequential of first shared storage respectively, and the reading and writing sequential of follow-up each piece shared storage is the reading and writing sequential of the last shared storage time slot of postponing to be obtained by reading the sequential delay unit accordingly and write the sequential delay unit.
Each piece of data of same cell writes in the identical piece in address in each piece shared storage in proper order.
The switching network that N port arranged, the data wire width that connects each piece shared storage of input data wire switch unit and output data wire switch unit is no more than N/one of cell overall width.
Be data wire width, determine every part of cell data or write several times in each piece shared storage according to every shared storage, or behind serial to parallel conversion in each piece shared storage of write-once.
The basic management of described shared storage memory manage unit and output queue management unit is to liking the block address of cell correspondence in each piece shared storage.
Described each cell data is by the mode cutting of five equilibrium.
Stream line-type R/W method for shared memory of the present invention, for N input port of switching network, the cell shared storage can be made of the N block storage, and every block storage is corresponding with an input port, the N block storage is worked simultaneously, can satisfy the requirement of switching network to the data throughput fully.All data of a cell are divided into N equal portions (N depends on input, the output port number of switching network fully), switching by the shared storage data/address bus, the N piece of data of a cell can be write in the identical piece in address in the N block storage (this N piece of data corresponding address in different memory blocks is identical) in the mode of similar pile line operation, be read N part cell data in the piece identical and export from output port with address from the N block storage.Every piece of data is when writing the shared storage piece, can be by the data wire width of importing (as byte wide) with coming with writing in the shared storage piece, also can after string and conversion, once or several times write in the shared storage piece every piece of data, the number of times that writes depends on the data wire width of every shared storage fully, i.e. the data wire width of chip.The management of cell realizes by the mode of management shared storage address or block address, if every part of cell data is the write-once shared storage, then to be mapped in each piece shared storage should be a unique address to the corresponding address of the basic management object-cell of shared storage memory manage unit and output queue management unit, if repeatedly write, it should be a block address that the corresponding address of cell is mapped in each piece shared storage, write how many times, just comprise what physical addresss in the address block.
Adopt method of the present invention, can save string and conversion and and the logical resource that takies of string conversion, and after a fraction of cell data writes in the cell shared storage, just can carry out the read operation of cell, effectively shortened the system delay of switching network; Simultaneously because it is only relevant with the number of input port to constitute the chip-scale of cell shared storage, so at the port number of switching network more after a little while, can effectively reduce the hardware size of shared storage, and port number is few more, it is obvious more that scale reduces; Because the read-write operation to each sheet memory adopts pipeline system, read-write control signal to each sheet memory all is identical, difference is successively just arranged on the time, as long as so realized the read-write of first block storage is controlled, the read-write control signal of all the other each pieces is as long as delayed time the read-write control signal of first block storage by time slot, compare with existing implementation method, do not increase the control complexity.
Therefore, adopt stream line-type R/W method for shared memory, when realizing the less switching network of port number, have the system resource of saving, shorten advantages such as system delay, compare with existing implementation method, under the prerequisite of not increase system control complexity, can effectively reduce the hardware size of shared storage, improve the performance of switching network.
Description of drawings
Fig. 1 is the implementation method schematic diagram of traditional shared storage;
Fig. 2 is the implementation method schematic diagram of pipeline system shared storage;
Fig. 3 is the implementing reading and writing method schematic diagram of pipeline system shared storage.
Embodiment
Further specify technology of the present invention below in conjunction with embodiment and accompanying drawing.
Address before Fig. 1 illustrates, repeat no more.
Referring to Fig. 2, be example still with 4 * 4 switching networks.Because the realization of pipeline system shared storage read-write mode is that a cell is divided into N part, umber is only relevant with the scale of switching network, 4 * 4 switching networks have 4 ports just needs 4 memory chips, the width of every memory can be byte wide, M=8 in the corresponding diagram, cell data just can be with coming with writing in the cell shared storage like this.
The realization of pipeline system shared storage read-write comprises input data wire switch unit 201, shared storage memory manage unit 202, output queue management unit 203, output data wire switch unit 204 and the cell shared storage 205 that is made of 4 memories.4 input ports 206 and 4 output ports 207,208 is idle address wire, 209 for reclaiming address wire, 210 is the incoming line of cell routing iinformation, 215,214 is the cell addresses output line, 211 is cell addresses, output 1 in output queue management unit 203 frames to output 4 is respectively cell-queue, the corresponding address of record cell in cell shared storage 205 in different cell-queues, the wide parallel data bus line (N represents port number, and M represents the data wire width of every block storage) of 212 and 213 expression N*M cells is the wide parallel data bus line of cell.Among the figure, digital frame 1,2,3, the 4 expression cell routing tags in the cell frame, dash box is represented the load of cell 1, and right oblique line frame table shows the load of cell 2, and left oblique line frame table shows the load of cell 3, and white box is represented the load of cell 4.
Corresponding four input ports 206 and four output ports 207, the read-write operation of cell shared storage 205 is divided into four time slots to carry out, each cell of input all is divided into four parts, cell shared storage 205 also is divided into four, and each piece cell shared storage is respectively stored a part of cell data.
Input data wire switch unit 101 reads idle address from shared storage memory manage unit 202, and they are distributed to respectively import cell, when each cell writes cell shared storage 205, the corresponding address of cell is write corresponding cell-queue in the output queue management unit 203, the output work queue that finishes cell by the routing tag in the header.Output data wire switch unit 204 is according to the cell addresses in each cell-queue in the output queue management unit 203 211, read cell data and send output 207 from cell shared storage 205, the cell addresses that will read cell shared storage 205 simultaneously is recovered in the shared storage memory manage unit 202 by reclaiming address wire 209.
The read-write of cell shared storage 205 is similar to the read-write of common cell shared storage, also be each port to be carried out poll by time slot, different is to be undertaken by the memory block piecemeal, be the part (as 1/4) that every block storage only write or read each cell data, the operation that reads or writes of finishing a cell need divide to be carried out for four times.
Be example with read operation than 1 time slot of write operation time-delay in the following table, 4 block storages are shown by reading that time slot is divided, write content, the read operation of memory block is than the write operation time slot of will postponing in the table, like this under situation about allowing, the cell data that writes just can begin to shift out shared storage at next time slot, the time-delay that whole cell is transmitted because of storage can reduce to very little (according to the conventional method, the time that then needs the whole cell cycle, promptly need to import the string and the conversion of cell data) with 4 time slots, the pipeline system operation has been saved for 3/4 storage forwarding time, for the more situation of port number, the meeting of saving of time is more.
| | | | | |||||
| Write | Read | Write | Read | Write | Read | Write | | |
| Time slot | ||||||||
| 1 | Port one | | | | | | | Port one |
| | | Port one | Port one | | | | | |
| | | | | Port one | Port one | | | |
| | | | | | | Port one | Port one | |
By last table and in conjunction with Fig. 2 as can be seen: there is certain rule in the read-write operation of each block storage, if write situation with it is example, corresponding 4 ports, be divided into four time slots the write cycle of a cell, at time slot 1, be that the first of 2 cell 1 (shade) is written into memory block 1 from port one, routing tag; At time slot 2, be that the second portion of 2 cell 1 (shade) is written into memory block 2 from port one, routing tag; At time slot 3, be that the third part of 2 cell 1 (shade) is written into memory block 3 from port one, routing tag; At time slot 4, be that the 4th part of 2 cell 1 (shade) is written into memory block 4 from port one, routing tag ...Promptly at time slot 1 to time slot 4,4 parts of cell datas of input port 1 are write respectively in the memory block 1 to 4; To time slot 1,4 parts of cell datas of input port 2 are write respectively in the memory block 1 to 4 at time slot 2; To time slot 2,4 parts of cell datas of input port 3 are write respectively in the memory block 1 to 4 at time slot 3; To time slot 3,4 parts of cell datas of input port 4 are write respectively in the memory block 1 to 4 at time slot 4.This shows, be to write respectively in the identical address piece of different memory piece for the different piece of same cell, and the one-to-one relationship of address and cell is constant.Simultaneously, concerning memory block 2, what it repeated is the operation (being that address bus, data/address bus and control signal are identical) of memory block 1 previous time slot, and memory block 3 repeats is the operation of memory block 2 previous time slots, and what memory block 4 repeated is the operation of memory block 3 previous time slots.Therefore, can be reduced to operation to memory block 1 to the operation of four block storages, all the other each pieces then are the time-delays of memory block 1 operation.The advantage of doing like this be can accomplish to import cell data with coming with writing, and write again after needn't waiting all data of cell all here, just can save lot of data cache logic resource and string and and the logical resource of parallel serial conversion part branch take.
The readout of cell is the inverse process of ablation process, operates and writes in like manner.
During enforcement, in order to reduce the read or write speed of memory, also can carry out little string and conversion earlier to the cell data of input, gather behind the width of a slice memory again in the write memory, as the M=P among the figure * 8, P is the byte number of write-once.
Referring to Fig. 3, the control of the read-write of 8 * 8 switching networks shown in the figure.8 road cell A, B, C, D, E, F, G, H are imported, exported to 8 input ports 301 and 8 output ports 302 respectively, cell shared storage 303 is corresponding with 8 ports, form by 8 block storages 1 to 8, be divided into 8 time slots cell shared storage 303 is carried out read-write operation.Idle address in the cell shared storage 303 is left among the idle address FIFO 304, and the OPADD of each port then leaves among the OPADD FIFO 311.Write sequential generation module 305 and read sequential generation module 310 and produce writing sequential and reading sequential of memory block 1 respectively, more respectively by writing sequential line 306 and reading sequential line 308 and send memory block 1.Each time delay module 307 and 309 is unit with the time slot to writing sequential, read sequential and delay time, and time delayed signal is sent in all the other memory blocks 2 to 8 successively.The cell data of each port input is divided into 8 parts, writes in the 8 block storage pieces 303 data from same cell that the identical address region memory is put in each memory block 1 to 8 in chronological order respectively.In figure, indicate in each memory block A address block storage be cell data from port A, indicate B the address block storage be cell data from port B, and the like.
One cell is write fashionable, earlier by the sequential of writing of writing sequential generation module 305 generation memory blocks 1, in the first's writing data into memory piece 1 with this cell; Next time slot, the second portion data of this cell are write sequential write memory piece 2 after according to time delay module 307 time-delays, subsequent process can and the like, until in memory block 8, writing the last part cell data.
During cell output, also by same process, 8 the order from memory block 1 to memory block reads cell data and output from each memory block, and it is similar to ablation process to read process.
Among Fig. 3, each cell in every memory a buffer memory a part of data, this part data can take several addresses, and form a little address block, the basic management object of output queue management unit and shared storage memory manage unit is exactly these block address, pipeline system and common shared storage cell way to manage are consistent, and promptly all are to realize indirect control by the address of management cell.
Be appreciated that from the explanation to Fig. 2, Fig. 3 employed memory chip number is only relevant with the port number of switching network the inventive method, when port number was very little, the scale of shared storage can be done very for a short time, and this helps reducing cost; With writing, theoretically, as long as write a byte, the data of this cell just can be read out its cell data, thereby have shortened the time-delay of cell in switching network, help improving the performance of switching network with next; In order to guarantee the consistency of address space, cell is to be buffered in the same address area in each block storage once more, as long as finished the read-write operation to a block storage, the read-write of all the other each pieces control is the just time-delay of first read-write operation just.
Stream line-type R/W method for shared memory of the present invention is not only applicable to the ATM switching network, also is applicable to the switching network of all fixed length packet switchinges.
Claims (7)
1. stream line-type R/W method for shared memory that is used for atm switching fabric is characterized in that comprising:
A. in the both sides that write and read of cell shared storage input data wire switch unit and output data wire switch unit are set respectively, between input data wire switch unit and output data wire switch unit, shared storage memory manage unit and output queue management unit are set;
B. by the input of switching network, the piece number that the output port number is provided with the cell shared storage, the cutting umber of each cell data and the timeslot number of write cycle and readout interval;
C. by input data wire switch unit, each piece of data of one port input cell is write in each piece cell shared storage in the corresponding address block in proper order by time slot;
D. from the shared storage memory manage unit, read idle address by input data wire switch unit, it is distributed to each input cell, and when each piece of data of input cell writes the shared storage piece, its address is write corresponding OPADD formation in the output queue management unit by the routing tag in the header, carry out the output work queue of cell;
E. output data wire switch unit divides time slot to read cell addresses from each OPADD formation of output queue management unit, and from each shared storage piece, read each part cell data by this address, when read operation is carried out, this cell addresses is recovered in the shared storage memory manage unit.
2. the stream line-type R/W method for shared memory that is used for atm switching fabric according to claim 1 is characterized in that: also be provided with and write the sequential generation unit and write the sequential delay unit, read the sequential generation unit and read the sequential delay unit; When each piece shared storage is carried out read-write operation, only need produce the reading and writing sequential of first shared storage respectively, and the reading and writing sequential of follow-up each piece shared storage is the reading and writing sequential of the last shared storage time slot of postponing to be obtained by reading the sequential delay unit accordingly and write the sequential delay unit.
3. the stream line-type R/W method for shared memory that is used for atm switching fabric according to claim 1 and 2 is characterized in that: each piece of data of same cell writes in the identical piece in address in each piece shared storage in proper order.
4. the stream line-type R/W method for shared memory that is used for atm switching fabric according to claim 1 and 2, it is characterized in that: the switching network of N port is arranged, and the data wire width that connects each piece shared storage of input data wire switch unit and output data wire switch unit is no more than N/one of cell overall width.
5. the stream line-type R/W method for shared memory that is used for atm switching fabric according to claim 1 and 2, it is characterized in that: be data wire width according to every shared storage, determine every part of cell data or write several times in each piece shared storage, or behind serial to parallel conversion in each piece shared storage of write-once.
6. the stream line-type R/W method for shared memory that is used for atm switching fabric according to claim 1 and 2 is characterized in that: the basic management of described shared storage memory manage unit and output queue management unit is to liking the block address of cell correspondence in each piece shared storage.
7. the stream line-type R/W method for shared memory that is used for atm switching fabric according to claim 1 is characterized in that: described each cell data is by the mode cutting of five equilibrium.
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| CN100396044C (en) * | 2003-01-28 | 2008-06-18 | 华为技术有限公司 | Dynamic buffer memory management ATM switching arrangement and switching method thereof |
| CN101770504B (en) * | 2009-12-29 | 2012-08-29 | 成都市华为赛门铁克科技有限公司 | Data storage method, data reading method, and data reading equipment |
| JP5663941B2 (en) * | 2010-04-30 | 2015-02-04 | 富士ゼロックス株式会社 | Printed document conversion apparatus and program |
| KR102091394B1 (en) * | 2013-03-04 | 2020-03-20 | 삼성전자 주식회사 | Nonvolatile memory device using variable resistive element and driving method thereof |
| CN103200111B (en) * | 2013-03-29 | 2016-08-24 | 华为技术有限公司 | A kind of cell switching method and device |
| CN109314658A (en) * | 2016-06-27 | 2019-02-05 | 华为技术有限公司 | The method of the network switching equipment and time gas exchange |
| CN108011913B (en) * | 2016-12-29 | 2021-08-20 | 北京车和家信息技术有限责任公司 | Data transmission method, vehicle display device, vehicle multimedia equipment and system |
| KR102016629B1 (en) * | 2018-01-18 | 2019-08-30 | 미쓰비시덴키 가부시키가이샤 | PLC, network unit, CPU unit, and data transfer method |
| US11582025B2 (en) | 2020-09-29 | 2023-02-14 | Amazon Technologies, Inc. | Efficient deduplication using block-based convergent encryption |
| US11329803B2 (en) | 2020-09-29 | 2022-05-10 | Amazon Technologies, Inc. | Redundancy controls in convergent encryption using dynamic salt values |
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