CN1917519A - Method and system for parallel transmitting serial data according to high level data link control - Google Patents
Method and system for parallel transmitting serial data according to high level data link control Download PDFInfo
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- CN1917519A CN1917519A CNA2006101535964A CN200610153596A CN1917519A CN 1917519 A CN1917519 A CN 1917519A CN A2006101535964 A CNA2006101535964 A CN A2006101535964A CN 200610153596 A CN200610153596 A CN 200610153596A CN 1917519 A CN1917519 A CN 1917519A
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Abstract
The invention can effectively reduces the occupation on redundancy bandwidth, avoid the generation of flag bit sequence of segments and lower the load of CPU. In the invention, reading the k bits of next group to the shift register from serial HDLC data stream; if the valid data only have C bits, C<K, then the front K-C bits in flag bit sequence are filled into the remaining space of shift register; sending the data in the shift register, and recording C; when needing to send next HDLC frame, the rear K-C+A bits in flag bit sequence are filled into the shift register, and then reading the valid data of the next HDLC frame from the serial HDLC data stream; wherein, A represents the bit numbers in flag bit sequence.
Description
Technical field
The present invention relates to the communications field, particularly the parallel transmission technology of serial data in the High level data link control.
Background technology
High level data link control (High-Level Data Link Control, be called for short " HDLC ") by (the International Standardization Organization of International Standards Organization, be called for short " ISO ") definition, be the general name of bit-oriented SDL, the modern data link protocol adopts HDLC or its certain subset more.
HDLC is towards the position, and in other words, data position are one by one monitored.The transmission content is made up of binary data, and without any special control routine, but the information in the frame comprises some controls and response command.HDLC supports full duplex transmission, and full duplex is meant that data transmit along both direction simultaneously, thereby can produce higher throughput.
HDLC is applicable to and point-to-pointly is connected with point-to-multipoint (multi-to-multi or one-to-many).X.25 each subclass of HDLC is used to, integrated services digital network (Integrated Services Digital Network, be called for short " ISDN ") and frame-relay network provide signaling and control data.
After a HDLC session is set up, can specify a node, be called host node, be used for management traffic, other nodes are appointed as from node.Host node is used for giving an order, and is used for sending response from node.
At present, three kinds of possible methods of attachment are arranged: i.e. normal response mode (Normal Response Mode, be called for short " NRM "), asynchronous response mode (Asynchronous Response Mode, be called for short " ARM ") and asynchronous balance mode (Asynchronous Balance Mode is called for short " ABM ").
Normal mode is non-equilibrium, because can only could transmit when host node allows its transmission from node.
Asynchronous Balanced Mode is used for carrying out point-to-point connection between two computers on the duplex line.Each station can send order and response on himself circuit, and receives order and response on duplex line.
Mode of operation be meant host node with from internodal relation.The major function of host node is the log-on data link, make from node work, control from respectively from node and to respectively from the data flow of node, overcome and can't when needing, logically remove connection by the system errors that retransmit to solve from node.Submit to host node from node, say that generally it is passive, function is also less, and it does not have ability or has only the fraction ability to solve for system errors.So its equipment is simple than host node, price is cheap than host node.Stipulated three types frame among the HDLC: information frame (I), supervisory frame (S), unnumbered frames (U).All comprise some orders and response in every class frame, they are distinguished by the different coding of the control field in the frame respectively.
The HDLC frame definition be used between each communication system the structure of transmission data and command message.Its frame structure as shown in Figure 1.
Wherein, " 01111110 " is " sign " field (FLAG) of frame, and the beginning and end of its indication HDLC frame is the idle padding data between the HDLC Frame.When HDLC valid data amount is little, can exist a large amount of FLAG to fill between frame and the frame.When avoiding intraframe data identical with FLAG, obscure mutually with FLAG, during any a part of packet continued presence 5 " 1 ", inserting technology by zero-bit and insert one " 0 " position afterwards the 5th " 1 " in frame, is a FLAG sign to guarantee intraframe data not to be thought by mistake.
" address " field in the HDLC frame comprises from the address of node.This field is generally 8, but connect for the multiple spot with a plurality of different addresses, 8 bit address may be not enough, and can use the extended addressing method this moment, also can in this field, insert a broadcast address, so that send a message on multiple spot all nodes in connecting.
" control bit " field is used for indicating the type of frame information, is data, order or response as the information that comprises in this HDLC frame.Wherein, order is sent by host node usually, and response is by sending from node.By this control information, frame and other command responses are hung up in can be confirmed, ask to retransfer the frame that has received frame or request.
Communication session can be by starting at host node and from connecting between the node.Host node is sent to one or more stations with a special frame, sets up process thereby start one.The information that is used for carrying out wrong and data flow con-trol from node during session responds this and sets up process.After everything is ready, transfer of data promptly can begin; During DTD, host node will send a frame, and indication disconnects this session connection.
If hardware interface difference between two terminals that use HDLC agreement communicates then must have a data store and forward unit to carry out adaptive to both sides' interface.
As shown in Figure 2, on terminal B direction, often having this situation: A is synchronous serial interface to the interface of C at terminal A, is that unit carries out transfer of data with 1 bit; C is that unit transmits with many bits then to the interface of B.This relates to the HDLC data serial changes parallel conversion.
The mode of existing techniques in realizing transformation from serial to parallel is very simple, promptly directly serial data is divided into groups by shift register, converts parallel HDLC grouping to.Fig. 3 is converted to the realization schematic diagram that parallel 16 bit HDLC are grouped into example with serial HDLC data.In Fig. 3, from the 1st bit of HDLC serial data stream, per 16 are divided into 1 grouping, and the grouping after dividing is transmitted by parallel mode, realize being serial to parallel conversion.
In actual applications, there is following problem: by existing transformation from serial to parallel transmission means, for any connection, may have the bulk redundancy bandwidth, and have fragment FLAG in the parallel grouping of transmission, strengthen the burden of receiving terminal to multiple spot.
Cause the main cause of this situation to be, in the prior art, insert 0 coding because serial HDLC data have been passed through, the length that has caused actual HDLC frame is not the integral multiple of FLAG.It generally is can be not problematic that this situation connects for point-to-point, but for some connection to multiple spot, then the FLAG fragment may occur, and influence is from the reception of node.Specifically, as shown in Figure 4, host node receives from higher level's central processing unit serial HDLC data of (Central Processing Unit is called for short " CPU "), and synchronously the data distributing that receives is given corresponding to node 1 and 2.Host node is to from node 1 transmission serial data the time, the data that belong in the serial data from node 2 can be replaced with FLAG, because having passed through, serial HDLC data insert 0 coding, therefore need the not necessarily integral multiple of FLAG of the data of replacing, may produce fragment FLAG after the replacement, host node will exist the serial data stream of fragment to be divided into the parallel data transmitted in packets to behind node 1, these fragments FLAG can produce interference to the recipient, need judge and handle fragment FLAG from node 1, increased the weight of burden, and in this process, transmitted a large amount of idle FLAG from node, taken a large amount of bandwidth, for for node 1 and 2, it is required having only half in the HDLC data of being transmitted, and makes effective bandwidth reduce, it is big that redundancy bandwidth becomes, and the utilance of resource is lower.
Summary of the invention
In view of this, main purpose of the present invention is to provide a kind of parallel transmission method and system thereof of High level data link control serial data, makes effectively to reduce taking of redundancy bandwidth, avoids producing fragment flag bit sequence, reduces the load of CPU.
For achieving the above object, the invention provides a kind of parallel transmission method of High level data link control serial data, comprise following steps:
From serial High level data link control HDLC data flow, read the HDLC frame that sends to respectively from node successively, with the HDLC frame that is read place under it from the node corresponding cache;
The serial HDLC frame from the node corresponding cache is respectively divided into groups and parallelly sends described grouping, if the length of a grouping of remaining HDLC frame data less than in the buffer memory behind this HDLC frame circulation fill an integer flag bit sequence, and to the flag bit sequence of being filled with remaining HDLC data parallel transmission of dividing into groups, in buffer memory, have the next one to wait the HDLC frame of sending out.
Wherein, the described current serial HDLC frame that need send is carried out the fixed length packets of K bit, the not enough K bit if last that cut apart divided into groups, then fill flag bit sequence and reach the K bit, and each HDLC grouping after will filling walks abreast and sends to target from node until it in the circulation of this grouping back.
In this external described method, write down the remaining flag bit sequence of last circulation filling in described last grouping, initial from described residue flag bit, circulation is filled an integer flag bit sequence and with the parallel transmission of the flag bit sequence of packets of being filled, is sent next serial HDLC frame until need.
In this external described method, if have remaining flag bit sequence after the integer flag bit sequence of packets that described circulation is filled, then before the next serial HDLC frame that needs send, add this remaining flag bit sequence, parallel data stream packets and transmission that the described serial HDLC frame after the interpolation is carried out.
In this external described method, described flag bit sequence is a binary coding 01111110.
The present invention also provides a kind of parallel transmission system of High level data link control serial data, comprises read module, corresponding to the transmission control module of target from the buffer memory and the described buffer memory of node;
Described read module is used for reading the HDLC frame that sends to respectively from node successively from serial HDLC data flow, and places its target from the node corresponding cache HDLC frame that is read;
Described buffer memory is used to store and sends to the HDLC frame of the corresponding target of this buffer memory from node;
The transmission control module of described buffer memory, be used for the serial HDLC frame of described buffer memory is divided into groups and the described grouping of parallel transmission, if the length of a grouping of remaining HDLC frame data less than in the buffer memory behind this HDLC frame circulation fill an integer flag bit sequence, and to the flag bit sequence of being filled with remaining HDLC data parallel transmission of dividing into groups, in buffer memory, have the next one to wait the HDLC frame of sending out.
Wherein, the transmission control module of described buffer memory is carried out the fixed length packets of K bit to the serial HDLC frame of buffer memory, and the not enough K bit if last HDLC of being cut apart divides into groups is then filled the flag bit sequence in this grouping back circulation and reached the K bit until it.
In this external described system, also comprise logging modle, be used for writing down described transmission control module and fill remaining flag bit sequence in the last circulation of described last grouping;
Described transmission control module is initial with the residue flag bit of described logging modle record, and an integer flag bit sequence is filled in circulation.
In this external described system, when the transmission control module of described buffer memory also is used for existing remaining flag bit sequence after the integer flag bit sequence of packets that described circulation is filled, this remaining flag bit sequence of interpolation before the next serial HDLC frame that needs send.
By relatively finding, the main distinction of technical scheme of the present invention and prior art is, from serial HDLC data flow, read the HDLC frame that sends to respectively from node successively, place its target from the node corresponding cache HDLC frame that is read, send corresponding HDLC frame by each buffer memory from node, because each buffer memory only sends the HDLC frame from node that belongs to its correspondence, no longer must send flag bit sequence or other flag bit sequences that produces owing to rate-matched of filling between two HDLC, reduce the transmission of mass of redundancy data, effectively avoided taking redundant bandwidth.
By serial HDLC frame is carried out the grouping of K bit length, form a plurality of parallel data streams, when having the remaining traffic of not enough K bit, circulation filling flag bit sequence reaches the K bit until it after this data flow, record is last bit number that circulates and filled wherein, and each parallel HDLC data flow that will comprise the data flow of having filled sends to target from node, realize the serial parallel conversion and the transmission of HDLC frame, make host node not simultaneously, also can correctly transmit the HDLC frame in the serial parallel type of the interface that receives and send the HDLC frame.
If have remaining flag bit sequence after the integer flag bit sequence of packets that circulation is filled, then before the next serial HDLC frame that needs send, add this remaining flag bit sequence, again the serial HDLC frame after adding is carried out identical parallel data stream packets and transmission, an energy interval integer flag bit sequence between feasible two HDLC frames that send, avoid producing the fragment of flag bit sequence, reduce the complexity that receiving terminal is handled, reduce the burden of receiving terminal CPU.
Description of drawings
Fig. 1 is a HDLC frame structure schematic diagram in the prior art;
Fig. 2 is the adaptive schematic diagram of terminal interface in the prior art;
Fig. 3 is that the HDLC data serial changes parallel schematic diagram in the prior art;
Fig. 4 is a bit to the connection diagram of multiple spot in the prior art;
Fig. 5 is the parallel transmission method flow chart according to the HDLC serial data of first embodiment of the invention;
Fig. 6 is the schematic diagram according to example in the parallel transmission method of the HDLC serial data of first embodiment of the invention;
Fig. 7 is the parallel transmission system construction drawing according to the HDLC serial data of second embodiment of the invention.
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, the present invention is described in further detail below in conjunction with accompanying drawing.
Core of the present invention is, from serial HDLC data flow, read the HDLC frame that sends to respectively from node successively, place its target from the node corresponding cache HDLC frame that is read, and corresponding HDLC frame from node in each buffer memory divided into groups and the filling of an integer flag bit sequence (FLAG), because each buffer memory only sends the HDLC frame from node that belongs to its correspondence, no longer must send the FLAG or other FLAG that produces owing to rate-matched that fill between two HDLC, reduce the transmission of mass of redundancy data, and avoided the generation of fragment FLAG.
According to inventive principle first embodiment of the invention is described below.First embodiment of the invention relates generally to the parallel transmission method of HDLC serial data, specifically as shown in Figure 5.
In step 501, host node receives the HDLC serial data from higher level CPU, and reads the HDLC frame that sends to respectively from node from serial HDLC data flow successively, and the HDLC frame that is read is placed under it from the node corresponding cache.Because the branch road of each buffer memory correspondence only sends the HDLC frame from node that belongs to its correspondence, and no longer must send the FLAG or other FLAG that produces owing to rate-matched that fill between two HDLC, reduce the transmission of mass of redundancy data, effectively avoided taking redundant bandwidth.
Then enter step 502, after receiving the HDLC Frame, this HDLC frame is carried out the fixed length packets of K bit, form parallel HDLC grouping by K bit shift register from the node corresponding cache.Usually, K can be the integral multiple of 8 bits, is that example describes with 16 bits in the present embodiment, promptly by 16 bit shift registers this HDLC frame is carried out the fixed length packets of 16 bits in this step.
Then enter step 503, after grouping, judge the HDLC frame data that whether also have remaining less than 16 bits in the buffer memory, if exist, then enter step 504, FLAG is filled in circulation behind remaining data, reaches 16 bits until it, form a HDLC grouping, send to correspondingly to node with this grouping and before HDLC grouping are parallel together, wherein, FLAG is 01111110; Otherwise then enter step 505, directly the HDLC grouping with each 16 bit sends to corresponding to node.Such as, HDLC frame in the buffer memory (after inserting 0 coding) is 52 bits, as shown in Figure 6, it is divided into the grouping of 3 16 bits, remaining HDLC frame data are 4 bits, promptly remain back 4 bits 1110 of the FLAG of this HDLC postamble, then FLAG:011111100111 is filled in circulation after this 4 bit, makes its HDLC that forms one 16 bit grouping: 1110011111100111.To divide into groups afterwards to give corresponding from node with 3 HDLC grouping parallel transmissions dividing before.Thereby realize the serial parallel conversion transmission of HDLC frame, make and host node and not simultaneously also can correctly transmit the HDLC frame from the serial parallel type of the interface of the reception HDLC frame of node.In addition for difference for the branch road of node, the total amount of data that data volume waiting for transmission receives much smaller than host node in the corresponding cache, therefore need not to adopt and receive identical speed and send respectively data from node, thereby can suitably reduce respectively transmission bandwidth, thereby reduce expending of bandwidth resources from node.
Then enter step 506, write down remaining FLAG figure place, when promptly being recorded in circulation filling FLAG, the remaining FLAG figure place in back is filled in last circulation; If not to the filling that circulates of HDLC frame data, that is to say the integral multiple that this HDLC frame is 16 bits before, then writing down this residual F LAG figure place is 0.At above-mentioned case, the part FLAG that last circulation is filled is 0111, and visible remaining FLAG figure place is 4, promptly 1110.
Then enter step 507, be buffered in do not receive next HDLC frame before, after above-mentioned HDLC grouping, initial from remaining FLAG, an integer FLAG is filled in circulation, and, write down the remaining FLAG figure place in grouping back again with the respectively parallel transmission in HDLC grouping back of 16 bits of FLAG formation of being filled.At above-mentioned case, before buffer memory is received next HDLC frame, in the end after the grouping that comprises the HDLC frame data, by remaining FLAG 1110 is initial, and an integer FLAG is filled in circulation, promptly 1,110 01,111,110 01111110 ... 01111110, the FLAG that fills is divided into groups by shift register, form each 16 bit fixed length packets: 1110011111100111 ... 1110011111100111, residue 1110.Send the parallel HDLC grouping that these are made up of FLAG, and write down remaining FLAG figure place.By writing down last circulation remaining FLAG when filling, and replenish in the next HDLC grouping, after making parallel HDLC grouping reduce fragment FLAG can not appear, influence is from the reception of node, make from node and can judge and obtain wherein HDLC frame data smoothly, reduce burden from the node processing Frame.
When buffer memory is received next HDLC frame, enter step 508, the high-order compensate for residual FLAG at this HDLC frame returns step 502 afterwards, to the HDLC frame that has added residual F LAG carry out 16 bit lengths grouping and parallel send to corresponding to node.At above-mentioned case, as shown in Figure 6, at next HDLC frame 011111100100 ... before, compensate for residual FLAG 1110, the HDLC frame after obtaining adding: 1110011111100100 ..., afterwards it is carried out 16 bit groupings and parallel the transmission.By the FLAG of compensate for residual before next HDLC frame, make and avoid producing the FLAG fragment by an energy interval integer FLAG between two HDLC frames that send, reduce the complexity that receiving terminal is handled, reduce the burden of receiving terminal CPU.
Second embodiment of the invention relates generally to the parallel transmission system of HDLC serial data, and as shown in Figure 7, this system comprises read module, corresponding to the transmission control module of target from the buffer memory and the buffer memory of node.Read module is used for reading the HDLC frame that sends to respectively from node successively from serial HDLC data flow, and places its target from the node corresponding cache HDLC frame that is read; Because the HDLC frame from node that belongs to its correspondence is only stored and sent to each buffer memory, no longer must send the FLAG or other FLAG that produces owing to rate-matched that fill between two HDLC, reduce the transmission of mass of redundancy data, effectively avoided taking redundant bandwidth.Buffer memory is used to store and sends to the HDLC frame of the corresponding target of this buffer memory from node; The transmission control module of buffer memory, be used for the serial HDLC frame of buffer memory is divided into groups and parallel transmission grouping, if the length of a grouping of remaining HDLC frame data less than in the buffer memory behind this HDLC frame circulation fill an integer FLAG, and to the FLAG that filled with remaining HDLC data parallel transmission of dividing into groups, in buffer memory, have the next one to wait the HDLC frame of sending out.
Wherein, the transmission control module of buffer memory is carried out the fixed length packets of K bit to the serial HDLC frame of buffer memory, and the not enough K bit if last HDLC of being cut apart divides into groups is then filled FLAG in this grouping back circulation and reached the K bit until it.
Also comprise logging modle in this system, be used for record and send control module last circulation of grouping in the end and fill remaining FLAG, this logging modle separately one of correspondence from node or by respectively shared from node.Sending control module is initial with the residue flag bit of logging modle record, and an integer FLAG is filled in circulation, and when after the integer FLAG grouping that circulation is filled, having residual F LAG, this remaining FLAG of interpolation before the next serial HDLC frame of needs transmission.By writing down last circulation remaining FLAG when filling, begin between two HDLC frames, to fill FLAG from residual F LAG for initial, and when there is remaining bits in the FLAG that fills, residual F LAG is replenished in the next HDLC frame, after making parallel HDLC grouping reduce fragment FLAG can not appear, influence is from the reception of node, and guarantee to fill an integer FLAG between two HDLC frames, make from node after receiving data, can judge and obtain the HDLC frame data smoothly, reduce burden from the node processing Frame.
Though pass through with reference to some of the preferred embodiment of the invention, the present invention is illustrated and describes, but those of ordinary skill in the art should be understood that and can do various changes to it in the form and details, and without departing from the spirit and scope of the present invention.
Claims (9)
1. the parallel transmission method of a High level data link control serial data is characterized in that, comprises following steps:
From serial High level data link control HDLC data flow, read the HDLC frame that sends to respectively from node successively, with the HDLC frame that is read place under it from the node corresponding cache;
The serial HDLC frame from the node corresponding cache is respectively divided into groups and parallelly sends described grouping, if the length of a grouping of remaining HDLC frame data less than in the buffer memory behind this HDLC frame circulation fill an integer flag bit sequence, and to the flag bit sequence of being filled with remaining HDLC data parallel transmission of dividing into groups, in buffer memory, have the next one to wait the HDLC frame of sending out.
2. the parallel transmission method of High level data link control serial data according to claim 1, it is characterized in that, the described current serial HDLC frame that need send is carried out the fixed length packets of K bit, the not enough K bit if last that cut apart divided into groups, then fill flag bit sequence and reach the K bit, and each HDLC grouping after will filling walks abreast and sends to target from node until it in the circulation of this grouping back.
3. the parallel transmission method of High level data link control serial data according to claim 2, it is characterized in that, write down the remaining flag bit sequence of last circulation filling in described last grouping, initial from described residue flag bit, circulation is filled an integer flag bit sequence and with the parallel transmission of the flag bit sequence of packets of being filled, is sent next serial HDLC frame until need.
4. the parallel transmission method of High level data link control serial data according to claim 3, it is characterized in that, if have remaining flag bit sequence after the integer flag bit sequence of packets that described circulation is filled, then before the next serial HDLC frame that needs send, add this remaining flag bit sequence, parallel data stream packets and transmission that the described serial HDLC frame after the interpolation is carried out.
5. according to the parallel transmission method of each described High level data link control serial data in the claim 1 to 4, it is characterized in that described flag bit sequence is a binary coding 01111110.
6. the parallel transmission system of a High level data link control serial data is characterized in that, comprises read module, corresponding to the transmission control module of target from the buffer memory and the described buffer memory of node;
Described read module is used for reading the HDLC frame that sends to respectively from node successively from serial HDLC data flow, and places its target from the node corresponding cache HDLC frame that is read;
Described buffer memory is used to store and sends to the HDLC frame of the corresponding target of this buffer memory from node;
The transmission control module of described buffer memory, be used for the serial HDLC frame of described buffer memory is divided into groups and the described grouping of parallel transmission, if the length of a grouping of remaining HDLC frame data less than in the buffer memory behind this HDLC frame circulation fill an integer flag bit sequence, and to the flag bit sequence of being filled with remaining HDLC data parallel transmission of dividing into groups, in buffer memory, have the next one to wait the HDLC frame of sending out.
7. the parallel transmission system of High level data link control serial data according to claim 6, it is characterized in that, the transmission control module of described buffer memory is carried out the fixed length packets of K bit to the serial HDLC frame of buffer memory, the not enough K bit if last HDLC of being cut apart divides into groups is then filled the flag bit sequence in this grouping back circulation and is reached the K bit until it.
8. the parallel transmission system of High level data link control serial data according to claim 7, it is characterized in that, also comprise logging modle, be used for writing down described transmission control module and fill remaining flag bit sequence in the last circulation of described last grouping;
Described transmission control module is initial with the residue flag bit of described logging modle record, and an integer flag bit sequence is filled in circulation.
9. the parallel transmission system of High level data link control serial data according to claim 7, it is characterized in that, when the transmission control module of described buffer memory also is used for existing remaining flag bit sequence after the integer flag bit sequence of packets that described circulation is filled, this remaining flag bit sequence of interpolation before the next serial HDLC frame that needs send.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101184048B (en) * | 2007-12-11 | 2010-12-08 | 华为技术有限公司 | Combination control method and equipment of data frame transmission |
| CN102098333A (en) * | 2010-12-31 | 2011-06-15 | 北京中创信测科技股份有限公司 | High-level data link control (HDLC) data processing method and system |
| CN103999550A (en) * | 2011-10-28 | 2014-08-20 | 皇家飞利浦有限公司 | Communication protocol for lighting system with embedded processors and system operating with the protocol |
| CN107835196A (en) * | 2017-12-13 | 2018-03-23 | 成都长城开发科技有限公司 | A kind of safety communicating method based on HDLC |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0346555B1 (en) * | 1988-06-16 | 1993-08-25 | International Business Machines Corporation | Parallel processing method and device for receiving and transmitting hdlc/sdlc bit streams |
| US6970563B1 (en) * | 2000-06-01 | 2005-11-29 | Mindspeed Technologies, Inc. | System for fast scrambling and descrambling of data |
| CN100401731C (en) * | 2002-06-15 | 2008-07-09 | 华为技术有限公司 | High speed data link control protocol receiving processing module and data processing/method |
| CN100426788C (en) * | 2004-10-11 | 2008-10-15 | 中兴通讯股份有限公司 | Remote transmission method of data in asynchronous serial port |
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2006
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101184048B (en) * | 2007-12-11 | 2010-12-08 | 华为技术有限公司 | Combination control method and equipment of data frame transmission |
| CN102098333A (en) * | 2010-12-31 | 2011-06-15 | 北京中创信测科技股份有限公司 | High-level data link control (HDLC) data processing method and system |
| CN102098333B (en) * | 2010-12-31 | 2013-04-24 | 北京中创信测科技股份有限公司 | High-level data link control (HDLC) data processing method and system |
| CN103999550A (en) * | 2011-10-28 | 2014-08-20 | 皇家飞利浦有限公司 | Communication protocol for lighting system with embedded processors and system operating with the protocol |
| US9826600B2 (en) | 2011-10-28 | 2017-11-21 | Philips Lighting Holding B.V. | Communication protocol for lighting system with embedded processors and system operating with the protocol |
| CN107835196A (en) * | 2017-12-13 | 2018-03-23 | 成都长城开发科技有限公司 | A kind of safety communicating method based on HDLC |
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| CN1917519B (en) | 2010-09-29 |
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