CN106789734B - Control system and method for macro frame in exchange control circuit - Google Patents
Control system and method for macro frame in exchange control circuit Download PDFInfo
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- CN106789734B CN106789734B CN201611194010.9A CN201611194010A CN106789734B CN 106789734 B CN106789734 B CN 106789734B CN 201611194010 A CN201611194010 A CN 201611194010A CN 106789734 B CN106789734 B CN 106789734B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L47/00—Traffic control in data switching networks
- H04L47/50—Queue scheduling
- H04L47/62—Queue scheduling characterised by scheduling criteria
- H04L47/625—Queue scheduling characterised by scheduling criteria for service slots or service orders
- H04L47/6275—Queue scheduling characterised by scheduling criteria for service slots or service orders based on priority
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L47/00—Traffic control in data switching networks
- H04L47/50—Queue scheduling
- H04L47/62—Queue scheduling characterised by scheduling criteria
- H04L47/6215—Individual queue per QOS, rate or priority
Abstract
The invention discloses a control system and method for giant frame in exchange control circuit, the system includes: the description priority scheduling module: according to a scheduling strategy, selecting a queue which is scheduled firstly from a plurality of priority queues, and providing a first descriptor address of the queue to a sending queue management module; a sending queue management module: according to the received or sent data, writing or degree operation is carried out on the descriptor sending queue, and according to the priority information, linked list type management is carried out on each priority queue; the buffer tag queue management module: performing linked list type management on the cache occupied by each data frame through the cache label contained in the descriptor stored in the sending queue; the idle queue management module: and releasing and recovering the storage addresses of the sending queue list item and the cache label list item. The invention improves the efficiency of reading and writing the descriptor and caching the label.
Description
Technical Field
The present invention relates to a network data communication technology applied to data processing in a network device of an ethernet protocol, and more particularly, to a control system and method for a macro frame in a switch control circuit.
Background
With the advent of ethernet technology, the speed of switches has also varied from 10Mbps, 100Mbps to 1Gbps, 10Gbps and even higher. The IEEE approved ethernet standard initially had a maximum frame length of 1518 bytes, which has increasingly become the toggle for data transmission efficiency. Jumbo Frame (Jumbo Frame), which is a standard super-long Frame format of manufacturers, is designed specifically for ethernet over 1Gbps, and has a length varying from 9000 bytes to 64000 bytes. The giant frame can make full use of the data transmission performance of the Ethernet, and the data transmission efficiency is improved by 50-100%.
Descriptor management plays an extremely important role in switch control circuit design, directly affecting the performance of the switch. It manages the mapping relation between frame storage address and destination port and the dequeuing order of high and low priority. The main work of the Ethernet switch is storage forwarding, after a data frame is analyzed by a PHY layer and an MAC layer, an MAC address table is searched to find a forwarding port, a corresponding descriptor is generated and dispatched to each sending port, and various kinds of information of the frame are recorded in the descriptor. The standard two-layer frame structure and the mega-frame structure are shown in fig. 5 and 6, respectively.
In the design of the descriptor, if 256 bytes are assumed as a page, in the switch in which the longest frame only supports 1518 bytes, the requirement can be satisfied by designing a descriptor or an extended type descriptor corresponding to a frame, and for the device supporting the macro frame, the design does not satisfy the requirement, and a single descriptor cannot contain all page addresses of the macro frame data.
Disclosure of Invention
The technical problem to be solved by the invention is to provide a system and a method for controlling a giant frame in a switching control circuit, which is a giant frame control method realized by using a two-stage linked list.
The invention solves the technical problems through the following technical scheme: a control system for switching a superframe in a control circuit, comprising:
the description priority scheduling module: according to a scheduling strategy, selecting a queue which is scheduled firstly from a plurality of priority queues, and providing a first descriptor address of the queue to a sending queue management module;
a sending queue management module: according to the received or sent data, writing or degree operation is carried out on the descriptor sending queue, and according to the priority information, linked list type management is carried out on each priority queue;
the buffer tag queue management module: performing linked list type management on the cache occupied by each data frame through the cache label contained in the descriptor stored in the sending queue;
the idle queue management module: and releasing and recovering the storage addresses of the sending queue list item and the cache label list item.
The present invention also provides a method for controlling a macro frame in a switching control circuit, which is characterized in that the method for controlling the macro frame in the switching control circuit comprises the following steps:
step one, a register file module stores configuration and state information required by system operation;
step two, the gigabit MAC module realizes the gigabit Ethernet data link layer function and completes the conversion between the MAC interface data format and the data bus data format;
step three, through a data bus, the data frame head is learned, analyzed and aged by a data table management module, and the content of the data frame is stored in a data cache;
step four, the data cache module allocates an idle memory for the received data and releases the data memory for the transmitted data;
step five, generating a plurality of sending descriptors of corresponding ports according to a destination port forwarding table provided by an address table management module, wherein the sending descriptors enter corresponding priority queues to be queued according to QOS attributes;
step six, generating a plurality of cache tags according to the data memory address information provided by the data cache module, wherein each tag corresponds to a page address;
step seven, scheduling each priority queue, providing a head address of a transmission frame to the data cache module from the descriptor successfully scheduled by the transmission queue, and then sequentially providing subsequent addresses of the transmission frame to the data cache module according to the cache label linked list;
and step eight, the data cache module transmits the data from the data cache to a data bus according to the data memory address provided by the descriptor management module, and then exchanges the data through the gigabit MAC module.
Preferably, the method for controlling the macro frame in the switching control circuit is applied to the macro frame, and the processing of the data storage address corresponding to the macro frame adopts a two-stage linked list, the first stage is a transmission queue linked list, and the second stage is a cache tag linked list.
Preferably, the transmission queue chain table carries a transmission order of each frame of the transmission port, frame information and a corresponding buffer tag.
Preferably, the sending port can support a plurality of sending queues for QOS, the size of each sending queue can be dynamically adjusted, and each sending queue item is a descriptor and corresponds to one frame of data; the cache tag manages each page of cache, requires multiple cache tag representations for frames over 256 bytes in length, and controls management through a linked list.
Preferably, the buffer tag linked list records the buffer address stored in each frame.
Preferably, the sending queue list item and the cache tag list item are designed to maintain the continuity of the linked list through a next descriptor address and a next cache tag address, and quickly judge the state of the linked list by adding a head identifier and a tail identifier; the descriptors in the sending queue are controlled and managed through a linked list; and writing the frame data, updating the cache tag linked list, and maintaining all page addresses stored in the frame corresponding to each descriptor.
The positive progress effects of the invention are as follows: the sending queue chain table and the cache label are managed together, the reading and writing sending queue descriptor and the cache label both adopt dual-port RAM (random access memory), data of different addresses can be read and written simultaneously, and the efficiency of reading and writing the descriptor and the cache label is improved; the two-stage linked list effectively solves the storage problem of the giant frame, and the realization of the hardware structure is not complex.
Drawings
Fig. 1 is an organizational diagram of a transmit queue chain table and a cache tag chain table.
Fig. 2 is a diagram of a transmit queue entry structure.
FIG. 3 is a diagram of a cache tag table entry structure.
Fig. 4 is a block diagram of a switching control circuit.
FIG. 5 is a block diagram of a descriptor management module architecture.
Fig. 6 is a diagram of a standard two-layer frame structure.
FIG. 7 is a diagram of a macro frame structure.
Detailed Description
The following provides a detailed description of the preferred embodiments of the present invention with reference to the accompanying drawings.
The control system for the macro frame in the switching control circuit of the present invention comprises:
the description priority scheduling module: according to a scheduling strategy, selecting a queue which is scheduled firstly from a plurality of priority queues, and providing a first descriptor address of the queue to a sending queue management module;
a sending queue management module: according to the received or sent data, writing or degree operation is carried out on the descriptor sending queue, and according to the priority information, linked list type management is carried out on each priority queue;
the buffer tag queue management module: performing linked list type management on the cache occupied by each data frame through the cache label contained in the descriptor stored in the sending queue;
the idle queue management module: and releasing and recovering the storage addresses of the sending queue list item and the cache label list item.
The method for controlling the macro frame in the exchange control circuit of the invention comprises the following steps:
step one, a register file module stores configuration and state information required by system operation;
step two, the gigabit MAC module realizes the gigabit Ethernet data link layer function and completes the conversion between the MAC interface data format and the data bus data format;
step three, through a data bus, the data frame head is learned, analyzed and aged by a data table management module, and the content of the data frame is stored in a data cache;
step four, the data cache module allocates an idle memory for the received data and releases the data memory for the transmitted data;
step five, generating a plurality of sending descriptors of corresponding ports according to a destination port forwarding table provided by an address table management module, wherein the sending descriptors enter corresponding priority queues to be queued according to QOS attributes, and the queuing form is as a first-level linked list in the figure 1;
step six, generating a plurality of cache tags according to the data memory address information provided by the data cache module, wherein each tag corresponds to a page address, and the queuing form is as the second-level linked list in fig. 1;
step seven, scheduling each priority queue, providing a head address of a transmission frame to the data cache module from the descriptor successfully scheduled by the transmission queue, and then sequentially providing subsequent addresses of the transmission frame to the data cache module according to the cache label linked list;
and step eight, the data cache module transmits the data from the data cache to a data bus according to the data memory address provided by the descriptor management module, and then exchanges the data through the gigabit MAC module.
As shown in fig. 1 to 4, the present invention is a method for controlling a macro frame in a switch control circuit, and each port has a two-level linked list for maintaining a transmit queue of the port. The processing of the data storage address corresponding to the macro frame adopts a two-level linked list, the first level is a transmission queue linked list, and the second level is a cache label linked list.
The transmission queue chain table carries the transmission order of each frame of the transmission port, the frame information and the corresponding buffer tag. The buffer label linked list records the buffer address stored in each frame.
Each transmit port can support multiple transmit queues (TXQ) for QOS, each transmit queue can be dynamically sized, and each transmit queue entry is a descriptor corresponding to a frame of data. For descriptors in the same transmit queue, management is controlled by a linked list.
Each page Buffer is managed by one Buffer Tag (Buffer Tag), and for frames exceeding 256 bytes in length, a plurality of Buffer tags are required for representation, and management is controlled by a linked list. If a 9728 byte macro frame requires 38 buffer tags, the 38 tags are managed by the next buffer tag address in a linked list manner.
The maintenance of the two-level linked list is realized by a read-write descriptor state machine and a read-write cache label state machine respectively.
And (3) writing in the frame data of each page, updating the cache tag linked list, and maintaining all page addresses stored in the corresponding frames of each descriptor. When the first page content of the long frame is received, a cache tag is written, the page address of the 256 bytes is recorded, meanwhile, the frame head state is set to be 1, the frame tail state is set to be 0, and the next cache tag address points to the head pointer of the idle cache tag linked list; when the next page content is received, writing a cache tag in addition, recording the page address stored by the residual bytes, setting the frame head state to be 0 and the frame tail state to be 1, and updating the next cache tag address field of the previous cache tag of the frame to be the current cache tag address.
When a long frame needs to be sent, the position of the cache tag linked list is found through the cache tag field of the descriptor, the page address of the sent frame is found, if the frame tail identifier is read to be 1, the next cache tag is continuously read according to the next cache tag address until the frame tail identifier is read to be 1, and the frame is read completely.
In the design of the descriptor, if 256 bytes are assumed as a page, in the switch in which the longest frame only supports 1518 bytes, the requirement can be satisfied by designing a descriptor or an extended type descriptor corresponding to a frame, and for the device supporting the macro frame, the design does not satisfy the requirement, and a single descriptor cannot contain all page addresses of the macro frame data.
The descriptor management module is an important function module in the exchange control circuit and is mainly responsible for management of frame storage addresses and scheduling of priority queues, and the two-level linked list is an implementation mode of frame storage address management.
In summary, the sending queue chain table and the cache tag are managed together, the reading and writing sending queue descriptor and the cache tag both adopt dual-port RAMs, data of different addresses can be read and written simultaneously, and the efficiency of reading and writing the descriptor and the cache tag is improved; the two-stage linked list effectively solves the storage problem of the giant frame, and the realization of the hardware structure is not complex.
The above embodiments are described in further detail to solve the technical problems, technical solutions and advantages of the present invention, and it should be understood that the above embodiments are only examples of the present invention and are not intended to limit the present invention, and any modifications, equivalent substitutions, improvements and the like made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (3)
1. A method for controlling a macro-frame in a switch control circuit, the method comprising the steps of:
step one, a register file module stores configuration and state information required by system operation;
step two, the gigabit MAC module realizes the gigabit Ethernet data link layer function and completes the conversion between the MAC interface data format and the data bus data format;
step three, through a data bus, the data frame head is learned, analyzed and aged by a data table management module, and the content of the data frame is stored in a data cache;
step four, the data cache module allocates an idle memory for the received data and releases the data memory for the transmitted data;
step five, generating a plurality of sending descriptors of corresponding ports according to a destination port forwarding table provided by an address table management module, wherein the sending descriptors enter corresponding priority queues to be queued according to QOS attributes;
step six, generating a plurality of cache tags according to the data memory address information provided by the data cache module, wherein each tag corresponds to a page address;
step seven, scheduling each priority queue, providing a head address of a transmission frame to the data cache module from the descriptor successfully scheduled by the transmission queue, and then sequentially providing subsequent addresses of the transmission frame to the data cache module according to the cache label linked list;
step eight, the data cache module transmits data from the data cache to a data bus according to the data memory address provided by the descriptor management module, and then exchanges the data through the gigabit MAC module;
the control method of the giant frame in the exchange control circuit is applied to the giant frame, a two-stage linked list is adopted for processing a data storage address corresponding to the giant frame, the first stage is a sending queue linked list, and the second stage is a cache label linked list;
the sending queue chain table records the sending sequence, frame information and corresponding cache labels of each frame of the sending port;
the sending port can support a plurality of sending queues for realizing QOS, the size of each sending queue can be dynamically adjusted, and each sending queue item is a descriptor and corresponds to one frame of data; the cache tag manages each page of cache, requires multiple cache tag representations for frames over 256 bytes in length, and controls management through a linked list.
2. The method as claimed in claim 1, wherein the buffer tag chain table records the buffer address stored in each frame.
3. The method of claim 1, wherein the sending queue entry and the buffer tag entry are designed to maintain the continuity of the linked list by the next descriptor address and the next buffer tag address, and to quickly determine the status of the linked list by adding the head identifier and the tail identifier; the descriptors in the sending queue are controlled and managed through a linked list; and (4) writing frame data, updating the cache tag linked list, and maintaining all page addresses stored in the frame corresponding to each descriptor.
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| CN110519180B (en) * | 2019-07-17 | 2022-09-13 | 华东计算技术研究所（中国电子科技集团公司第三十二研究所） | Network card virtualization queue scheduling method and system |
| CN111338999B (en) * | 2020-02-20 | 2021-05-28 | 南京芯驰半导体科技有限公司 | DMA system and data transmission method |
| CN114531488B (en) * | 2021-10-29 | 2024-01-26 | 西安微电子技术研究所 | High-efficiency cache management system for Ethernet switch |
| CN115037804B (en) * | 2022-05-09 | 2023-06-27 | 西安电子科技大学 | Ground detection device for realizing giant frame generation and detection based on FPGA |
| CN115002052B (en) * | 2022-07-18 | 2022-10-25 | 井芯微电子技术(天津)有限公司 | Layered cache controller, control method and control equipment |
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