CN115002052B - Layered cache controller, control method and control equipment - Google Patents
Layered cache controller, control method and control equipment Download PDFInfo
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Abstract
The invention provides a hierarchical cache controller, a control method and control equipment, which adopt a hierarchical control mode, firstly manage data nodes through data node descriptors, then correspond data packets and data node chains through label descriptors, and finally take labels as the minimum unit of scheduling. The data processing mode provided by the invention realizes the management of the sending queue at the data packet level, the whole cache data control aspect is clearer, and the data processing cost of the data packet is reduced.
Description
Technical Field
The invention relates to the field of integrated circuit design and integrated circuit data processing, can be applied to the field of FPGA or ASIC design, needs to perform cache management and cache control by taking a data packet as a unit, is particularly suitable for realizing communication related chips, and particularly relates to a layered cache controller, a control method and related control equipment.
Background
In the conventional structure, only one layer of data node management control structure is used, and in the structure needing management and control based on a data packet, such as a structure of a sending single queue, a queue based on priority, a queue based on data flow and the like, all data nodes are put into a queue in the prior art, and the data nodes are seen during scheduling, so that the integrity of the data packet is maintained in the sending process. Although the structure only has one data structure, the function division of the module is unclear, all data nodes are put into the queue, so that the size of the queue becomes huge, the integrity of a data packet is maintained in the scheduling process, and the data scheduling and controlling cost is increased.
The above structure adopted in the prior art directly maintains a small unit structure similar to a data node in a queue maintained by reading out the queue in a common design, and simultaneously manages the data node and the sending sequence in the sending queue, which causes the sending queue to be very long, and the data management control content between packets and in the packets is mixed, so that the boundary is not clear, and the overall management and processing of the data are relatively complex. If there are multiple queues, the scheduling management is difficult in units of data packets because the small data node structure is directly seen in the queues, and errors in data scheduling are easily caused.
Disclosure of Invention
In order to solve the problems in the prior art, the invention provides a hierarchical cache controller, a control method and a control device, which adopt a hierarchical management mode, firstly manage data nodes through data node descriptors, then correspond data packets and data node chains through label descriptors, and finally take labels as the minimum unit of scheduling. The data processing mode is clearer in management, and the data processing cost of the data packet is reduced.
Specifically, the invention discloses the following technical scheme:
in one aspect, the present invention provides a hierarchical cache controller, where the controller includes:
the node use management module is used for managing the available data nodes and tracking the available data nodes;
the label use management module is used for managing available data packet labels and tracking the situation of the data packets which can be stored;
the data node cache module is used for storing the data packets by taking the data nodes as units;
the node descriptor caching module is used for storing the data node descriptor;
the tag descriptor caching module is used for storing tag descriptors;
a write module to implement a write operation of a data packet, and the write module further performs: applying for a data node tag to the node use management module, applying for a data packet tag to the tag use management module, writing packet data to the data node cache module, writing a data node descriptor to the node descriptor cache module, and outputting a tag descriptor to a read module;
a read module for implementing queue control and write operations for data packets, and further performing: receiving a label descriptor sent by a writing module; reading out the packet data from the data node cache module; and reading out the data node descriptor from the node descriptor cache module, releasing the data node label to the node use management module, and releasing the data packet label to the label use management module.
Preferably, the node use management module and the label use management module are implemented by adopting a bitmap, fifo or queue mode.
Preferably, the index of the data node is a number of a minimum storage unit of the cache, and the implementation manner is as follows: dividing the whole cache equally according to the fixed length NodeLength, taking each equal part as a minimum storage unit, and numbering each equal part, wherein the number is used as an index of a data node; the specific positions of the data nodes contained in the data packet in the cache are linked through data node descriptors. Here, the cache is divided in an equal division manner, so that when the number of each share is determined, the specific cache address, i.e., the storage location, can be determined.
Preferably, the starting address of the data node and the address of the cache are in a direct correspondence relationship, and the relationship between the starting address of the data node and the address of the cache is as follows:
DataNode*NodeLength
wherein, the DataNode is the index of the data node;
and storing at least part of data in the data packet in a cache corresponding to the data node.
Preferably, each of the data nodes includes one or more packet data, each packet data corresponds to a cache address, and the bit width of the packet data is consistent with the bit width of the cache.
Preferably, the data node descriptor corresponds to each data node and is used for describing information of each data node, and the information contained in the data node descriptor includes:
and (3) error indication: identifying that an error exists in a data packet corresponding to the data node;
pointer and effective address: when the packet tail indication of the data packet is invalid, identifying the index of the next data node of the data packet; when the packet tail of the data packet indicates validity, indicating the valid address length in the data node;
and (4) tail indication: identifying whether the data node is the last node of the corresponding data packet;
byte-valid indication: when the end of packet indication is valid, it represents the number of bytes valid for the last packet data.
Preferably, the tag descriptor corresponds to a packet, and the tag descriptor includes information including:
next tag pointer: pointing to the next data packet label to be read;
a data node pointer: and pointing to the first data node of the data packet corresponding to the current label.
On the other hand, the invention also provides a hierarchical cache control method, which is applied to the hierarchical cache controller and comprises write-in control and read-out control;
the writing control step is as follows:
step 1, a writing module receives a data packet, applies for a data node label to a node use management module, applies for a data packet label to a label use management module, forms a label descriptor and sends the label descriptor to a reading module; meanwhile, the writing module writes the packet data contained in the data packet into a cache address corresponding to the applied data node label;
step 2, counting the beat number of the data packet in a writing module, applying for a data node label from a node use management module when a fixed length NodeLength is met, forming a new data node descriptor, and storing the data node descriptor to a node descriptor caching module by taking the data node number as an address; meanwhile, writing the packet data corresponding to the new data node into a data node cache module; the fixed length NodeLength is the length for equally dividing the whole cache;
the readout control step is:
step 3, storing the label descriptor to a label descriptor caching module;
step 4, when the sending condition of the reading module is met, reading the label descriptor, reading the packet data from the data node cache module based on the label descriptor, and simultaneously reading the data node descriptor until the packet data is completely read;
and 5, after the packet data is read, releasing the label to a label use management module, and simultaneously releasing the currently processed data node label to a node use management module.
More preferably, in step 4, the packet data is read from the data node cache module based on the tag descriptor, specifically, the packet data is read through the information related to the data node in the tag descriptor.
Preferably, the step 4 further comprises:
when the packet tail in the descriptor of the data node indicates to be effective, only reading the packet data with the number same as the number of the effective addresses; if the packet tail indication is invalid, after the NodeLength cache addresses are read out, the address of the data node cache is switched to a next node pointer in the data node descriptor, meanwhile, a corresponding new data node descriptor is read out from the data node descriptor cache module by taking the next node pointer as the address, and meanwhile, the currently processed data node label is released to the node use management module; this is repeated until the end of packet in the data node descriptor indicates valid.
Preferably, in step 4, the sending condition of the reading module is:
subsequent modules are ready for the corresponding location, or
And clearing the back pressure signal.
In another aspect, the present invention further provides a hierarchical cache control device, which includes a memory and a processor; the processor can call instructions in the memory to cause the control device to perform a hierarchical cache control method as described above.
Compared with the prior art, the technical scheme adopts a hierarchical management mode to divide the cache into the data nodes, so that the utilization rate of the cache is improved, the data nodes are organized into the data packets through the data node descriptors, meanwhile, the label descriptors are used for corresponding to the data packets, and the management of the sending queues is realized at the level of the data packets;
according to the scheme, the data nodes are managed through the data node descriptors, then the data packets correspond to the data node chains through the label descriptors, and finally the labels are used as the minimum unit of scheduling to separate the management of the data packets from the management of the queues.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a schematic diagram of a packet buffer write and read architecture according to an embodiment of the present invention;
fig. 2 is a schematic diagram of a corresponding relationship between a data node and a data cache pair according to an embodiment of the present invention;
FIG. 3 is a diagram illustrating a description information structure of a data node according to an embodiment of the present invention;
fig. 4 is a schematic diagram of a data structure of a tag according to an embodiment of the present invention.
Detailed Description
Embodiments of the present invention are described in detail below with reference to the accompanying drawings. It should be understood that the described embodiments are only some embodiments of the invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It will be appreciated by those of skill in the art that the following specific examples or embodiments are a series of presently preferred arrangements of the invention to further explain the principles of the invention, and that such arrangements may be used in conjunction or association with one another, unless it is expressly stated that some or all of the specific examples or embodiments are not in association or association with other examples or embodiments. Meanwhile, the following specific examples or embodiments are merely provided as the best mode for setting, and are not to be construed as limiting the scope of the present invention.
In a specific embodiment, the technical solution of the present invention provides a structure for writing and reading a cache of a data packet, where the cache is divided into data nodes, so as to improve the utilization rate of the cache, the data nodes are organized into data packets through data node descriptors, and meanwhile, tag descriptors are used to correspond to the data packets, and management of a transmission queue is implemented at the level of the data packets.
As shown in fig. 1, in the packet writing and reading structure, the following functional modules are mainly involved:
1. the node uses a management module, namely, dataNodeManage: and managing available data nodes and tracking the available data nodes in the cache. The node use management module can be implemented by using a bitmap, fifo or queue, for example.
In a more specific embodiment, taking the node use management module as an example and being implemented in a bitmap manner, when tracking available data nodes in a cache, N vld bits are set according to the number N of managed nodes, that is, vld [ 0-N-1 ], and values of N vld in an initial state are all set to 1, which represents that all data nodes are available, and each application for one node sets the vld value with the node as an index to 0, and each release for one node sets the vld value with the node as an index to 1, so that tracking of the available data nodes can be implemented in this way.
2. The tag usage management module, namely tagmanagement: and managing available data packet labels and tracking the data packet condition which can be stored in the cache. The label use management can be realized by adopting bitmaps, fifo or queues.
Here, in a preferred embodiment, the tracking of the condition of the data packet that can be stored in the cache may also be implemented by adopting a way that the node uses the management module to track the data node, that is, in the cache, a corresponding status bit is set to a value of 1 (of course, it may also be set to 0 here) when the data packet is available, and the value of the corresponding status bit is set to 0 when the data packet is not available.
3. Data node cache module, namely datanodibuffer: and storing the cache of the data packet by taking the data node as a unit.
4. Node descriptor caching module, i.e. NodeDesBuffer: is a cache for storing data node descriptors DataNodeDes.
5. Tag descriptor cache module, tagDesBuffer: is a cache for storing the tag descriptors TagDes. The label descriptor consists of a "next label pointer" and a "data node pointer".
When a data packet corresponding to a certain tag is processed, the tag is used as an index to read the cache module, and the next description to be read and the current cache position to be read, namely the data node pointer, can be obtained.
6. Write module, enqueue: for implementing a write operation of a data packet. The module applies for Data node labels to a node use management module DataNodeManage, applies for Data packet labels to a label use management module TagManage, writes packet Data to a Data node cache module DataNodeBuffer, writes Data node descriptors DataNodeDes to a node descriptor cache module NodeDesBuffer, and outputs label descriptors TagDes to a readout module dequeue.
7. Read module, i.e. queue: the method is used for realizing queue management and writing operation of the data packet. The module receives a tag descriptor tagDes sent by a write-in module enqueue and manages the tag descriptor tagDes in a FIFO mode; reading out the Data from the Data node buffer module; and reading the data node descriptor DataNodeDes from the node descriptor cache module NodeDesBuffer, releasing the data node label to the node use management module DataNodeManage, and releasing the data packet label to the label use management module TagManage.
In a more preferred embodiment, the present invention provides the above structure, further introduces specific structures of the data node, the data node descriptor, and the tag descriptor, and usage manners in the working process thereof:
1. data node (the number corresponding to the data node is DataNode): the data node corresponds to the minimum data unit stored, that is, the minimum storage unit of the cache is obtained by equally dividing the whole storage cache in advance, the minimum storage unit of the cache is obtained by equally dividing the whole storage cache according to the fixed length NodeLength, then each equal part is numbered from 0, the number DataNode is the index of the data node, or the value of the number called as the data node, and can be used for representing the corresponding data node. The data node is an abstract number and is also indication information directly corresponding to the cache. The smaller the granularity, the higher the utilization for the cache, but the more complex the management relatively. Each data packet can occupy a plurality of data nodes, and the specific positions of the data nodes in the cache can be scattered and linked through data node descriptors; each data packet can be divided into a plurality of packet data for storage, and each data node can store one or a plurality of packet data. The data node has direct corresponding relation with the stored address, the index of the data node is the number of the minimum cache storage unit, the cache relation between the initial address and the stored address is DataNode NodeLength, the DataNode is the index of the data node, and the value is the number of the minimum cache storage unit corresponding to the data node. Assuming that the NodeLength is 4, the corresponding relationship between the Data node and the Data cache pair is as shown in fig. 2, where each packet Data corresponds to a cache address, and the bit width of the cache address is consistent with the bit width of the cache, and in combination with fig. 2, each Data node may contain multiple packet Data, for example, when the NodeLength is 4, the storage address corresponding to the Data node is 4 cache addresses, that is, 4 packet Data are composed.
2. Data node descriptor DataNodeDes: corresponding to each data node, the related information for describing each data node is shown in fig. 3. The information contained therein includes:
(1) And (3) error indication: and identifying that the data packet has an error, and performing packet alignment and other operations during data scheduling.
(2) Pointer or effective address: when the packet tail indication is invalid, identifying the number of the next Data node of the Data packet, and finding the corresponding packet Data position through the number, as shown in the figure, the Data node 0 points to the Data node 1, and the last packet Data representing the Data node 0 is connected with the first packet Data of the Data node 1; when the end of packet indicates valid, this field indicates the address length valid in the Data node, for example, for the Data node 0 in fig. 3, if the end of packet indicates valid and the value of this field is 2, it represents that the packet Data 0/1/2 is valid and the packet Data3 is invalid.
(3) And (4) tail indication: identifying whether the data node is the last node of the data packet.
(4) Byte valid indicates: when the end of packet indicates valid, this field makes sense, representing the number of bytes for which the last packet Data is valid. Here, a practical example is illustrated: if NodeLength is 4, the width of the packet Data is 128 bits, i.e., 16 bytes. If a packet is 84 bytes long, the end-of-packet indication of the second data node should be valid, because 84-16 x 4= 20-16 x 4 (i.e., less than one data node remains), and then two valid addresses are needed in the second data node to store the remaining 20 bytes, i.e., valid address is 2, the first two addresses of the second node are valid, and the byte valid indication is 4, which represents 4 bytes in the second address, i.e., the valid number of bytes of the last packet data stored in the data node.
3. Tag descriptor TagDes: corresponding to the data packets, queue management and output ordering of the data packets are managed according to TAGs (i.e., TAGs). The Tag (i.e., label) contains information of the first data node in the packet. The data structure of the tag descriptor contains information as shown in fig. 4:
(1) Next tag pointer: pointing to the next packet tag to be read.
(2) A data node pointer: and pointing to the first data node of the data packet corresponding to the current label.
Further, in a specific embodiment, as shown in fig. 1, in the above-mentioned cache management scheme provided by the present invention, the write and read processes of the whole cache are as follows:
in the write control, the specific steps are as follows:
step 1, a data packet enters a write-in module enqueue, and in the first beat, a data node label is applied to a node use management module DataNodeManage, a data packet label is applied to a label use management module TagManage, a label descriptor TagDes is formed and sent to a read-out module dequeue, and the label descriptor TagDes comprises a next label pointer and a data node pointer; meanwhile, for example, using DataNode NodeLength as a cache address to write the Data of the packet Data into the cache address corresponding to the applied Data node label; the data node pointer points to the cache address corresponding to the data node label;
step 2, counting the number of beats of the data packet in the write-in module enqueue, applying for a data node label to a node using management module DataNodeManage after the length of each NodeLength is counted, forming a data node descriptor DataNodeDes at the same time, and storing the formed data node descriptor into a node descriptor cache module NodeDesBuffer by taking the data node number as an address; meanwhile, the new DataNode NodeLength is used as the cache address to continuously write the Data of the package Data into the Data node cache module.
If the end of a Data packet is encountered in the process of storing a certain Data node, immediately forming a Data node descriptor DataNodeDes, storing the descriptor into a node descriptor cache NodeDesbuffer taking the current Data node number as an address, wherein the packet tail indication in the Data node descriptor DataNodeDes is valid, namely the Data node is the last node of the Data packet, the valid address indicates the valid address length in the Data node, the Data node is updated according to the actual situation, and the byte valid indicates that the corresponding field is updated to be the real situation, namely the number of bytes of the valid Data of the last packet;
in the readout control, the specific steps are as follows:
and 3, in the reading module queue, storing the tag descriptor TagDes into a tag descriptor caching module TagDesBuffer, and carrying out sequencing management in a FIFO or linked list mode.
Step 4, when the sending condition of the queue of the reading module is met, the condition can be that a subsequent module is ready to set or a backpressure signal is cleared, the tag descriptor TagDes is read out from an FIFO or a linked list of the tag descriptor caching module, the Data node pointer NodeLength in the tag descriptor tagDes is taken as an address to read out the packet Data from the Data node cache, the Data node pointer is taken as an address to read out the Data node descriptor DataNodeDes from the Data node descriptor caching module, if the packet tail indication in the packet is valid, only the packet Data with the valid address is read out, and the tail beat valid indication of the sent Data packet is formed by the byte valid indication in the packet tail indication; if the packet tail indication is invalid, after reading out NodeLength cache addresses, switching the address of the data node cache into a next node pointer NodeLength in a data node descriptor DataNodeDes, simultaneously reading out the data node descriptor DataNodeDes from the data node descriptor cache module by taking the next node pointer as the address, and simultaneously releasing a currently processed data node label to the node use management module; repeating the steps until the packet tail indication in the data node descriptor DataNodeDes is effective, and stopping after the reading is finished; therefore, during the reading operation, it can be ensured that all the packet data which should be read or can be read are completely read, that is, all the datanodes corresponding to the packet data can be completely read through the combing.
In a more preferred approach, the data node pointer points directly to the index of the data node, and its corresponding value may directly use the value of the index of the pointed data node.
In a preferred embodiment, the condition that the subsequent module is ready to be set is that the subsequent module is a module to be sent after the queue module group package, and in a specific preferred implementation, the subsequent module may be a transport layer of the protocol controller. The ready bit means that the following module has a ready indication that it can receive a new packet for processing.
In the condition of clearing the back-pressure signal sent by the back-stage module, the back-pressure signal is a bp signal (i.e. a back-pressure signal) commonly used in signal processing, and the back-stage module sends the back-pressure signal to represent that the back-stage module is processing other services, and the front-stage module is not allowed to feed packets. These conditions of back pressure include, for example: 1. the processing capacity of the rear stage is smaller than that of the front stage, and the back pressure is realized after the cache is full; 2. when the rear stage is abnormal, the front stage is reversed; 3. back pressure occurs at a later stage of the latter stage, and so on.
In the above-mentioned tail beat valid indication in which the byte valid indication forms a transmitted data packet, the valid indication may not be stored, but may be transmitted in the form of packet associated data, for example, if we organize the data packet in the form of axi stream, the valid indication is stored in the usr signal. Usually, vld is used for indication, for example, the data bit width of the bus is 128 bits, and vld is 16 bits, each bit represents that one byte in the bus is valid.
And step 5, when the packet tail indication in the read data node descriptor DataNodeDes is valid and the packet data of the effective address is read, releasing the Tag to a Tag use management module, and simultaneously releasing the currently processed data node Tag to a node use management module.
The above is a specific embodiment of the method provided in the technical scheme of the present invention.
In addition, in a more preferred embodiment, the present solution may also be implemented by a control device, and the device may include a corresponding module that executes the above hierarchical cache controller or the corresponding control method of the cache controller. Thus, each step or several steps of the above-described embodiments may be performed by a respective module, and the electronic device may comprise one or more of these modules. The modules may be one or more hardware modules specifically configured to perform the respective steps, or implemented by a processor configured to perform the respective steps, or stored within a computer-readable medium for implementation by a processor, or by some combination.
Any process or method descriptions otherwise herein may be understood as representing modules, segments, or portions of code which include one or more executable instructions for implementing specific logical functions or steps of the process, and the scope of the preferred embodiments of the present disclosure includes other implementations in which functions may be executed out of order from that shown or discussed, including substantially concurrently or in reverse order, depending on the functionality involved, as would be understood by those reasonably skilled in the art of implementation of the present disclosure. The processor performs the various methods and processes described above. For example, method embodiments in this scenario may be implemented as a software program tangibly embodied on a machine-readable medium, such as a memory. In some embodiments, some or all of the software programs may be loaded and/or installed via memory and/or a communication interface. When the software program is loaded into memory and executed by a processor, one or more steps of the method described above may be performed. Alternatively, in other embodiments, the processor may be configured to perform one of the methods described above by any other suitable means (e.g., by means of firmware).
The logic and/or steps otherwise described herein may be embodied in any readable storage medium for use by or in connection with an instruction execution system, apparatus, or device, such as a computer-based system, processor-containing system, or other system that can fetch the instructions from the instruction execution system, apparatus, or device and execute the instructions.
The above description is only for the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (7)
1. A hierarchical cache controller, the controller comprising:
the node use management module is used for managing the available data nodes and tracking the available data nodes;
the label use management module is used for managing available data packet labels and tracking the situation of the data packets which can be stored;
the data node cache module is used for storing the data packets by taking the data nodes as units;
the node descriptor caching module is used for storing the data node descriptors;
the tag descriptor caching module is used for storing tag descriptors;
a write module to implement a write operation of a data packet, and the write module further performs: applying for a data node tag to the node use management module, applying for a data packet tag to the tag use management module, writing packet data to the data node cache module, writing a data node descriptor to the node descriptor cache module, and outputting a tag descriptor to a read module;
a read module for implementing queue control and write operations for data packets, and further performing: receiving a label descriptor sent by a writing module; reading out the packet data from the data node cache module; reading out the data node descriptor from the node descriptor cache module, releasing a data node label to the node use management module, and releasing a data packet label to the label use management module;
the data node tag is the number of the minimum storage unit of the cache, and the implementation mode is as follows: dividing the whole cache equally according to the fixed length NodeLength, taking each equal part as a minimum storage unit, and numbering each equal part, wherein the number is used as a data node label; the specific positions of the data nodes contained in the data packet in the cache are linked through data node descriptors;
the initial address of the data node and the address of the cache are in direct correspondence, and the relationship between the initial address of the data node and the address of the cache is as follows:
DataNode*NodeLength
wherein, the DataNode is a data node label;
storing at least part of data in the data packet in a cache corresponding to the data node;
the data node descriptor corresponds to each data node and is used for describing information of each data node; the data node descriptor contains information including:
and (4) wrapping a tail pointer: identifying whether the data node is the last node of the corresponding data packet;
pointer and effective address: when the packet tail indication of the data packet is invalid, marking the next data node label of the data packet; when the packet tail of the data packet indicates validity, indicating the valid address length in the data node;
the tag descriptor corresponds to a data packet, and the tag descriptor includes information including:
next tag pointer: pointing to the next data packet label to be read;
a data node pointer: and pointing to the first data node of the data packet corresponding to the current label.
2. The controller according to claim 1, wherein the node usage management module and the label usage management module are implemented in a bitmap, fifo, or queue manner.
3. The controller of claim 1, wherein each of said data nodes comprises one or more packet data, each packet data corresponding to a buffer address, and wherein said packet data bit width corresponds to a buffer bit width.
4. The controller of claim 1, wherein the data node descriptor contains information further comprising:
and (3) error indication: identifying that the data packet corresponding to the data node has an error;
byte-valid indication: when the end of packet indication is valid, it represents the number of bytes valid for the last packet data.
5. A hierarchical cache control method applied to a hierarchical cache controller according to any one of claims 1 to 4, the method comprising write control and read control;
the writing control step is as follows:
step 1, a writing module receives a data packet, applies for a data node label to a node use management module, applies for a data packet label to a label use management module, forms a label descriptor and sends the label descriptor to a reading module; meanwhile, the writing module writes the packet data contained in the data packet into a cache address corresponding to the applied data node label;
step 2, counting the beat number of the data packet in a writing module, applying for a data node label from a node use management module when a fixed length NodeLength is met, forming a new data node descriptor, and storing the data node descriptor to a node descriptor caching module by taking the data node number as an address; meanwhile, writing the packet data corresponding to the new data node into a data node cache module; the fixed length NodeLength is the length for equally dividing the whole cache;
the readout control step is:
step 3, storing the label descriptor to a label descriptor caching module;
step 4, when the sending condition of the reading module is met, reading the label descriptor, reading the packet data from the data node cache module based on the label descriptor, and simultaneously reading the data node descriptor until the packet data is completely read;
and 5, after the packet data is read, releasing the label to a label use management module, and simultaneously releasing the currently processed data node label to a node use management module.
6. The method of claim 5, wherein the step 4 further comprises:
when the packet tail in the descriptor of the data node indicates to be effective, only reading the packet data with the same number as the effective addresses; if the packet tail indication is invalid, after reading out NodeLength cache addresses, switching the address of the data node cache into a next node pointer in a data node descriptor, simultaneously reading out a corresponding new data node descriptor from the data node descriptor cache module by taking the next node pointer as an address, and simultaneously releasing a currently processed data node label to the node use management module; and repeating the steps until the packet tail in the descriptor of the data node indicates validity.
7. A hierarchical cache control device, characterized in that the device comprises a memory, a processor; the processor is capable of invoking instructions in the memory to cause the control device to perform a hierarchical cache control method according to any of claims 5-6.
Priority Applications (1)
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| CN1547358A (en) * | 2003-12-02 | 2004-11-17 | 烽火通信科技股份有限公司 | A data frame buffer memory device and method for Ethernet passive optical network |
| US8495301B1 (en) * | 2007-11-23 | 2013-07-23 | Pmc-Sierra Us, Inc. | System and method for scatter gather cache processing |
| CN109416674A (en) * | 2016-03-18 | 2019-03-01 | 甲骨文国际公司 | Tuple coding perception direct memory access engine for the multi-core processor that buffer enables |
| CN112860589A (en) * | 2019-11-12 | 2021-05-28 | 广东菲氏科技有限公司 | Data writing method based on flash memory |
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| CN114531488B (en) * | 2021-10-29 | 2024-01-26 | 西安微电子技术研究所 | High-efficiency cache management system for Ethernet switch |
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| CN1547358A (en) * | 2003-12-02 | 2004-11-17 | 烽火通信科技股份有限公司 | A data frame buffer memory device and method for Ethernet passive optical network |
| US8495301B1 (en) * | 2007-11-23 | 2013-07-23 | Pmc-Sierra Us, Inc. | System and method for scatter gather cache processing |
| CN109416674A (en) * | 2016-03-18 | 2019-03-01 | 甲骨文国际公司 | Tuple coding perception direct memory access engine for the multi-core processor that buffer enables |
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