CN1499599A - 对半导体器件进行并行测试的装置和方法 - Google Patents

对半导体器件进行并行测试的装置和方法 Download PDF

Info

Publication number
CN1499599A
CN1499599A CNA2003101017745A CN200310101774A CN1499599A CN 1499599 A CN1499599 A CN 1499599A CN A2003101017745 A CNA2003101017745 A CN A2003101017745A CN 200310101774 A CN200310101774 A CN 200310101774A CN 1499599 A CN1499599 A CN 1499599A
Authority
CN
China
Prior art keywords
memory
logic
test
bist
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CNA2003101017745A
Other languages
English (en)
Other versions
CN1243376C (zh
Inventor
W��R���ƶ���
W·R·科尔宾
B·R·凯斯勒
�ɶ�ѷ
E·A·纳尔逊
²���ķ
T·E·奥布雷姆斯基
ض�
D·L·威特尔
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of CN1499599A publication Critical patent/CN1499599A/zh
Application granted granted Critical
Publication of CN1243376C publication Critical patent/CN1243376C/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/48—Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318572—Input/Output interfaces
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/26—Accessing multiple arrays
    • G11C2029/2602—Concurrent test
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/30—Accessing single arrays
    • G11C2029/3202—Scan chain
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/10—Aspects relating to interfaces of memory device to external buses
    • G11C2207/104—Embedded memory devices, e.g. memories with a processing device on the same die or ASIC memory designs

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Tests Of Electronic Circuits (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)

Abstract

一种通过使用逻辑扫描链测试程序与存储器自检(BIST)并行地执行逻辑和内置存储器测试的技术。它是使用在存储器和逻辑分段之间的电压隔离以及在逻辑和存储器测试时钟之间的隔离的组合来完成的。引进了一种测试算法以在BIST操作期间启动或禁止扫描电路操作。

Description

对半导体器件进行并行测试的装置和方法
技术领域
本发明一般涉及用于测试位于同一芯片上的半导体集成电路装置中的逻辑和嵌入式存储器的装置。
背景技术
近来，具有各种存储器内置式结构的不同类型的半导体集成电路装置(在下文称为LSI)已经投入实际应用。例如，为了进行高速数据处理，在同一基板上提供多个小容量的存储器作为数据处理缓冲器，或者在同一基板上提供诸如微处理器的高速缓冲存储器那样的大容量存储器。
这样，不仅加大了LSI的规模，还增强了测试覆盖(test coverage)的安全性，缩短了不断变长的测试时间等等，这些在执行LSI的功能测试中已经成为显著的问题。
通常，通过向LSI提供用于确认该LSI功能的预定测试向量，并将响应从LSI中读出的测试向量的运算值和期望值进行比较，来执行包括内置LSI中的逻辑电路的内部组合电路的测试操作(即，所谓的逻辑测试)。然而，这对于保护带有少量测试向量的测试操作的测试覆盖来说不是一个非常好的方法，
因此，近来，对倒装或内置在LSI中的类似器件提供具有扫描功能的时序电路，并且有时也会采用利用时序电路的扫描方法来进行测试。例如，Kinoshita等在“Digital Kairo No Kosho Shindan”(Kogaku Tosho K.K.出版的第一卷，第214-215页)中就描述了上述利用扫描方法的测试(在下文称为扫描测试)。而且，通过利用诸如步进算法和校验器算法那样的预定算法进行数据读/写测试，来执行用于LSI中的内置式存储器的存储器测试。
然而，在内置式存储器中的读/写测试是不充分的。例如，即使当内置式存储器具有基于RAM的存储单元结构时，也可能因一具体的存储单元的漏泄电流而产生诸如数据消失那样的问题。因此，在预定时间段内，需要实施用来确保数据保持的测试。具体地说，在所述数据保持测试中，提前把预定数据写入存储器，在预定时间段内没有数据写入或从存储器读出，且在一预定时间段过后，检查写入的数据是否还在。在没有执行存储器存取期间，所述数据保持测试需要几十毫秒至几百毫秒的保持时间。这一时间远远大于LSI几个至几十纳秒的的通常操作时间长。
因为越来越多的LSI设计结合了嵌入式存储器，因此需要研发有效的和能够缩短所需测试时间的测试技术。
发明内容
因此，本发明的一个目的是提供具有存储器和逻辑部件的LSI设计的并行测试。
另一个目的是在不影响测试质量的情况下优化测试时间。
进一步的目的是在不限制芯片的尺寸的情况下优化测试时间。
再有一个目的是加速在每一个设计中的测试时间。
现有的对具有逻辑和嵌入式存储器的芯片的测试解决方法不能优化测试时间。一个典型的解决方法包括串行地测试逻辑和存储器，这导致浪费测试时间。例如，在DRAM保持测试的芯片暂停的这部分期间，不进行逻辑测试。如果存在使逻辑和嵌入式存储器能够并行测试的解决方法，将使测试时间得到优化。
本发明对逻辑和嵌入式存储器进行并行测试。本发明最基本的概念是提供一种与内置存储器自检(BIST)并行执行的逻辑扫描测试能力。这些通过下面来完成：
(1)在逻辑和存储器分段之间的电压隔离；
(2)隔离的逻辑和存储器测试时钟；
(3)扫描旁路/隔离；
(4)测试算法；
电压隔离使独立电压电平在测试期间能够被提供到逻辑和存储器分段。存储器和逻辑测试在各自的测试期间需要不同的电压电平。电压隔离可以用几种方式来完成：(a)单独的Vdd平面(例如，芯片外)，(b)电压调节器，由外部基准电压产生各个宏(macro)电压电平，(c)一个在BIST引擎中的控制功能部件，为各个宏，控制宏的电压调节器的基准，或(d)从芯片逻辑部分反馈到所述调节器以控制电压电平。应当理解，在本领域中存在的其它好的已知技术也可以用在所述系统中来提供电压隔离，因此本发明将不限于上述所例举的例子。
附图说明
图1是本发明的方框图。
图2是本发明的另一个方面的方框图。
图3是本发明的流程图。
具体实施方式
参见图1，其中示出能够在包括逻辑和嵌入式存储器的芯片上进行并行测试的装置。一个所述装置的必要元件提供所述逻辑和存储器测试顺序的独立计时。所述独立计时能力允许加载逻辑测试模式并导致所述存储器测试时钟需求的独立卸载。所述计时信号由外部测试器10提供给时钟倍增器和控制电路11。在测试过程20中，所述时钟倍增器电路11提供测试时钟信号12、13、14以将独立时钟信号提供给逻辑部分21和在所述芯片的存储器宏部分23上的BIST。
在一可选方案中来自所述测试器10的时钟信号可以应用在时钟发生器25上，此时钟发生器25可以直接产生时钟信号12、13、14或向所述时钟倍增器控制电路11提供一个信号，它可以依次产生所述时钟信号12、13、14。在测试中，使用两个方案中的任一个将对应用于所述芯片的时钟信号提供充分的隔离。
作为另外的可选的测试器10可以独立地提供全部的时钟信号给所述芯片，这个方案虽然最简单，但却具有使用许多I/O只用于测试目的之缺点。
内置自检系统(电路没有示出)，产生对于存储器宏部分23的测试信号。电路30在BIST测试期间禁止把测试时钟给予存储器宏以便“时钟倍增与控制”电路11可以基于从测试器(或可选的从OPCG ckt(25))输入的基准频率产生BIST测试时钟。控制电路11还产生控制信号给倍增器35，所述倍增器35在BIST操作期间选择由“时钟倍增与控制”部件产生的测试时钟。这使得独立的测试时钟能够应用于存储器和逻辑分段。在扫描操作期间，所述时钟使全局测试时钟有效，从而可以如下述那样的适当卸载(扫描出)BIST内容。
根据本发明，部分时间(当测试存储器BIST引擎时)里对逻辑和存储器两者同时计时，然后为了加快测试，一旦BIST校验完成，就分离对于BIST引擎的计时(如存储器测试遵循与逻辑测试不同的计时顺序)并且当逻辑测试也发生时，存储器的测试就可以进行。
扫描旁路/隔离
扫描旁路使存储器宏能够和扫描链隔离。当为了在BIST引擎正在运行时，通过扫描链装载逻辑测试模式及卸载测试结果，这样的隔离在并行测试期间是必要的。图2阐明了扫描旁路/隔离的一个优选实施例。初级输入40或通用测试寄存器锁存器40可以用来为在每个存储器分段中的多路复用器30提供控制信号(标注为“旁路”)。扫描链用来装载BIST模式。一旦从输入42装载了BIST操作模式，来自测试锁存器40的控制信号通过选择信号中的扫描而不是通过BIST引擎的输出44设置多路复用器30为旁路模式。然后，当BIST引擎运行时，经由扫描链装载逻辑模式以及卸载结果。当完成BIST时，旁路多路复用器退出旁路模式并且使用上述的计时方案经由扫描链卸载结果。
图3举例说明了测试算法的一个高级流程。一旦验证了扫描链50和BIST逻辑完整性，就经由扫描链52装载BIST模式。当装载BIST模式和计时由全局测试时钟(不是局部BIST时钟)控制时，芯片不处于旁路模式。一旦装载了BIST模式，就经由图2所示的“旁路信号”设置芯片为旁路模式53(存储器宏与扫描链隔离)。在旁路模式下，单独的BIST测试时钟由在部分2中所描述的处理产生。逻辑测试模式的装载以及结果的卸载经由扫描链与BIST引擎运行54并行。这是通过隔离的计时以及与存储器宏隔离的扫描来完成的。电压隔离也可以用在逻辑/BIST并行测试期间。当BIST和逻辑测试结束时55，芯片退出旁路模式56以及全局测试时钟再次控制存储器宏，BIST结果经由扫描链57卸载。这样的处理重复地用于所有的逻辑/BIST顺序。
很明显的，在不脱离本发明的精神和范围下，本领域熟练的技术人员可以在用于本发明的存储器设备的并行测试电路中进行各种修改和变化。因此，本发明意图覆盖出现在本发明所提供的附加的权利要求和它们的等价物范围中的修改和变化。

Claims (14)

1、一种用于与BIST电路并行地对具有逻辑和存储器宏的半导体器件执行逻辑和存储器测试的装置，包括：
电压隔离元件，用于逻辑和存储器电路；
计时系统，包括用于逻辑和存储器电路的计时隔离元件；
扫描链旁路隔离元件；
启动或禁止所述BIST，以在读出逻辑扫描链结果时，执行所述存储器宏电路的测试
2、根据权利要求1所述的装置，其中所述旁路隔离元件由控制信号启动。
3、根据权利要求2所述的装置，其中所述控制信号由来自控制电路的初级输入提供。
4、根据权利要求2所述的装置，其中所述控制信号由锁存器提供。
5、根据权利要求2所述的装置，其中所述控制信号应用于锁存器。
6、根据权利要求5所述的装置，其中所述锁存器提供所述控制信号给在各个存储器宏中的多路复用器。
7、根据权利要求6所述的装置，其中所述控制信号通过选择在装载逻辑测试模式到所述BIST电路中的信号中的一个扫描将所述装置设置为旁路模式。
8、根据权利要求7所述的装置，其中在完成所述BIST后，所述装置退出旁路模式以及卸载结果。
9、根据权利要求6所述的装置，其中计时系统包括存储器测试时钟，其允许与存储器时钟无关地装载以及卸载逻辑测试模式。
10、根据权利要求9的装置，其中由外部测试器将时钟系统的信号应用到时钟倍增器与控制电路上。
11、根据权利要求9的装置，其中由外部测试器将时钟系统的信号应用到位于半导体器件上的时钟发生器上。
12、一种用于与BIST并行地对具有逻辑和存储器电路的半导体器件执行逻辑和存储器测试的方法，包括：
使用隔离元件分离逻辑和存储器电路；
为逻辑和存储器电路计时；
启动或禁止BIST扫描链旁路隔离元件；以及
当读出逻辑扫描链结果时，测试存储器电路。
13、根据权利要求12所述的方法，包括由控制旁路信号测试旁路隔离元件。
14、一种用于与BIST并行地对具有逻辑和存储器电路的半导体器件执行逻辑和存储器宏测试的方法，包括：
验证扫描链和BIST操作；
利用全局计时装载BIST模式；
将设备设置为旁路模式，其中将存储器宏电路与扫描链隔离；
产生单独的测试时钟信号给存储器宏电路和逻辑电路两者；以及
与BIST并行地运行扫描链。
CNB2003101017745A 2002-10-25 2003-10-23 对半导体器件进行并行测试的装置和方法 Expired - Fee Related CN1243376C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/065,503 2002-10-25
US10/065,503 US7103814B2 (en) 2002-10-25 2002-10-25 Testing logic and embedded memory in parallel

Publications (2)

Publication Number Publication Date
CN1499599A true CN1499599A (zh) 2004-05-26
CN1243376C CN1243376C (zh) 2006-02-22

Family

ID=32106056

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB2003101017745A Expired - Fee Related CN1243376C (zh) 2002-10-25 2003-10-23 对半导体器件进行并行测试的装置和方法

Country Status (4)

Country Link
US (1) US7103814B2 (zh)
KR (1) KR100522520B1 (zh)
CN (1) CN1243376C (zh)
TW (1) TWI245913B (zh)

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101515479A (zh) * 2009-03-30 2009-08-26 北京中星微电子有限公司 一种提高扫描链测试覆盖率的方法和装置
CN101371153B (zh) * 2006-01-06 2011-09-28 Nxp股份有限公司 Ic测试方法和装置
CN101292171B (zh) * 2005-10-24 2012-04-18 Nxp股份有限公司 Ic测试方法和设备
CN103576076A (zh) * 2012-07-27 2014-02-12 飞思卡尔半导体公司 用于执行扫描测试的系统和方法
CN103890597A (zh) * 2011-10-25 2014-06-25 泰拉丁公司 用于控制测试块并行性的支持简化配置的测试系统
CN105891695A (zh) * 2014-05-07 2016-08-24 北京同方微电子有限公司 一种基于单io的ic卡并行测试方法
CN106291313A (zh) * 2015-06-10 2017-01-04 飞思卡尔半导体公司 用于测试集成电路的方法和设备
CN106653098A (zh) * 2017-01-04 2017-05-10 盛科网络（苏州）有限公司 针对逻辑和cpu均可读写存储器的测试方法
CN107731264A (zh) * 2016-08-10 2018-02-23 英飞凌科技股份有限公司 非易失性存储器测试
CN109060522A (zh) * 2018-06-28 2018-12-21 苏州勃朗特半导体存储技术有限公司 针对m.2固态硬盘压拉测试的电压控制系统

Families Citing this family (72)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6556044B2 (en) 2001-09-18 2003-04-29 Altera Corporation Programmable logic device including multipliers and configurations thereof to reduce resource utilization
JP4105077B2 (ja) * 2003-10-30 2008-06-18 株式会社東芝 半導体集積回路
DE602005008552D1 (de) 2004-01-19 2008-09-11 Nxp Bv Testarchitektur und -verfahren
US7308626B2 (en) * 2004-02-19 2007-12-11 International Business Machines Corporation Method and structure for picosecond-imaging-circuit-analysis based built-in-self-test diagnostic
DE102004009693A1 (de) * 2004-02-27 2005-10-13 Advanced Micro Devices, Inc., Sunnyvale Technik zum Kombinieren eines Abtasttests und eines eingebauten Speicherselbsttests
US7555690B1 (en) * 2004-12-23 2009-06-30 Xilinx, Inc. Device for and method of coupling test signals to a device under test
KR100688517B1 (ko) * 2005-01-11 2007-03-02 삼성전자주식회사 전압공급유닛 분할을 통한 반도체 소자의 병렬검사 방법
US8620980B1 (en) 2005-09-27 2013-12-31 Altera Corporation Programmable device with specialized multiplier blocks
JP2007205933A (ja) * 2006-02-02 2007-08-16 Nec Electronics Corp 半導体集積回路
US8266198B2 (en) * 2006-02-09 2012-09-11 Altera Corporation Specialized processing block for programmable logic device
US8266199B2 (en) * 2006-02-09 2012-09-11 Altera Corporation Specialized processing block for programmable logic device
US8041759B1 (en) 2006-02-09 2011-10-18 Altera Corporation Specialized processing block for programmable logic device
US8301681B1 (en) 2006-02-09 2012-10-30 Altera Corporation Specialized processing block for programmable logic device
JP2007263866A (ja) * 2006-03-29 2007-10-11 Nec Electronics Corp 半導体集積回路及びそのテスト方法
US7836117B1 (en) 2006-04-07 2010-11-16 Altera Corporation Specialized processing block for programmable logic device
US7822799B1 (en) 2006-06-26 2010-10-26 Altera Corporation Adder-rounder circuitry for specialized processing block in programmable logic device
US8386550B1 (en) 2006-09-20 2013-02-26 Altera Corporation Method for configuring a finite impulse response filter in a programmable logic device
US7930336B2 (en) * 2006-12-05 2011-04-19 Altera Corporation Large multiplier for programmable logic device
US8386553B1 (en) 2006-12-05 2013-02-26 Altera Corporation Large multiplier for programmable logic device
US7814137B1 (en) 2007-01-09 2010-10-12 Altera Corporation Combined interpolation and decimation filter for programmable logic device
US7865541B1 (en) 2007-01-22 2011-01-04 Altera Corporation Configuring floating point operations in a programmable logic device
US8650231B1 (en) 2007-01-22 2014-02-11 Altera Corporation Configuring floating point operations in a programmable device
US8645450B1 (en) 2007-03-02 2014-02-04 Altera Corporation Multiplier-accumulator circuitry and methods
US7949699B1 (en) 2007-08-30 2011-05-24 Altera Corporation Implementation of decimation filter in integrated circuit device using ram-based data storage
US7630259B1 (en) 2007-12-18 2009-12-08 Lattice Semiconductor Corporation Programmable logic device with built in self test
US8959137B1 (en) 2008-02-20 2015-02-17 Altera Corporation Implementing large multipliers in a programmable integrated circuit device
US8244789B1 (en) 2008-03-14 2012-08-14 Altera Corporation Normalization of floating point operations in a programmable integrated circuit device
US8626815B1 (en) 2008-07-14 2014-01-07 Altera Corporation Configuring a programmable integrated circuit device to perform matrix multiplication
US8255448B1 (en) 2008-10-02 2012-08-28 Altera Corporation Implementing division in a programmable integrated circuit device
US8307023B1 (en) 2008-10-10 2012-11-06 Altera Corporation DSP block for implementing large multiplier on a programmable integrated circuit device
US8549055B2 (en) 2009-03-03 2013-10-01 Altera Corporation Modular digital signal processing circuitry with optionally usable, dedicated connections between modules of the circuitry
US8886696B1 (en) 2009-03-03 2014-11-11 Altera Corporation Digital signal processing circuitry with redundancy and ability to support larger multipliers
US8805916B2 (en) * 2009-03-03 2014-08-12 Altera Corporation Digital signal processing circuitry with redundancy and bidirectional data paths
US8645449B1 (en) 2009-03-03 2014-02-04 Altera Corporation Combined floating point adder and subtractor
US8706790B1 (en) 2009-03-03 2014-04-22 Altera Corporation Implementing mixed-precision floating-point operations in a programmable integrated circuit device
US8468192B1 (en) 2009-03-03 2013-06-18 Altera Corporation Implementing multipliers in a programmable integrated circuit device
US8650236B1 (en) 2009-08-04 2014-02-11 Altera Corporation High-rate interpolation or decimation filter in integrated circuit device
US8412756B1 (en) 2009-09-11 2013-04-02 Altera Corporation Multi-operand floating point operations in a programmable integrated circuit device
US8396914B1 (en) 2009-09-11 2013-03-12 Altera Corporation Matrix decomposition in an integrated circuit device
US8539016B1 (en) 2010-02-09 2013-09-17 Altera Corporation QR decomposition in an integrated circuit device
US7948267B1 (en) 2010-02-09 2011-05-24 Altera Corporation Efficient rounding circuits and methods in configurable integrated circuit devices
US8601044B2 (en) * 2010-03-02 2013-12-03 Altera Corporation Discrete Fourier Transform in an integrated circuit device
US8458243B1 (en) 2010-03-03 2013-06-04 Altera Corporation Digital signal processing circuit blocks with support for systolic finite-impulse-response digital filtering
US8484265B1 (en) 2010-03-04 2013-07-09 Altera Corporation Angular range reduction in an integrated circuit device
US8510354B1 (en) 2010-03-12 2013-08-13 Altera Corporation Calculation of trigonometric functions in an integrated circuit device
US8539014B2 (en) * 2010-03-25 2013-09-17 Altera Corporation Solving linear matrices in an integrated circuit device
US8589463B2 (en) 2010-06-25 2013-11-19 Altera Corporation Calculation of trigonometric functions in an integrated circuit device
US8862650B2 (en) 2010-06-25 2014-10-14 Altera Corporation Calculation of trigonometric functions in an integrated circuit device
US8577951B1 (en) 2010-08-19 2013-11-05 Altera Corporation Matrix operations in an integrated circuit device
JP5606880B2 (ja) * 2010-11-11 2014-10-15 ピーエスフォー ルクスコ エスエイアールエル 半導体記憶装置
US8645451B2 (en) 2011-03-10 2014-02-04 Altera Corporation Double-clocked specialized processing block in an integrated circuit device
US9600278B1 (en) 2011-05-09 2017-03-21 Altera Corporation Programmable device using fixed and configurable logic to implement recursive trees
TWI466124B (zh) * 2011-05-27 2014-12-21 Realtek Semiconductor Corp 測試系統
US8812576B1 (en) 2011-09-12 2014-08-19 Altera Corporation QR decomposition in an integrated circuit device
US8949298B1 (en) 2011-09-16 2015-02-03 Altera Corporation Computing floating-point polynomials in an integrated circuit device
US9053045B1 (en) 2011-09-16 2015-06-09 Altera Corporation Computing floating-point polynomials in an integrated circuit device
US9336342B2 (en) * 2011-09-23 2016-05-10 Synopsys, Inc. Memory hard macro partition optimization for testing embedded memories
US8762443B1 (en) 2011-11-15 2014-06-24 Altera Corporation Matrix operations in an integrated circuit device
US8543634B1 (en) 2012-03-30 2013-09-24 Altera Corporation Specialized processing block for programmable integrated circuit device
US9098332B1 (en) 2012-06-01 2015-08-04 Altera Corporation Specialized processing block with fixed- and floating-point structures
US8996600B1 (en) 2012-08-03 2015-03-31 Altera Corporation Specialized processing block for implementing floating-point multiplier with subnormal operation support
US9207909B1 (en) 2012-11-26 2015-12-08 Altera Corporation Polynomial calculations optimized for programmable integrated circuit device structures
US9189200B1 (en) 2013-03-14 2015-11-17 Altera Corporation Multiple-precision processing block in a programmable integrated circuit device
US9348795B1 (en) 2013-07-03 2016-05-24 Altera Corporation Programmable device using fixed and configurable logic to implement floating-point rounding
US9379687B1 (en) 2014-01-14 2016-06-28 Altera Corporation Pipelined systolic finite impulse response filter
CN105575438B (zh) 2014-10-16 2020-11-06 恩智浦美国有限公司 用于测试存储器的方法及装置
US9684488B2 (en) 2015-03-26 2017-06-20 Altera Corporation Combined adder and pre-adder for high-radix multiplier circuit
US9733307B1 (en) 2016-10-20 2017-08-15 International Business Machines Corporation Optimized chain diagnostic fail isolation
US10942706B2 (en) 2017-05-05 2021-03-09 Intel Corporation Implementation of floating-point trigonometric functions in an integrated circuit device
CN111366842B (zh) * 2020-03-09 2022-04-22 广芯微电子（广州）股份有限公司 一种芯片量产测试方法
FR3110261B1 (fr) * 2020-05-18 2022-04-29 Idemia Starchip Procede et systeme de test d’un circuit integre
CN113299335B (zh) * 2021-05-24 2023-01-31 长江存储科技有限责任公司 一种存储器件的测试方法、测试系统及测试设备

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3961251A (en) 1974-12-20 1976-06-01 International Business Machines Corporation Testing embedded arrays
US4481627A (en) 1981-10-30 1984-11-06 Honeywell Information Systems Inc. Embedded memory testing method and apparatus
JPH06203597A (ja) 1992-09-25 1994-07-22 Nec Corp ダイナミックｒａｍ
US5535164A (en) 1995-03-03 1996-07-09 International Business Machines Corporation BIST tester for multiple memories
US5663965A (en) 1995-10-06 1997-09-02 International Business Machines Corp. Apparatus and method for testing a memory array
US5680543A (en) * 1995-10-20 1997-10-21 Lucent Technologies Inc. Method and apparatus for built-in self-test with multiple clock circuits
US5987635A (en) * 1996-04-23 1999-11-16 Matsushita Electric Industrial Co., Ltd. Semiconductor integrated circuit device capable of simultaneously performing self-test on memory circuits and logic circuits
JPH1011996A (ja) 1996-06-24 1998-01-16 Advantest Corp メモリ試験装置
US5954830A (en) 1997-04-08 1999-09-21 International Business Machines Corporation Method and apparatus for achieving higher performance data compression in ABIST testing by reducing the number of data outputs
US5996097A (en) 1997-04-28 1999-11-30 International Business Machines Corporation Testing logic associated with numerous memory cells in the word or bit dimension in parallel
US6044481A (en) 1997-05-09 2000-03-28 Artisan Components, Inc. Programmable universal test interface for testing memories with different test methodologies
KR100240662B1 (ko) * 1997-09-25 2000-01-15 윤종용 제이태그에 의한 다이나믹램 테스트장치
KR100252040B1 (ko) 1997-10-08 2000-05-01 윤종용 불휘발성 메모리 내장 반도체 장치 테스트 방법
US6111800A (en) 1997-12-05 2000-08-29 Cypress Semiconductor Corporation Parallel test for asynchronous memory
KR100280442B1 (ko) 1998-02-05 2001-02-01 김영환 디램의병렬테스트회로
US6430718B1 (en) * 1999-08-30 2002-08-06 Cypress Semiconductor Corp. Architecture, circuitry and method for testing one or more integrated circuits and/or receiving test information therefrom
US6587979B1 (en) * 1999-10-18 2003-07-01 Credence Systems Corporation Partitionable embedded circuit test system for integrated circuit
US6650589B2 (en) * 2001-11-29 2003-11-18 Intel Corporation Low voltage operation of static random access memory

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101292171B (zh) * 2005-10-24 2012-04-18 Nxp股份有限公司 Ic测试方法和设备
CN101371153B (zh) * 2006-01-06 2011-09-28 Nxp股份有限公司 Ic测试方法和装置
CN101515479A (zh) * 2009-03-30 2009-08-26 北京中星微电子有限公司 一种提高扫描链测试覆盖率的方法和装置
CN103890597A (zh) * 2011-10-25 2014-06-25 泰拉丁公司 用于控制测试块并行性的支持简化配置的测试系统
CN103576076A (zh) * 2012-07-27 2014-02-12 飞思卡尔半导体公司 用于执行扫描测试的系统和方法
CN103576076B (zh) * 2012-07-27 2019-02-01 恩智浦美国有限公司 用于执行扫描测试的系统和方法
CN105891695B (zh) * 2014-05-07 2019-01-11 紫光同芯微电子有限公司 一种基于单io的ic卡并行测试方法
CN105891695A (zh) * 2014-05-07 2016-08-24 北京同方微电子有限公司 一种基于单io的ic卡并行测试方法
CN106291313A (zh) * 2015-06-10 2017-01-04 飞思卡尔半导体公司 用于测试集成电路的方法和设备
CN107731264A (zh) * 2016-08-10 2018-02-23 英飞凌科技股份有限公司 非易失性存储器测试
CN107731264B (zh) * 2016-08-10 2021-09-28 英飞凌科技股份有限公司 非易失性存储器测试
CN106653098A (zh) * 2017-01-04 2017-05-10 盛科网络（苏州）有限公司 针对逻辑和cpu均可读写存储器的测试方法
CN109060522A (zh) * 2018-06-28 2018-12-21 苏州勃朗特半导体存储技术有限公司 针对m.2固态硬盘压拉测试的电压控制系统

Also Published As

Publication number Publication date
CN1243376C (zh) 2006-02-22
KR100522520B1 (ko) 2005-10-18
TW200422634A (en) 2004-11-01
US7103814B2 (en) 2006-09-05
KR20040036542A (ko) 2004-04-30
TWI245913B (en) 2005-12-21
US20040083412A1 (en) 2004-04-29

Similar Documents

Publication Publication Date Title
CN1243376C (zh) 对半导体器件进行并行测试的装置和方法
US7225379B2 (en) Circuit and method for testing semiconductor device
Hetherington et al. Logic BIST for large industrial designs: Real issues and case studies
Pandey et al. Reconfiguration technique for reducing test time and test data volume in Illinois scan architecture based designs
US5768289A (en) Dynamically controlling the number of boundary-scan cells in a boundary-scan path
US20040006729A1 (en) Hierarchical test methodology for multi-core chips
KR100267096B1 (ko) 디버그 및 제조 테스트 목적을 위한 적응적 스캔 체인
US20160349320A1 (en) Remote bus wrapper for testing remote cores using automatic test pattern generation and other techniques
US7620866B2 (en) Test access architecture and method of testing a module in an electronic circuit
US5394403A (en) Fully testable chip having self-timed memory arrays
US5781560A (en) System testing device and method using JTAG circuit for testing high-package density printed circuit boards
EP2587273A1 (en) Dynamic clock domain bypass for scan chains
US8671320B2 (en) Integrated circuit comprising scan test circuitry with controllable number of capture pulses
US6553530B1 (en) Integrated circuit devices that include self-test apparatus for testing a plurality of functional blocks and methods of testing same
CN101144847B (zh) 集成电路和指定集成电路的方法
EP0469238B1 (en) Reduced delay circuits for shift register latch scan strings
US8700962B2 (en) Scan test circuitry configured to prevent capture of potentially non-deterministic values
KR100394575B1 (ko) 반도체 메모리의 테스트용 핀을 통한 내부정보 선택적출력방법 및 그에 따른 출력회로
US20130311843A1 (en) Scan controller configured to control signal values applied to signal lines of circuit core input interface
US20040128604A1 (en) Memory bypass with support for path delay test
US7913132B2 (en) System and method for scanning sequential logic elements
US6341092B1 (en) Designing memory for testability to support scan capability in an asic design
US20040098643A1 (en) Method and apparatus for accessing internal RAMs during diagnostic testing
Franklin et al. Embedded RAM testing
US6920582B2 (en) Method and apparatus for testing circuit modules

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20060222

Termination date: 20181023