CN1470069A - 包含具有埋置电容器的衬底的电子组装件及其制造方法 - Google Patents
包含具有埋置电容器的衬底的电子组装件及其制造方法 Download PDFInfo
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Abstract
为了降低开关噪声,集成电路管芯的电源端子可以被耦合到多层陶瓷衬底中的至少一个埋置电容器的各个端子。在一个实施方案中,电容器由至少一个高介电常数层组成。在另一个实施方案中,几个高介电常数层与导电层交替。作为变通,电容器可以包含至少一个埋置的分立电容器。还描述了一种电子系统、一种数据处理系统、以及各种制造方法。
Description
发明的技术领域
本发明一般涉及到电子封装件。更确切地说,本发明涉及到一种包括衬底的电子组装件,此衬底具有一个或多个用来降低高频集成电路中的开关噪声的埋置电容器,本发明还涉及到相关的制造方法。
发明的背景
通常,借助于将集成电路(IC)物理上和电学上耦合到由有机材料或陶瓷材料制成的衬底,而将集成电路通常组装在封装件中。一个或多个这种IC封装件可以被物理上和电学上耦合到印刷电路板(PCB),从而形成“电子组装件”。此“电子组装件”可以是“电子系统”的部件。此处,“电子系统”被广义地定义为任何一种包含“电子组装件”的产品。电子系统的例子包括计算机(例如台式计算机、膝上计算机、手持计算机、服务器等)、无线通信装置(例如蜂窝电话、无线电话、传呼机等)、计算机的外设(例如打印机、扫描仪、监视器等)、娱乐装置(例如电视机、收音机、立体声、录音机、CD唱机、录象机、MP3(动画专家组,音频层3等)唱机、等等。
在电子系统领域中,为了提高设备的性能和降低生产成本,在厂家之间存在着持续不断的竞争压力。对于IC在衬底上的封装来说更是如此,每一代新的封装方法必定提供更好的性能而尺寸通常更小即更紧凑。
IC衬底可以包含大量被选择性地图形化以提供金属互连线(此处称为“迹线”)的隔离的金属层以及一个或多个安装在衬底的一个或多个表面上的电子元件。这些电子元件通过包括衬底迹线的多层导电路径,在功能上被连接到电子系统的其它元件。衬底迹线通常承载着系统各个电子元件例如IC之间传输的信号。某些IC具有较大量的输入/输出(I/O)端子以及大量的电源端子和接地端子。大量的I/O端子、电源端子、以及接地端子要求衬底含有较大量的迹线。某些衬底要求多层迹线来提供所有的系统互连。
位于不同层中的迹线通常被制作在板中的通道孔(也称为“镀通孔”)电连接。可以借助于穿过衬底的某些层或所有层制作孔,然后对孔的内表面进行电镀或用诸如铜或钨之类的导电材料对孔进行填充而形成通道孔。
将IC安装在衬底上的一种常规方法被称为“受控崩塌芯片连接”(C4)。在制造C4封装件的过程中,利用可回流的焊料块或焊料球,IC元件的导电端子即小岛(通常称为“电接触”)被直接焊接到衬底表面上的相应小岛。C4工艺由于其牢固性和简单性而被广泛地使用。
处理器之类的IC内部电路工作于越来越高的时钟频率,且当IC工作于越来越高的功率电平时,开关噪声可能提高到无法接受的水平。
由于上述的原因和本技术熟练人员阅读和理解本说明书之后将明了的下述其它原因,在本技术领域中,对于尽量减少诸如开关噪声之类的与高时钟频率和高功率供给相关的问题的用来在衬底上封装IC的方法和装置,存在着很大需求。
附图的简要描述
图1是根据本发明一个实施方案的至少组合一个具有埋置电容器的电子组装件的电子系统的方框图;
图2示出了根据本发明一个实施方案的具有埋置电容器的多层衬底的剖面图;
图3示出了根据本发明另一个实施方案的具有埋置电容器的多层衬底的剖面图;
图4示出了根据本发明一个变通实施方案的具有埋置分立电容器的多层衬底的剖面图;
图5示出了电容对能够用于根据本发明一个实施方案的具有埋置电容器的衬底的各种介质材料的面积的曲线;
图6是根据本发明一个实施方案制造包含埋置电容器的衬底的方法的流程图;而
图7是根据本发明一个实施方案制造具有包含埋置电容器的衬底的电子组装件的方法的流程图。
本发明实施方案的详细描述
在本发明实施方案的下列详细描述中,参照构成本发明一部分的附图,其中用举例的方法示出了可以实施本发明的具体优选实施方案。对这些实施方案进行了足够详细的描述,以便本技术领域的熟练人员能够实施本发明,且应该理解的是,可以利用其它的实施方案并作出逻辑的、机械的和电学的改变而不偏离本发明的构思与范围。因此,下列描述不被认为是限制性的,本发明的范围仅仅由所附权利要求来定义。
本发明借助于在多层衬底中埋置一个或多个去耦电容器而为与运行于高时钟速度和高功率电平的集成电路现有封装技术相关的功率发送问题提供了一种解决办法。此处描述了各种实施方案。在一个实施方案中,IC管芯被直接安装到含有埋置电容器的多层衬底。埋置的电容器可以是分立电容器,或者是一层或多层容性材料。
图1是根据本发明一个实施方案的至少组合一个具有埋置电容器的电子组装件4的电子系统1的方框图。电子系统1仅仅是能够采用本发明的电子系统的一个例子。在此例子中,电子系统1包含数据处理系统,此数据处理系统包括用来耦合系统各个元件的系统总线2。系统总线2在电子系统1的各个元件之间提供通信连接,并能够实现为单个总线、组合总线,或以任何其它适当的方式加以实现。
电子组装件4被耦合到系统总线2。电子组装件4可以包括任何电路或电路组合。在一个实施方案中,电子组装件4包括可以是任何类型的处理器6。如此处所用的那样,“处理器”意味着任何类型的计算电路,例如但不局限于微处理器、微控制器、复杂指令系统计算(CISC)微处理器、简化指令系统计算(RISC)微处理器、甚长指令字(VLIW)微处理器、图形处理器、数字信号处理器(DSP)、或任何其它类型的处理器或处理电路。
能够包括在电子组装件4中的其它类型的电路是定制电路、专用集成电路(ASIC)等,例如用于蜂窝电话、传呼机、便携式计算机、对讲机、以及相似电子系统之类的无线装置的一种或多种电路(例如通信电路7)。此IC能够执行任何其它类型的功能。
电子系统1还可以包括外部存储器10,外部存储器10又可以包括适合于特殊用途的一个或多个存储器,例如以随机存取存储器(RAM)形式出现的主存储器12、一个或多个硬盘驱动器14、和/或一个或多个处置诸如软盘、光盘(CD)、数字视频光盘(DVD)之类的移动媒质16的驱动器。
电子系统1还可以包括显示器件8、扬声器9、以及键盘和/或控制器20,键盘和/或控制器20可以包括鼠标、跟踪球、游戏控制器、声音识别装置、或使系统用户能够将信息输入到电子系统1和/或从电子系统1接收信息的任何其它装置。
图2示出了根据本发明一个实施方案的具有埋置电容器的多层衬底210的剖面图。衬底210在其一个表面上具有多个小岛211-213,这些小岛能够经由焊料球或焊料块208被分别耦合到IC管芯200上的各个引线或导电区201-203。引线201被耦合到IC管芯200的信号线,引线202被耦合到Vcc,而引线203被耦合到Vss。可以理解的是,虽然完全相同的参考号被用于承载信号电平的二个导电路径,亦即包含由参考号201、208、211、以及221-223表示的结构的路径,但这些信号可以是不同的。信号路径结构可以包括表示为陶瓷衬底210中诸如信号导体235-237的导电层的各种信号导体。
诸如信号凸块201的信号引线或凸块,通常以例如几行深(为了简便起见,管芯各侧仅仅示出了一行)的形式被安排在管芯外围。
衬底210可以包括多个Vcc、Vss和信号导体,为了简便起见,仅仅示出了其中的一些。
衬底210包含一对埋置电容器。各个电容器230包含一对电容平板226和229,在电容平板226和229之间以及在各个电容器230之间,具有高介电常数(Dk)层228。各个电容器230的一个电容平板226可以经由导体215、小岛213和焊料球208被耦合到管芯200上的Vss端子203。各个电容器230的另一个电容平板229可以经由导体227、小岛212和焊料球208被耦合到管芯200上的Vcc端子202。
此处使用的术语“高介电常数层”意味着诸如高介电常数钛酸盐陶瓷层之类的高介电常数材料层;诸如例如用溶胶-凝胶或金属-有机化学气相淀积(MOCVD)方法淀积的钛酸盐膜之类的高介电常数介质膜;或任何其它类型的高介电常数材料层。
衬底210可以配备有一个或多个埋置电容器230。
管芯200和衬底210可以是任何类型的。在一个实施方案中,管芯200是处理器,而衬底210是多层陶瓷衬底。
在图2所示的实施方案中,金属化的电源通道孔215和227能够将电容器210的Vss和Vcc电容平板226和229分别连接到分布在管芯200中心区域中的能够分别包含较大量Vss和Vcc管芯凸块的管芯相应区域。此大的平行连接确保了非常低的电感(例如小于1皮亨),并提高了整个IC封装结构的电流承载能力。
本发明同样可应用于信号迹线不出现在管芯外围的实施方案以及Vcc和Vss迹线被提供在管芯上任何地方的实施方案。
可以理解,虽然图2中电源通道孔215和227的间距被示为相同于管芯凸块间距,但电源通道孔215和227的间距可以不同于管芯凸块的间距。同样,虽然信号通道孔223的间距被示为比管芯凸块间距更宽,但在另一个实施方案中也可以是相同的。通道孔的几何尺寸,包括通道孔间距,能够以任何适当的方式根据本技术领域熟练人员所知的设计参数而变化。
利用陶瓷衬底技术能够实现各种实施方案。
具有埋置电容器的衬底的一个重要目的是提供相当靠近管芯的较大的电容,以便在IC运行时降低电抗性感应耦合的影响,特别是在高的时钟速度下。
图3示出了根据本发明另一个实施方案的具有埋置电容器的衬底310的剖面图。在图3所示的实施方案中,衬底310可以被耦合到另一个衬底320。衬底320可以相似于衬底310,也可以在其反面上具有IC管芯(未示出),或可以是印刷电路板(PCB)或其他类型的衬底。衬底320的引线或导电区域334、339和319可以经由焊料球338被耦合到衬底310的相应小岛331、332和317。
衬底310的内部结构可以相似于上述衬底210的内部结构(图2)。这样,衬底310在其一个表面上就具有多个能够经由焊料球308分别被耦合到IC管芯300上的引线或导电区域301-303的小岛311-313。引线301被耦合到IC管芯300的信号线,引线302被耦合到Vcc,而引线303被耦合到Vss。可以理解的是,虽然完全相同的参考号被用于二种承载信号电平的导电路径,亦即包含由参考号301、308、311以及321-323表示的结构的路径,但这些信号也可以是不同的。信号路径结构可以包括诸如信号导体335-337之类的示为衬底310中的导电层的各种信号导体。
衬底310可以包括多个Vcc、Vss和信号导体,为了简便起见,仅仅示出了其中的几个。
衬底310可以包含一对埋置电容器330,各个埋置电容器330包含一对电容平板326和329,在电容平板326和329之间以及在各个电容器330之间,有高Dk层340。各个电容器330的一个电容平板326可以经由通道孔区段315、小岛313和焊料球308被耦合到管芯300上的Vss端子303。也可以利用通道孔区段316、小岛317和焊料球338将平板326耦合到衬底320上的Vss端子319。各个电容器330的另一个电容平板329可以经由通道孔区段327、小岛312和焊料球308被耦合到管芯300上的Vcc端子302。也可以利用通道孔区段328、小岛332和焊料球338将平板329耦合到衬底320上的Vcc端子339。
衬底310可以配备有一个或多个埋置电容器330。
管芯300和衬底310可以是任何类型的。在一个实施方案中,管芯300是处理器,衬底310是多层陶瓷衬底,而衬底320是PCB。在另一个实施方案中,衬底320是陶瓷衬底。
在图3所示的实施方案中,金属化的通道孔315、316(应该指出的是,图2和3所示的各个通道孔区段,例如通道孔区段315、316以及327、328,可以是分立的通道孔或连续的通道孔)以及327、328,能够将电容器310的Vss和Vcc电容平板326和329分别连接到管芯的相应区域,这些区域能够分别包含较大量的分布在管芯各个中心区域300的Vss和Vcc管芯凸块303和302。这一大的平行连接确保了非常低的电感(例如小于1皮亨)。
利用陶瓷衬底工艺,能够实现衬底310和320的各种实施方案。衬底310和320的结构,包括所用材料的类型、尺寸、层的数量、电源导体和信号导体的布局、等等,根据它们构成其一部分的电子组装件的要求,可以是相似的或不同的。
可以理解,衬底310顶部的小岛/凸块间距需要与管芯300的凸块间距相匹配,且衬底310底部的小岛/凸块间距需要与衬底320的焊点间距相匹配。虽然在图3所示的实施方案中电源通道孔315和327的间距在衬底320的顶部和底部是相同的,且衬底320底部的信号通道孔间距比衬底320顶部的更宽,但为了满足设计限制和目的,能够以任何适当的方式改变间距关系。
图4示出了根据本发明一个变通实施方案的具有二个分立的电容器430和440的多层衬底410的剖面图。衬底410能够包括多层Vcc、Vss和信号导体,被用来在其上安装管芯400。衬底410的引线402被置于Vcc电位,并可以经由某个焊料球401被耦合到IC管芯400上的相应导电区域(未示出)。同样,小岛403被置于Vss电位,并可以经由其它的焊料球401被耦合到IC管芯400上的相应区域(未示出)。
分立的电容器430和440可以是任何适当类型的。在一个实施方案中,各个分立电容器430和440包含一对上端子426和428以及一对下端子423和425。然而,也可以采用具有更多端子或更少端子和/或具有仅仅耦合到衬底410上部的端子的分立电容器。例如,在上述的相关发明的一个实施方案中,埋置在插入部分中的单个分立电容器具有二个仅仅耦合到插入部分上部的端子。相似的电容性结构同样能够被应用于本发明的实施方案,亦即具有仅仅耦合到衬底410上部的端子的实施方案中。
小岛402被包括电源通道孔404、导电层406和电源通道孔412的路径耦合到埋置电容器430的上部端子426。小岛403被包括电源通道孔405、导电层407和电源通道孔413的路径耦合到埋置电容器430的其它上部端子428。
小岛431被包括电源通道孔418、导电层416和电源通道孔422的路径耦合到埋置电容器430的下部端子423。小岛432被包括电源通道孔419、导电层417和电源通道孔424的路径耦合到埋置电容器430的其它下部端子425。
如图4所示,可以对电容器440的端子进行相似于电容器430的Vcc和Vss连接。
如本技术领域一般熟练人员可以理解的那样,在衬底410中还能够提供各种信号路径(为了简便起见而未示出,但包含IC管芯400的信号区域、某些焊料球410、衬底410上的适当的小岛例如小岛408和434、以及衬底410中的信号面和信号通道孔例如信号通道孔409)。
埋置电容器430和440可以是任何适当构造的。在一个实施方案中,这些电容器是用常规陶瓷芯片电容器工艺制造的陶瓷芯片电容器。虽然为了描述简便起见而示出了二个电容器430和440,但在图4所示的实施方案中,可以使用不同数目的电容器,包括仅仅使用一个电容器。
图2-4仅仅是说明性的而没有按比例绘制。其某些部分可能被夸大,而其它部分可能被缩小了。图2-4被用来说明本技术领域一般熟练人员能够理解并恰当地实施的本发明的各种实现方法。
制造
可以用诸如但不局限于高温共烧陶瓷(HTCC)工艺、高热膨胀系数(HITCE)工艺、或玻璃陶瓷工艺之类的常规工艺,来制造多层陶瓷衬底。
虽然在陶瓷工艺中已知借助于将诸如Al2O3之类的常规陶瓷薄膜(例如2密尔)夹在金属片之间而在陶瓷衬底中埋置低Dk电容器,但在本发明中的一个实施方案中,采用了高Dk层的多层叠层。例如用来制造陶瓷芯片电容器的高Dk层可以在市场上购得。诸如钛酸盐颗粒之类的适当的高Dk材料可以被插入到常规陶瓷基质中。在本发明中,诸如BaTiO3的高Dk多层叠层能够提供高达10_F/cm2的电容,相比之下,低Dk层的电容仅仅在每平方厘米毫微法拉的范围内。
在一个变通实施方案中,可以用熟知的技术,例如金属有机化学气相淀积(MOCVD)工艺或溶胶-凝胶工艺,在陶瓷衬底中形成诸如钛酸盐膜,例如(BaxSr1-x)TiO3(BST)或PbZrTiO3(PZT)或Ta2O5或SrTiO3之类的高Dk层,在溶胶-凝胶工艺中,作为液体中的固体颗粒胶状悬浮物的溶胶,由于固体颗粒的生长和相互连接而转变成凝胶。
在二种情况下,高Dk材料都能够在与陶瓷工艺一致的温度范围(例如600-1000℃)内被埋置。
关于图4所示的分立电容器430和440被埋置在衬底410中的实施方案,借助于任何常规技术,例如冲压或激光烧蚀,能够接近电容器430和440,且利用与工艺温度要求一致的任何适当的金属化工艺,衬底410的Vcc和Vss导体能够被耦合到电容器430和440的端子。
电容的估计
可以用方程1来估计图3所示实施方案的电容数值。
方程(1) C=A*_r*-o/d
其中:A=电容器尺寸(平方米)
_r=介电常数8.854×10-12法拉/米
_o=绝缘体的介电常数
d=介电层的厚度(米)
图5示出了能够用于根据本发明一个实施方案的具有埋置电容器的衬底的各种介电材料的电容(单位为毫微法拉)对电容器边长(单位为微米)的曲线。图5所示的是下列介电材料的曲线:曲线501是PZT(Dk=2000)的,曲线502是BaTiO3(Dk=1000)的,曲线503是BST(Dk=500)的,曲线504是SrTiOx(Dk=200)的,而曲线505是TaOx(Dk=25)的。
图5总结了用所示各种钛酸盐和氧化物材料能够得到的电容的大致范围。当使用高介电常数陶瓷层(例如用BaTiO3浸渍的陶瓷层)时,所示的数值对应于用含有40个这种层的叠层中Vcc层和Vss层之间的厚度为10微米的层通常能够得到的最大电容。
在用溶胶-凝胶或MOCVD实施方案形成的介质(例如PZT、BST、SrTiO3、或Ta2O5)的情况下,计算得到的数值对应于所示介质的0.25微米膜。
为了满足任何给定实施方案的电容要求,可以按需要层叠多个电容器层。
图6是根据本发明一个实施方案制造包含埋置电容器的衬底的方法的流程图。此方法开始于601。
在603中,在衬底结构中至少制作了一个具有第一和第二端子的电容器。在一个实施方案中,此结构是多层陶瓷结构,虽然在其它的实施方案中此结构可以由陶瓷材料之外的材料组成。电容器包含(1)至少一个夹在各个导电层之间的高介电常数层;或者,电容器是(2)分立电容器。
在605中,在衬底结构中制作第一和第二电源节点。如此处所用的那样,术语“电源节点”指的是地节点(例如Vss)或与地有电位差的电源节点(例如Vcc)。
在607中,在衬底结构的表面上制作多个小岛,包括耦合到电容器第一端子和耦合到第一电源节点的第一小岛以及耦合到电容器第二端子和耦合到第二电源节点的第二小岛。第一和第二小岛被定位成耦合到待要被并列到衬底结构表面且物理上固定于其上的管芯(例如图2的IC管芯200)的第一和第二电源节点。此方法在609处结束。
图7是根据本发明一个实施方案制造具有包含埋置电容器的衬底的电子组装件的方法的流程图。此方法开始于701。
在703中,提供具有第一和第二电源节点的管芯。
在705中,提供具有第三和第四电源节点的衬底。此衬底包含至少一个具有第一和第二端子的电容器。此电容器包含(1)至少一个夹在各个导电层之间的高介电常数层;或者此电容器是分立电容器。此衬底还包含其表面上的多个小岛,包括耦合到电容器第一端于和耦合到第三电源节点的第一小岛以及耦合到电容器第二端子和耦合到第四电源节点的第二小岛。
在707中,第一和第二小岛被分别耦合到管芯的第一和第二电源节点。此方法在709处结束。
图6和7所示方法的上述各个操作,可以按不同于此处所述的顺序执行。
结论
本发明提供了一种电子组装件以及尽量减少诸如与高时钟频率和高功率发送相关的开关噪声之类问题的方法。利用能够满足例如高性能处理器的功率发送要求的具有低电感的埋置去耦电容器,本发明提供了可调节的大电容(例如大于每平方厘米10毫法拉)。结合了本发明的电子系统能够在更高的时钟频率下运行,因而在商业上更有吸引力。
如此处所示,本发明能够在大量不同的实施方案中实现,包括衬底、电子组装件、电子系统、数据处理系统、制作衬底的方法、以及制作电子组装件的方法。对于本技术领域的一般熟练人员来说,其它的实施方案是显而易见的。电容元件、材料的选择、几何形状、以及电容都能够改变以适应特定的封装要求。埋置电容器的特定几何形状,就其方位、尺寸、数量、位置及其组成元件的组分而言,是非常灵活的。
虽然各个实施方案已经显示其中的信号迹线绕外围而提供,且其中的Vcc和Vss迹线被提供在管芯中心,但本发明同样可应用于信号迹线出现在外围以外的实施方案,并可应用于Vcc和Vss被提供在管芯上任何地方的实施方案。
而且,本发明不局限于用在C4封装件中,而是能够用于此处所述本发明的特点能提供优点的任何其它类型的IC封装件中。
虽然此处已经描述了具体的实施方案,但本技术领域的一般熟练人员可以理解的是,任何适合于达到同样目的的安排都可以代替所示的具体实施方案。本申请被认为覆盖了本发明的任何修正或改变。因此,显然本发明仅仅受权利要求及其等效物的限制。
Claims (30)
1.一种用来安装管芯的多层陶瓷衬底,它包含:
具有第一和第二端子的埋置电容器;以及
其第一表面上的第一多个小岛,包括耦合到第一端子的第一小岛以及耦合到第二端子的第二小岛,其中的第一和第二小岛被定位成耦合到管芯的相应电源节点。
2.权利要求1所述的多层陶瓷衬底,还包含其第二表面上的第二多个小岛,包括耦合到第一端子的第三小岛以及耦合到第二端子的第四小岛。
3.权利要求2所述的多层陶瓷衬底,其中的第三和第四节点被定位成耦合到多层陶瓷衬底下面的额外衬底的相应电源节点。
4.权利要求1所述的多层陶瓷衬底,其中的电容器包含至少一个高介电常数层。
5.权利要求1所述的多层陶瓷衬底,其中的电容器包含多个高介电常数层。
6.权利要求5所述的多层陶瓷衬底,其中的电容器包含多个与高介电常数层交替的导电层,使交替的导电层分别被耦合到第一和第二小岛。
7.权利要求1所述的多层陶瓷衬底,其中的电容器包含至少一个埋置的分立电容器。
8.一种电子组装件,它包含:
包含第一和第二电源节点的管芯;
多层陶瓷衬底,它包含:
分别耦合到第一和第二电源节点的第三和第四电源节点;以及
第一端子耦合到第三电源节点而第二端子耦合到第四电源节点的电容器。
9.权利要求8所述的电子组装件,其中的电容器包含至少一个高介电常数层。
10.权利要求8所述的电子组装件,其中的电容器包含多个高介电常数层。
11.权利要求10所述的电子组装件,其中的电容器包含多个与高介电常数层交替的导电层,使交替的导电层分别被耦合到第一和第二小岛。
12.权利要求8所述的电子组装件,其中的电容器包含至少一个埋置的分立电容器。
13.一种电子系统,它包含管芯耦合到多层陶瓷衬底的电子组装件,此衬底包含至少一个第一和第二端子耦合到管芯第一和第二电源节点的埋置电容器。
14.权利要求13所述的电子系统,其中的电容器包含至少一个高介电常数层。
15.权利要求13所述的电子系统,其中的电容器包含多个高介电常数层。
16.权利要求15所述的电子系统,其中的电容器包含多个与高介电常数层交替的导电层,使交替的导电层分别被耦合到第三和第四电源节点。
17.权利要求13所述的电子系统,其中的电容器包含至少一个埋置的分立电容器。
18.一种数据处理系统,它包含:
耦合数据处理系统中各个元件的总线;
耦合到总线的显示器;
耦合到总线的外部存储器;以及
耦合到总线的处理器,并包含电子组装件,它包括:
包含第一和第二电源节点的管芯;以及
多层陶瓷衬底,它包含第一端子耦合到第一电源节点而第二端子耦合到第二电源节点的电容器。
19.权利要求18所述的数据处理系统,其中的电容器包含至少一个高介电常数层。
20.权利要求18所述的数据处理系统,其中的电容器包含多个高介电常数层。
21.权利要求20所述的数据处理系统,其中的电容器包含多个与高介电常数层交替的导电层,使交替的导电层分别被耦合到第一和第二端子。
22.权利要求18所述的数据处理系统,其中的电容器包含至少一个埋置的分立电容器。
23.一种用来制作多层陶瓷衬底以封装管芯的方法,它包含:
在衬底中制作至少一个具有第一和第二端子的电容器;
在衬底中制作第一和第二电源节点;以及
在衬底表面上制作多个小岛,包括耦合到第一端子和耦合到第一电源节点的第一小岛以及耦合到第二端子和耦合到第二电源节点的第二小岛,其中的第一和第二小岛被定位成耦合到管芯的第一和第二电源节点。
24.权利要求23所述的方法,其中的至少一个电容器由多个高介电常数层组成。
25.权利要求24所述的方法,其中的至少一个电容器由多个与高介电常数层交替的导电层组成,使交替的导电层分别被耦合到第一和第二小岛。
26.权利要求23所述的方法,其中的至少一个电容器由至少一个埋置的分立电容器组成。
27.一种制作电子组装件的方法,它包含:
提供具有第一和第二电源节点的管芯;
提供衬底,它包含:
第三和第四电源节点;
至少一个具有第一和第二端子的电容器;以及
其表面上的多个小岛,包括耦合到第一端子和耦合到第三电源节点的第一小岛以及耦合到第二端子和耦合到第四电源节点的第二小岛;以及
将第一和第二小岛耦合到第一和第二电源节点。
28.权利要求27所述的方法,其中的至少一个电容器由多个高介电常数层组成。
29.权利要求28所述的方法,其中的至少一个电容器由多个与高介电常数层交替的导电层组成,使交替的导电层分别被耦合到第一和第二小岛。
30.权利要求27所述的方法,其中的至少一个电容器由至少一个埋置的分立电容器组成。
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CN100492628C CN100492628C (zh) | 2009-05-27 |
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US (1) | US6611419B1 (zh) |
EP (2) | EP1358675B1 (zh) |
JP (1) | JP2004505469A (zh) |
KR (1) | KR100591217B1 (zh) |
CN (1) | CN100492628C (zh) |
AT (1) | ATE360889T1 (zh) |
AU (1) | AU2001280850A1 (zh) |
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-
2000
- 2000-07-31 US US09/631,037 patent/US6611419B1/en not_active Expired - Lifetime
-
2001
- 2001-07-26 CN CNB01802999XA patent/CN100492628C/zh not_active Expired - Fee Related
- 2001-07-26 DE DE60128145T patent/DE60128145T2/de not_active Expired - Lifetime
- 2001-07-26 AT AT01959277T patent/ATE360889T1/de not_active IP Right Cessation
- 2001-07-26 KR KR1020027004176A patent/KR100591217B1/ko not_active IP Right Cessation
- 2001-07-26 WO PCT/US2001/023721 patent/WO2002011207A2/en active IP Right Grant
- 2001-07-26 EP EP01959277A patent/EP1358675B1/en not_active Expired - Lifetime
- 2001-07-26 JP JP2002516833A patent/JP2004505469A/ja active Pending
- 2001-07-26 EP EP04025966A patent/EP1515365B1/en not_active Expired - Lifetime
- 2001-07-26 AU AU2001280850A patent/AU2001280850A1/en not_active Abandoned
Also Published As
Publication number | Publication date |
---|---|
KR20020042698A (ko) | 2002-06-05 |
EP1515365A2 (en) | 2005-03-16 |
DE60128145T2 (de) | 2008-01-03 |
EP1358675B1 (en) | 2007-04-25 |
WO2002011207A2 (en) | 2002-02-07 |
KR100591217B1 (ko) | 2006-06-22 |
EP1358675A2 (en) | 2003-11-05 |
EP1515365A3 (en) | 2006-10-04 |
EP1515365B1 (en) | 2010-03-31 |
US6611419B1 (en) | 2003-08-26 |
JP2004505469A (ja) | 2004-02-19 |
DE60128145D1 (de) | 2007-06-06 |
AU2001280850A1 (en) | 2002-02-13 |
WO2002011207A3 (en) | 2003-08-28 |
CN100492628C (zh) | 2009-05-27 |
ATE360889T1 (de) | 2007-05-15 |
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