CN1433569A - 一种制造功率mos场效应管的方法 - Google Patents

一种制造功率mos场效应管的方法 Download PDF

Info

Publication number
CN1433569A
CN1433569A CN01810604A CN01810604A CN1433569A CN 1433569 A CN1433569 A CN 1433569A CN 01810604 A CN01810604 A CN 01810604A CN 01810604 A CN01810604 A CN 01810604A CN 1433569 A CN1433569 A CN 1433569A
Authority
CN
China
Prior art keywords
groove
body region
epitaxial loayer
field effect
oxide
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN01810604A
Other languages
English (en)
Other versions
CN1230880C (zh
Inventor
理查德A·布兰查德
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
General Semiconductor Inc
Original Assignee
General Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US09/586,407 external-priority patent/US6593619B1/en
Application filed by General Semiconductor Inc filed Critical General Semiconductor Inc
Publication of CN1433569A publication Critical patent/CN1433569A/zh
Application granted granted Critical
Publication of CN1230880C publication Critical patent/CN1230880C/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • H01L22/26—Acting in response to an ongoing measurement without interruption of processing, e.g. endpoint detection, in-situ thickness measurement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
    • H01L21/2255—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer comprising oxides only, e.g. P2O5, PSG, H3BO3, doped oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
    • H01L21/2257—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer being silicon or silicide or SIPOS, e.g. polysilicon, porous silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs

Abstract

一种制造高电压MOS场效应管的方法，其中提供了一个第一导电型的衬底(2)，在该衬底上沉积一个也是第一导电型的外延层(1)，在该外延层的漂移区中形成多个沟槽(44，46)，该沟槽由包括第二导电型掺杂物的材料填充，该沟槽从第一和第二主体区(5a，6a，5b，6b)朝着该衬底的方向扩展，并且该掺杂物从该沟槽扩散进入相邻的沟槽的外延层部分。此外，击穿电压被在该外延层中测量，并且与一个想要的击穿电压相比，通过使用在扩散时间和击穿电压之间的预先确定的关系确定一个附加的扩散时间，并且对于所述附加的扩散时间实施进一步的扩散步骤。

Description

一种制造功率MOS场效应管的方法
相关申请
本申请是在2000年6月2日申请的美国专利申请，序列号09/586,407，称作“具有低导通电阻的高电压功率MOS场效应管”的后续申请。
发明领域
本发明通常涉及半导体器件的制造，尤其涉及高电压半导体器件，诸如大功率的MOS场效应管器件。
发明背景
高电压功率MOS场效应管器件用于诸如汽车点火系统、电源供给、电机驱动、镇定器及功率调节的应用。这样的器件应该在断电状态维持高电压，并且在通电状态具有大电流流量的低电压降落。
图1举例说明一个用于N型沟槽道功率MOS场效应管的典型结构。一个N外延硅层1在包含p主体区5和6的N+硅衬底2之上形成，并且在该器件中N+源极区域7和8用于二个MOS场效应管单元。P主体区5和6可以包括浅的区5a和6a以及深的p主体区5b和6b。源极主体电极12通过外延层1的某个表面部分伸出，以接触该源极区和主体区。在图1中，用于两个单元的N型漏极是通过N外延层1部分伸出半导体表面的上部而形成。一个漏极(没有单独示出)在N+衬底2的底部上提供。一个包括氧化物和多晶硅层栅极导体的绝缘栅电极18在该上部的半导体表面上覆盖信道和漏极部分。
在图1示出的常规的MOS场效应管的导导通电阻主要是通过在外延层1中的漂移区阻抗确定的。该漂移区的阻抗是通过掺杂掺杂和外延层1的层厚度确定的。但是，为了提高器件的击穿电压，当层厚度增加时，外延层1的掺杂密度必须降低。在图2中曲线20示出用于常规的MOSFET的导导通电阻乘以与击穿电压有关的器件面积(常常称为特定的导通电阻)与击穿电压的函数关系。令人遗憾地是，如特性曲线20所示，该器件的特定的导通电阻当其击穿电压增加之时快速地增加了。当该MOS场效应管将工作在高电压，尤其是在电压大于几百伏的时候，这个特定导通电阻的急剧增长将产生问题。
图3示出一个设计成能以降低的导通电阻工作在高电压的MOS场效应管。这个MOS场效应管在IEDM会议论文集，论文No.26.2，1998年，第683页上公开。这个MOS场效应管类似于在图2中示出的常规的MOS场效应管，除了其包括p型掺杂区40和42之外，其从主体区5和6的下面伸出进入器件的漂移区。如在常规的MOS场效应管中，该p型掺杂区40和42不仅使得在垂直方向上，而且也在水平方向方向上建立反向电压。结果，如在常规的器件中一样，这个器件可以随外延层1降低层厚度及随在漂移区中增长掺杂浓度获得相同的反向电压。在图2中，特性曲线25示出每一单位面积特定的导通电阻与在图3示出的MOS场效应管的击穿电压的函数关系。  显而易见，在高工作电压时，相对于在图1示出的器件，导通电阻基本上随击穿电压线性地增长，这个器件的导通电阻实质上降低了。
在图3示出的结构可以以包括多个外延沉积步骤的工艺程序制造，每个步骤继之以适当的掺杂物引入。令人遗憾地是，实施外延沉积步骤是昂贵的，并且因此制造这个结构是昂贵的。
因此，希望提供一种制造在图3示出结构的MOS场效应管的方法，其需要最小数量的沉积步骤使得其可以便宜地制造。
发明概述
按照本发明，提供了一种包括第一导电型衬底的高电压MOS场效应管。在该衬底上沉积一个也是第一导电型的外延层。第一和第二主体区主体区位于该外延层中，并且在它们之间划定一个漂移区。该主体区主体区具有第二导电型。第一导电型的第一和第二源极区域分别位于第一和第二主体区。多个沟槽位于在外延层的漂移区中的主体区的下面。充满包括第二导电型掺杂物材料的该沟槽从第一和第二主体区朝着衬底的方向扩展。该掺杂物被从沟槽扩散进相邻的沟槽的外延层部分，因此形成p型掺杂区，使得在水平方向和垂直方向建立反向电压。接着，在外延层中的击穿电压被测量，并且与在击穿电压和扩散时间之间的预先确定的关系相比，以确定需要获得规定的击穿电压剩余的扩散时间。对于该剩余的扩散时间实施一个附加的扩散步骤，使得该产生的器件具有规定的击穿电压。
按照本发明的一个方面，填充该沟槽的材料是多晶硅。
按照本发明的另一个方面，填充该沟槽的多晶硅至少被部分氧化。作为选择，该多晶硅随后可以再结晶以形成单晶硅。
按照本发明的另一个方面，填充该沟槽的该材料是诸如二氧化硅的电介质。
按照本发明的另一个方面，填充该沟槽的材料可以包括多晶硅和电介质两者。
按照本发明的另一个方面，该沟槽可以包括外延硅和电介质两者。
按照本发明的另一个方面，提供了一种用于形成高电压MOS场效应管的方法。该方法从提供一个第一导电型的衬底并且在该衬底上沉积一个外延层开始。该外延层具有第一导电型。在该外延层中形成第一和第二主体区，以在其间划定一个漂移区。该主体区具有第二导电型。第一导电型的第一和第二源区被分别形成在第一和第二主体区中。沟槽在外延层的漂移区中形成多个沟槽。该沟槽充满具有第二导电型的掺杂物的材料。该沟槽从第一和第二主体区朝着该衬底的方向扩展。至少一部分该掺杂物被从该沟槽扩散进入相邻的沟槽的外延层部分。接着，在外延层中的击穿电压被测量，并且与预先确定的在击穿电压和扩散时间之间的关系相比，以确定需要获得规定的击穿电压剩余的扩散时间。对于该剩余的扩散时间实施一个附加的扩散步骤，使得该产生的器件具有规定的击穿电压。
附图的简要说明
图1示出一个常规的高电压MOS场效应管结构的剖视图。
图2示出与用于常规的高电压MOS场效应管和按照本发明构成的MOS场效应管的击穿电压有关的每一单位面积的导通电阻。
图3示出一个在相同的电压下设计成能以比在图1描述的结构的每一单位面积低的导通电阻工作的MOS场效应管结构。
图4-6示出按照本发明构成的功率MOS场效应管的不同的实施例的有关的部分。
图7示出一个按照本发明构成的完整的高电压MOS场效应管。
图8示出一个可用于同时优化在图7示出的高电压MOS场效应管的击穿电压和导通电阻的测试结构。
图9是一个曲线图，示出在用于在图8示出的测试结构的扩散时间和击穿电压之间的示例的关系。
图10是一个曲线图，示出在用于图8的测试结构的扩散时间和导通电阻之间的示例的关系。
详细说明
按照本发明，在图3示出的p型区40和42是通过首先围绕p型区40和42放置的位置蚀刻一对沟槽形成的。该沟槽随后用充足的掺杂物材料填充。在该材料中的掺杂物是从该沟槽当中扩散的，并且进入相邻的形成器件的漂移区的外延层之内。外延层部分掺杂的结果形成该p型区。随同该掺杂物一起填充该沟槽的材料保持在该最终的器件中，该掺杂物没有从该沟槽当中扩散。因此，应该选择该材料，使得其不会不利地影响该器件的特性。那些示例的可以用于填充该沟槽的材料包括多晶硅或诸如二氧化硅的电介质。
图4-6示出可用于填充在外延硅层1中形成的沟槽44和46的若干不同的材料组合。虽然图4-6示出该沟槽44和46、外延层1及衬底2，为了清楚起见，图4-6没有示出功率MOS场效应管结构的上部，该上部包括P主体区和源区。
在图4中，该沟槽44和46充满了掺杂的介质，诸如掺杂硼的二氧化硅。在该沟槽被填充之后，硼被扩散进入相邻的外延层1之，以形成p型区40和42。填充该沟槽的掺杂硼的二氧化硅保持在最后的MOS场效应管器件中。
在图5中，该沟槽至少部分被用多晶体的硅，即多晶硅充满，其掺杂有硼。在该沟槽被填充之后，硼被扩散进入相邻的外延层1之内，去形成p型区40和42。填充该沟槽的剩余的掺杂硼的多晶硅保持在最后的MOS场效应管器件中。在实施该扩散步骤以形成二氧化硅之后，作为选择，该多晶硅可以全部或部分被氧化。因此，保留在最后的MOS场效应管器件中的该沟槽充满电介质，即二氧化硅以及一些剩余多晶硅。在另一个备选方案中，在该沟槽中的一些掺杂硼多晶硅被以一个高温再结晶去形成单晶硅。在这种情况下，保持在最后的MOS场效应管器件中的该沟槽充满单晶硅，或单晶硅与二氧化硅或别的电介质联合在一起。
在图6，该沟槽44和46首先被掺杂的多晶硅部分充满，继之以沉淀的电介质去彻底地填充该沟槽。在该沟槽被填充之后，硼被扩散进入相邻的外延层1之内，以形成p型区40和42。填充该沟槽的剩余的掺杂硼的多晶硅和电介质保持在最后的MOS场效应管器件中。有时候，该掺杂硼的多晶硅在一个高温下再结晶以形成单晶硅。因此，保持在最后的MOS场效应管器件中的该沟槽被单晶硅和电介质两者填充。
图7示出按照本发明构成的功率MOS场效应管。该MOS场效应管包括衬底2、外延层1、p主体区5和6、浅的p主体区5a和6a、深的p主体区5b和6b、源区7和8，以及p型区40和42，其中沟槽44和46分别位于p型区40和42中。还示出了栅电极和源体电极，该栅电极包括氧化层48和多晶硅层49，该源体电极包括金属敷层50。
在图7示出的发明的功率MOS场效应管可以按照任何常规的处理方法制造。例如，可以实施下面连续示例的步骤去形成在图7描述的功率MOS场效应管。
一个N掺杂的外延层1在传统的N+掺杂的衬底2上产生。对于带有15-60欧姆-厘米电阻率的400-800V器件，外延层1一般是15-50微米厚。接着，一个氧化物掩蔽层，诸如氧化物和氮化物的复合通过覆盖外延层1的表面氧化层而形成，然后进行通常的曝光和形成图案以抛弃掩模部分，划定该沟槽44和46的位置。该沟槽经由掩模开口通过活性离子蚀刻被干蚀刻到典型地从10到40微米的深度。硅层(典型地大约500-1000A)可以从该沟槽侧壁上去掉，以消除由该活性离子蚀刻处理所引起的损伤。首先，一个牺牲的二氧化硅膜在沟槽44和46的表面上生长。该牺牲的层和该掩模部分或者通过缓冲氧化腐蚀或者通过半蚀刻除去，使得该产生的沟槽侧壁尽可能平滑。
该沟槽44和46被任何先前提到的材料填充，诸如单晶硅、多晶硅、二氧化硅或其的组合。在沉淀期间，该单晶硅、多晶硅或氧化物典型地掺杂以诸如硼的掺杂物。随后实施扩散步骤以向该沟槽外扩散该掺杂物，并且进入围绕的外延层之内。如果保持在该沟槽中的材料是单晶硅或多晶硅，其可以被氧化或再结晶。
带有包含填充的沟槽的该衬底现在准备用于制造高电压MOS场效应管中常规的步骤。接着生长栅氧化层，并且沉积、掺杂和氧化一个多晶硅层。如果采用离子注入和扩散过程，使用常规的掩模形成深的p主体区5b和6b。对于该深的p主体区的掺杂将典型地大约从1×1014到5×1015/cm2变动。接着使用常规的注入和扩散步骤形成浅的p主体区5a和6a。该p主体区被以40至60KeV、大约1×1013至5×1014/cm2的剂量注入硼。
接着，使用光致抗蚀掩膜处理用来形成一个划定源区7和8的图案掩模层。然后通过注入和扩散过程形成源区7和8。例如，该源区可以以80KeV注入砷，以达到典型地在2×1015至1.2×1016/cm2范围内的密度。在注入之后，该砷将扩散到大约0.5至2.0微米的深度。虽然该主体区的范围大约从1到3微米深度，该深的p主体区的深度典型地大约从2.5到5微米变动。最后，该掩模层被以常规的方式除去以形成在图7描述的结构。
通过形成和构图该氧化层去提供接触开口以常规的方式完成该双扩散MOS晶体管。金属敷层50也被沉积和掩模以接触该源主体区和该栅极导体。接着可以沉积、掩模和蚀刻一个钝化层以划定焊点触点。最后，漏极接触层(未示出)在该衬底的底面上形成。
应当注意到，虽然在先前描述的处理中，该沟槽被在形成p主体和厚的p主体区之前形成，本发明一般地包含该沟槽被在任何或所有的剩余掺杂区之前或之后形成的过程。此外，虽然公开了用于制造该功率MOS场效应管特定的工艺程序，而限制在本发明的范围之内其他的工艺程序可以使用。
按照本发明构成的该功率MOS场效应管器件提供了多个与通过传统方法构成的现有技术器件相比的优点。例如，p型区的垂直掺杂物梯度非常接近于零。该水平掺杂物梯度可以通过改变传入的掺杂物的数值，及在扩散步骤中使用的热周期的数量和持续时间准确地控制。此外，传入的掺杂物的数值和横向掺杂物梯度可以改变，以优化器件的击穿电压和导通电阻。
在图7示出的本发明的实施例中，该p型沟槽在该主体区下面被形成。但是，不是每个p型沟槽需要具有一个与其有关的主体区，尤其是在该铸模的周边或在包含焊点或相互连接的区或。
本发明的MOS场效应管结构的击穿电压取决于在p型区40和42中的掺杂浓度。因此，该掺杂剂浓度控制得越准确，具有给定的击穿电压的器件越能准确地达到。该掺杂浓度将按照在与沟槽的表面接触的层中掺杂物的数值以及该扩散过程被允许进行的时间量来确定。
在图8示出一个用于同时优化该高电压MOS场效应管的导通电阻的测试结构。该测试结构包括接触区50和52，在其上暴露有p型区40和42。如在此处使用的，该术语“最佳化”指的是通过提供足够的余量该MOS场效应管的击穿电压大于指定的击穿电压，而该器件导通电阻的增加不会有这么多。
图9是一个曲线图，示出在用于本发明的测试结构的扩散时间和击穿电压之间的关系。这个关系将适用于具有给定结构和大体上通过相同的制造法制造的MOS场效应管。即，在扩散时间和击穿电压之间的关系将对于具有不同结构或组成成分，或具有大体上相同的结构和组成成分、但是通过不同的制造技术制造的MOS场效应管是不同的。
在图9中描述的在扩散时间和击穿电压之间的关系可以被在实验上测定。首先，一系列大体上相同的MOS场效应管结构被制造，其中该掺杂物被从沟槽扩散进相邻的外延层，在与该沟槽表面接触的层中发现对于掺杂物量的范围对应于不同的时间量。接着，该器件的表面层的一部分被移去以暴露相邻的p型区40和42，以形成接触区50和52(参见图8)。一个电极被放置以与p型区40和42的每个接触，并且施加电压允许掺杂物充分消耗，使得可以测量该击穿电压。以这种方法，可以沿着在图9中的曲线获得单一数据点。通过对于一系列MOS场效应管重复这个过程，可以产生完整的特性曲线。
一旦已经获得这个曲线图，通过允许的扩散步骤去着手制造比必需达到需要的击穿电压时间明显少的时间长度来制造后续的结构。当然，典型地，该期望的击穿电压就会是其最大值。然后将一个或多个这样的结构的击穿电压以如上所述的方式进行测量。该测量的击穿电压位于在图9的曲线图上，并且在该测量的击穿电压和该期望的击穿电压之间的不同的扩散时间被确定。然后该剩余的后续结构可以经受在等于差别的扩散时间的一段时间周期内的额外的扩散步骤。以这种方法，该完整的结构将具有非常接近于期望的最大值的击穿电压。
在高电压MOS场效应管的导通电阻和扩散时间之间的关系在图10中示出。如这个图示出的，该MOS场效应管应该再扩散足够长的时间以获得期望的击穿电压，但不能长到该器件的导通电阻开始显著地增加。
虽然在此处已经具体地举例说明和描述了各种各样的实施例，应该理解，无需脱离本发明的精神和想要的范围，通过以上所述教导覆盖的本发明的改进和变化是在所附权利要求的范围之内。例如，可以提供按照本发明的用于高电压MOS场效应管的测试结构，其中测试结构的不同的半导体区的导电性和该MOS场效应管是与在此处描述的那些相反的。

Claims (14)

1.一种形成高电压MOS场效应管的方法，包括步骤：
提供一个第一导电型衬底；
在该衬底上淀积一个外延层，所述外延层具有第一导电型；
在该外延层中形成第一和第二主体区以在其间划定一个漂移区，所述主体区具有第二导电型；
在第一和第二主体区中分别形成第一导电型的第一和第二源极区域；和
在该外延层的所述漂移区中形成多个沟槽；
以具有第二导电型的掺杂物材料填充所述沟槽，所述沟槽从第一和第二主体区朝着该衬底的方向扩展；
从所述沟槽至少扩散所述掺杂物的一部分进入与所述沟槽相邻的沟槽外延层部分；
测量在所述外延层中的击穿电压；
比较该测量的击穿电压与在击穿电压和扩散时间之间预先确定的关系，以确定剩余的扩散时间，去达到一个规定的击穿电压；和
对于所述剩余扩散时间实施一个附加的扩散步骤。
2.根据权利要求1的方法，其中所述填充该沟槽的材料是单晶硅或多晶硅。
3.根据权利要求1的方法，其中所述填充该沟槽的材料是电介质。
4.根据权利要求3的方法，其中所述电介质是二氧化硅。
5.根据权利要求1的方法，其中所述掺杂物是硼。
6.根据权利要求2的方法，进一步包括步骤，至少部分氧化所述单晶硅或多晶硅。
7.根据权利要求2的方法，进一步包括步骤，再结晶所述多晶硅以形成单晶硅。
8.根据权利要求1的方法，其中所述填充该沟槽的材料包括单晶硅和电介质，或多晶硅和电介质。
9.根据权利要求1的方法，其中所述主体区包括深的主体区。
10.根据权利要求1的方法，其中所述沟槽是通过提供一个划定至少一个沟槽的掩模层，并且通过蚀刻由该掩模层划定的该沟槽形成的。
11.根据权利要求1的方法，其中所述主体区是通过注入和扩散掺杂物进入该衬底形成的。
12.一种按照权利要求10的方法制造的高电压MOS场效应管。
13.根据权利要求6的方法，进一步包括步骤，再结晶所述多晶硅以形成单晶硅。
14.根据权利要求1的方法，其中所述规定的击穿电压是最大击穿电压。
CNB018106048A 2000-06-02 2001-06-01 一种制造功率mos场效应管的方法 Expired - Fee Related CN1230880C (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US09/586,407 2000-06-02
US09/586,407 US6593619B1 (en) 1999-06-03 2000-06-02 High voltage power MOSFET having low on-resistance
US09/766,229 2001-01-19
US09/766,229 US6479352B2 (en) 2000-06-02 2001-01-19 Method of fabricating high voltage power MOSFET having low on-resistance

Publications (2)

Publication Number Publication Date
CN1433569A true CN1433569A (zh) 2003-07-30
CN1230880C CN1230880C (zh) 2005-12-07

Family

ID=27079698

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB018106048A Expired - Fee Related CN1230880C (zh) 2000-06-02 2001-06-01 一种制造功率mos场效应管的方法

Country Status (9)

Country Link
US (1) US6479352B2 (zh)
EP (1) EP1287552B1 (zh)
JP (1) JP2003536261A (zh)
KR (1) KR100732051B1 (zh)
CN (1) CN1230880C (zh)
AU (1) AU2001275189A1 (zh)
DE (1) DE60132994T2 (zh)
TW (1) TW511296B (zh)
WO (1) WO2001095385A1 (zh)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100385679C (zh) * 2003-12-25 2008-04-30 恩益禧电子股份有限公司 半导体器件及其制造方法
CN100390937C (zh) * 2006-04-17 2008-05-28 南京国盛电子有限公司 5英寸功率mos管用硅外延片的制造方法
CN101040388B (zh) * 2004-10-14 2010-06-09 Nxp股份有限公司 用于高电压应用的mosfet及其制作方法
CN101459093B (zh) * 2007-12-10 2011-09-28 上海华虹Nec电子有限公司 验证非对称高压场效应管漂移区电阻的方法
CN102593157A (zh) * 2011-01-05 2012-07-18 茂达电子股份有限公司 具有低米勒电容的超级介面的功率晶体管及其制作方法
CN102738001A (zh) * 2011-03-30 2012-10-17 茂达电子股份有限公司 具有超级介面的功率晶体管的制作方法
CN102789990A (zh) * 2012-08-17 2012-11-21 西安龙腾新能源科技发展有限公司 一种浅槽源电极结构超结器件的制作工艺

Families Citing this family (58)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6461918B1 (en) * 1999-12-20 2002-10-08 Fairchild Semiconductor Corporation Power MOS device with improved gate charge performance
US6627949B2 (en) * 2000-06-02 2003-09-30 General Semiconductor, Inc. High voltage power MOSFET having low on-resistance
US6660571B2 (en) * 2000-06-02 2003-12-09 General Semiconductor, Inc. High voltage power MOSFET having low on-resistance
US6696726B1 (en) * 2000-08-16 2004-02-24 Fairchild Semiconductor Corporation Vertical MOSFET with ultra-low resistance and low gate charge
US7745289B2 (en) 2000-08-16 2010-06-29 Fairchild Semiconductor Corporation Method of forming a FET having ultra-low on-resistance and low gate charge
US7345342B2 (en) * 2001-01-30 2008-03-18 Fairchild Semiconductor Corporation Power semiconductor devices and methods of manufacture
US6916745B2 (en) 2003-05-20 2005-07-12 Fairchild Semiconductor Corporation Structure and method for forming a trench MOSFET having self-aligned features
US7132712B2 (en) * 2002-11-05 2006-11-07 Fairchild Semiconductor Corporation Trench structure having one or more diodes embedded therein adjacent a PN junction
US6713813B2 (en) 2001-01-30 2004-03-30 Fairchild Semiconductor Corporation Field effect transistor having a lateral depletion structure
US6803626B2 (en) 2002-07-18 2004-10-12 Fairchild Semiconductor Corporation Vertical charge control semiconductor device
US6818513B2 (en) * 2001-01-30 2004-11-16 Fairchild Semiconductor Corporation Method of forming a field effect transistor having a lateral depletion structure
US6710403B2 (en) * 2002-07-30 2004-03-23 Fairchild Semiconductor Corporation Dual trench power MOSFET
FI120310B (fi) * 2001-02-13 2009-09-15 Valtion Teknillinen Parannettu menetelmä erittyvien proteiinien tuottamiseksi sienissä
US7061066B2 (en) * 2001-10-17 2006-06-13 Fairchild Semiconductor Corporation Schottky diode using charge balance structure
US6750104B2 (en) * 2001-12-31 2004-06-15 General Semiconductor, Inc. High voltage power MOSFET having a voltage sustaining region that includes doped columns formed by trench etching using an etchant gas that is also a doping source
US6576516B1 (en) * 2001-12-31 2003-06-10 General Semiconductor, Inc. High voltage power MOSFET having a voltage sustaining region that includes doped columns formed by trench etching and diffusion from regions of oppositely doped polysilicon
KR100859701B1 (ko) * 2002-02-23 2008-09-23 페어차일드코리아반도체 주식회사 고전압 수평형 디모스 트랜지스터 및 그 제조 방법
US7576388B1 (en) 2002-10-03 2009-08-18 Fairchild Semiconductor Corporation Trench-gate LDMOS structures
US6710418B1 (en) 2002-10-11 2004-03-23 Fairchild Semiconductor Corporation Schottky rectifier with insulation-filled trenches and method of forming the same
US7638841B2 (en) 2003-05-20 2009-12-29 Fairchild Semiconductor Corporation Power semiconductor devices and methods of manufacture
KR100994719B1 (ko) 2003-11-28 2010-11-16 페어차일드코리아반도체 주식회사 슈퍼정션 반도체장치
US7368777B2 (en) 2003-12-30 2008-05-06 Fairchild Semiconductor Corporation Accumulation device with charge balance structure and method of forming the same
US20050199918A1 (en) * 2004-03-15 2005-09-15 Daniel Calafut Optimized trench power MOSFET with integrated schottky diode
KR100594277B1 (ko) * 2004-05-25 2006-06-30 삼성전자주식회사 포토 다이오드 및 그 제조방법
US7352036B2 (en) 2004-08-03 2008-04-01 Fairchild Semiconductor Corporation Semiconductor power device having a top-side drain using a sinker trench
US7265415B2 (en) * 2004-10-08 2007-09-04 Fairchild Semiconductor Corporation MOS-gated transistor with reduced miller capacitance
US7285823B2 (en) * 2005-02-15 2007-10-23 Semiconductor Components Industries, L.L.C. Superjunction semiconductor device structure
US7482220B2 (en) 2005-02-15 2009-01-27 Semiconductor Components Industries, L.L.C. Semiconductor device having deep trench charge compensation regions and method
US7176524B2 (en) * 2005-02-15 2007-02-13 Semiconductor Components Industries, Llc Semiconductor device having deep trench charge compensation regions and method
US7253477B2 (en) * 2005-02-15 2007-08-07 Semiconductor Components Industries, L.L.C. Semiconductor device edge termination structure
CN101882583A (zh) 2005-04-06 2010-11-10 飞兆半导体公司 沟栅场效应晶体管及其形成方法
US7276766B2 (en) * 2005-08-01 2007-10-02 Semiconductor Components Industries, L.L.C. Semiconductor structure with improved on resistance and breakdown voltage performance
US7381603B2 (en) * 2005-08-01 2008-06-03 Semiconductor Components Industries, L.L.C. Semiconductor structure with improved on resistance and breakdown voltage performance
US7385248B2 (en) * 2005-08-09 2008-06-10 Fairchild Semiconductor Corporation Shielded gate field effect transistor with improved inter-poly dielectric
US7446374B2 (en) 2006-03-24 2008-11-04 Fairchild Semiconductor Corporation High density trench FET with integrated Schottky diode and method of manufacture
US7679146B2 (en) * 2006-05-30 2010-03-16 Semiconductor Components Industries, Llc Semiconductor device having sub-surface trench charge compensation regions
US7411266B2 (en) * 2006-05-30 2008-08-12 Semiconductor Components Industries, L.L.C. Semiconductor device having trench charge compensation regions and method
US7319256B1 (en) 2006-06-19 2008-01-15 Fairchild Semiconductor Corporation Shielded gate trench FET with the shield and gate electrodes being connected together
US7799640B2 (en) * 2006-09-28 2010-09-21 Semiconductor Components Industries, Llc Method of forming a semiconductor device having trench charge compensation regions
WO2009039441A1 (en) 2007-09-21 2009-03-26 Fairchild Semiconductor Corporation Superjunction structures for power devices and methods of manufacture
US7772668B2 (en) 2007-12-26 2010-08-10 Fairchild Semiconductor Corporation Shielded gate trench FET with multiple channels
US9000550B2 (en) 2008-09-08 2015-04-07 Semiconductor Components Industries, Llc Semiconductor component and method of manufacture
US7902075B2 (en) * 2008-09-08 2011-03-08 Semiconductor Components Industries, L.L.C. Semiconductor trench structure having a sealing plug and method
US7960781B2 (en) * 2008-09-08 2011-06-14 Semiconductor Components Industries, Llc Semiconductor device having vertical charge-compensated structure and sub-surface connecting layer and method
US20120273916A1 (en) 2011-04-27 2012-11-01 Yedinak Joseph A Superjunction Structures for Power Devices and Methods of Manufacture
JP5532758B2 (ja) * 2009-08-31 2014-06-25 富士電機株式会社 半導体装置の製造方法および半導体装置
US8319290B2 (en) 2010-06-18 2012-11-27 Fairchild Semiconductor Corporation Trench MOS barrier schottky rectifier with a planar surface using CMP techniques
TW201246542A (en) * 2011-05-02 2012-11-16 Anpec Electronics Corp Power element having super interface
US8836028B2 (en) 2011-04-27 2014-09-16 Fairchild Semiconductor Corporation Superjunction structures for power devices and methods of manufacture
US8772868B2 (en) 2011-04-27 2014-07-08 Fairchild Semiconductor Corporation Superjunction structures for power devices and methods of manufacture
US8786010B2 (en) 2011-04-27 2014-07-22 Fairchild Semiconductor Corporation Superjunction structures for power devices and methods of manufacture
US8673700B2 (en) 2011-04-27 2014-03-18 Fairchild Semiconductor Corporation Superjunction structures for power devices and methods of manufacture
CN102760662B (zh) * 2011-04-29 2014-12-31 茂达电子股份有限公司 半导体功率装置的制作方法
TWI441261B (zh) * 2011-05-13 2014-06-11 Anpec Electronics Corp 半導體功率元件的製作方法
US10325908B2 (en) 2017-04-26 2019-06-18 Alpha And Omega Semiconductor Incorporated Compact source ballast trench MOSFET and method of manufacturing
US10211333B2 (en) * 2017-04-26 2019-02-19 Alpha And Omega Semiconductor (Cayman) Ltd. Scalable SGT structure with improved FOM
CN108091683B (zh) * 2017-12-11 2020-09-22 深圳迈辽技术转移中心有限公司 半导体功率器件的超结结构及其制作方法
US10714580B2 (en) 2018-02-07 2020-07-14 Alpha And Omega Semiconductor (Cayman) Ltd. Source ballasting for p-channel trench MOSFET

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5191396B1 (en) 1978-10-13 1995-12-26 Int Rectifier Corp High power mosfet with low on-resistance and high breakdown voltage
GB2089119A (en) 1980-12-10 1982-06-16 Philips Electronic Associated High voltage semiconductor devices
JPS63107133A (ja) * 1986-10-24 1988-05-12 Hitachi Ltd 半導体装置の製造方法
US5404040A (en) 1990-12-21 1995-04-04 Siliconix Incorporated Structure and fabrication of power MOSFETs, including termination structures
CN1019720B (zh) 1991-03-19 1992-12-30 电子科技大学 半导体功率器件
DE59409300D1 (de) * 1993-06-23 2000-05-31 Siemens Ag Verfahren zur Herstellung von einem Isolationsgraben in einem Substrat für Smart-Power-Technologien
JP3395473B2 (ja) * 1994-10-25 2003-04-14 富士電機株式会社 横型トレンチｍｉｓｆｅｔおよびその製造方法
JP2656740B2 (ja) * 1994-10-28 1997-09-24 山形日本電気株式会社 縦型電界効果トランジスタの製造方法
JPH08264772A (ja) * 1995-03-23 1996-10-11 Toyota Motor Corp 電界効果型半導体素子
DE19611045C1 (de) 1996-03-20 1997-05-22 Siemens Ag Durch Feldeffekt steuerbares Halbleiterbauelement
US5895951A (en) * 1996-04-05 1999-04-20 Megamos Corporation MOSFET structure and fabrication process implemented by forming deep and narrow doping regions through doping trenches
US5869875A (en) * 1997-06-10 1999-02-09 Spectrian Lateral diffused MOS transistor with trench source contact
DE19748523C2 (de) 1997-11-03 1999-10-07 Siemens Ag Halbleiterbauelement, Verfahren zum Herstellen eines derartigen Halbleiterbauelementes und Verwendung des Verfahrens
EP1029358A1 (de) 1997-11-03 2000-08-23 Infineon Technologies AG Hochspannungsfeste randstruktur für halbleiterbauelemente
JP4061711B2 (ja) * 1998-06-18 2008-03-19 株式会社デンソー Ｍｏｓトランジスタ及びその製造方法
EP0973203A3 (de) 1998-07-17 2001-02-14 Infineon Technologies AG Halbleiterschicht mit lateral veränderlicher Dotierung und Verfahren zu dessen Herstellung

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100385679C (zh) * 2003-12-25 2008-04-30 恩益禧电子股份有限公司 半导体器件及其制造方法
CN101040388B (zh) * 2004-10-14 2010-06-09 Nxp股份有限公司 用于高电压应用的mosfet及其制作方法
CN100390937C (zh) * 2006-04-17 2008-05-28 南京国盛电子有限公司 5英寸功率mos管用硅外延片的制造方法
CN101459093B (zh) * 2007-12-10 2011-09-28 上海华虹Nec电子有限公司 验证非对称高压场效应管漂移区电阻的方法
CN102593157A (zh) * 2011-01-05 2012-07-18 茂达电子股份有限公司 具有低米勒电容的超级介面的功率晶体管及其制作方法
CN102738001A (zh) * 2011-03-30 2012-10-17 茂达电子股份有限公司 具有超级介面的功率晶体管的制作方法
CN102789990A (zh) * 2012-08-17 2012-11-21 西安龙腾新能源科技发展有限公司 一种浅槽源电极结构超结器件的制作工艺
CN102789990B (zh) * 2012-08-17 2015-10-28 西安龙腾新能源科技发展有限公司 一种浅槽源电极结构超结器件的制作工艺

Also Published As

Publication number Publication date
EP1287552B1 (en) 2008-02-27
US6479352B2 (en) 2002-11-12
AU2001275189A1 (en) 2001-12-17
KR20030007834A (ko) 2003-01-23
JP2003536261A (ja) 2003-12-02
WO2001095385A1 (en) 2001-12-13
US20020009832A1 (en) 2002-01-24
TW511296B (en) 2002-11-21
CN1230880C (zh) 2005-12-07
DE60132994T2 (de) 2009-02-19
EP1287552A1 (en) 2003-03-05
DE60132994D1 (de) 2008-04-10
KR100732051B1 (ko) 2007-06-27

Similar Documents

Publication Publication Date Title
CN1230880C (zh) 一种制造功率mos场效应管的方法
CN1171318C (zh) 具有低导通电阻的高压功率金属氧化物半导体场效应晶体管
CN1280919C (zh) 功率mos场效应管及其制造方法
CN100342505C (zh) 高压半导体器件及其制造方法
CN1109358C (zh) 制造双扩散mos晶体管的方法
CN1610974A (zh) 具有电压维持区域并从相反掺杂的多晶硅区域扩散的高电压功率mosfet
US20030213993A1 (en) Trench mosfet with field relief feature
CN1152419C (zh) 功率半导体器件及其制造方法
CN101567384B (zh) 具有低导通电阻的高电压功率mosfet
CN1274028C (zh) 具有减小导通电阻的双扩散场效应晶体管
KR100292718B1 (ko) 반도체 장치 및 그 제조방법
CN111162009B (zh) 一种低导通电阻低压分离栅mos器件的制造方法
CN111354642B (zh) 一种低导通电阻低压槽栅mos器件的制造方法
CN1941414B (zh) 功率mos场效应管及其制造方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20051207

Termination date: 20160601

CF01 Termination of patent right due to non-payment of annual fee