CN1430276A - Ic芯片破损少的薄型高频模块 - Google Patents

Ic芯片破损少的薄型高频模块 Download PDF

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CN1430276A
CN1430276A CN02157873A CN02157873A CN1430276A CN 1430276 A CN1430276 A CN 1430276A CN 02157873 A CN02157873 A CN 02157873A CN 02157873 A CN02157873 A CN 02157873A CN 1430276 A CN1430276 A CN 1430276A
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insulating body
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frequency model
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CN1264215C (zh
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松田重俊
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Alps Alpine Co Ltd
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Abstract

本发明提供性能良好、IC芯片破损少的薄型高频模块。其中具有:由多块陶瓷薄片(2)积层而形成的绝缘基体(1)、以及在该绝缘基体(1)上面形成的绝缘层(7),在上述绝缘层7的上面上形成薄膜电路(10),该薄膜电路(10)包括用薄膜形成的布线图形(8)、以及与该布线图形(8)相连接,用薄膜形成的至少由电阻或/和电容器构成的电子元件(9),所以,能制成与过去相比精度更高的电子元件,能提供性能更好的高频模块。

Description

IC芯片破损少的薄型高频模块
技术领域
本发明涉及适用于移动电话手机的收发单元和电压控制振荡器等的高频模块。
背景技术
过去的高频模块,在积层而形成的绝缘基体的表面或层间利用厚膜来形成布线图形,同时在绝缘基体的表面或层间利用厚膜来形成电阻或电容的电子元件。
并且,在绝缘基体的表面上所形成的布线图形上安装由半导体构成的IC芯片,安装的状态是IC芯片从绝缘基体的表面上露出、突出。
过去的高频模块存在的问题是:因为用厚膜来形成电子元件,所以,其一致性差,性能不佳。
并且,因为IC芯片安装在绝缘基体的表面上,所以使厚度增大,不易实现薄型化,同时处于露出状态的IC芯片容易受到外力而造成破损。
发明内容
因此,本发明的目的是提供性能良好,IC芯片破损少的薄型高频模块。
对于上述问题,其第1解决方法是:高频模块具有:由多块陶瓷薄片积层而形成的绝缘基体、以及在该绝缘基体上面形成的绝缘层,在上述绝缘层的上面上形成薄膜电路,该薄膜电路包括用薄膜形成的布线图形、以及与该布线图形相连接,用薄膜形成的至少由电阻或/和电容器构成的电子元件,上述绝缘基体至少具有:形成在层间的导电体、形成在厚度方向上的第2、第2连接导体、以及在与上述导电体相连接的状态下形成在侧面上的电极部,上述第1连接导体与上述布线图形相连接,同时,上述第2连接导体与收容在上述绝缘基体内的IC芯片和上述布线图形相连接。
并且,第2解决方法是:上述绝缘基体由能在低温下烧结的上述陶瓷薄片形成,同时,上述绝缘层由玻璃或聚酰亚胺形成。
再者,第3解决方法是:上述连接导体的上端具有从上述绝缘基体的上面突出来的突出部,该突出部与上述绝缘层的表面为同一个平面,或者从上述绝缘层的表面上突出来,使上述布线图形与该突出部导通。
并且,第4解决方法是:在收容上述IC芯片的上述绝缘基体的凹部内充填同绝缘材料构成的密封材料。
并且,第5解决方法是:上述IC芯片由裸芯片形成。
附图说明
图1是本发明的高频模块的斜视图。
图2是本发明的高频模块的主要部分的断面图。
具体实施方式
对本发明的高频模块的附图加以说明,图1是本发明的高频模块的斜视图,图2是本发明的高频模块的主要部分的断面图。
以下根据图1、图2,详细说明本发明的高频模块的构成。平板状的绝缘基体1是由许多块陶瓷薄片2积层而形成,其下面设置多个凹部1a,同时在绝缘基体1的厚度方向上设置多个孔1b。
并且,在绝缘基体1的层间和凹部1a的底面上,设置由银等导电材料构成的导电体3,这些导电体3形成在与孔1b相对应的位置上。
由银等导电材料构成的第1、第连接导体4、5是充填在绝缘基体1的孔1b内而形成的,第1连接导体4与形成在层间的导电体3相连接,同时,第2连接导体5与设置在凹部1a底面上的导电体3相连接。
并且,该第1、第2连接导体4、5的上端具有在绝缘基体1的上面稍稍突出的突出部4a、5a。
再者,在绝缘基体1的侧面上设置出银等导电材料构成的多个电极部6,该电极部6在与形成在层间的导电体3相连接的状态下形成在绝缘基体1的厚度方向上,同时,横跨在绝缘基体1的下面上而形成。
具有这种结构的绝缘基体1的制造方法是:把能在低温(1000℃以下)烧结的瓷坯片(未烧结状态)的多块陶瓷薄片2重叠起来形成积层,同时在孔1b中充填由银浆构成的第1、第2连接导体4、5,使由银浆制成的导电体3导通,而且,在使导电体3导通的状态下在侧面上形成由银浆(paste)构成的电极部6。
然后,对其进行烧结,于是陶瓷薄片2经烧结后形成由块体构成的绝缘基体1,同时,银浆经烧结后形成导电体3和第1、第2连接导体4、5以及电极部6。
这时,第1、第2连接导体4、5的上端的突出部4a、5a形成从绝缘层基体1上面突出来的状态。
绝缘层7由玻璃、聚酰亚胺、SiO2、BCB(苯并环丁烯)、无定形(アモルフアス)氟树脂、氮化硅、环氧树脂等构成,该绝缘层7形成在绝缘基体1的上面,但第1、第2连接导体4、5的突出部4a、5a的前端除外。
并且,在形成绝缘层7时,突出部4a、5a的前端部与绝缘层7的表面在同一个面上,或者从绝缘层7的表面上稍稍突出一点。
在该绝缘层7的表面上设置用蒸发淀积等方法形成薄膜的布线图形8,同时,在与该布线图形8相连接的状态下,在绝缘层7的表面上利用薄膜来形成电子元件9,其中包括电阻9a、电容器9b和电感器9c,在绝缘层7的表面上,形成薄膜电路10。
并且,在绝缘层7的表面上形成布线图形8时,布线图形8形成与第1、第2连接导体4、5的突出部4a、5a相导通的状态,布线图形8通过第1连接导体4导电体3从电连接来看被引出到位于侧面上的电极部6上。
由半导体裸芯片构成的IC芯片11被装入到绝缘基体1的凹部1a内,IC芯片11的线11a和引出电极11b分别与导电体3相连接。
其结果,IC芯片11通过导电体3和第2连接导体5而与布线图形8相连接。
由绝缘材料构成的封装材料12被充填到绝缘基体1的凹部1a内,对IC芯片进行封装,这样,IC芯片11就被保护起来,防止外气、外力的影响,同时,封装材料12的下面与绝缘基体1的下面相一致,便于稳定地安装在绝缘基体1上。
具有这种结构的高频模块,安装在电子设备的电路板上,设置在绝缘基体1的侧面上的电极部6被焊接在电路板上的导电图形上,这样就完成了高频模块的安装和布线。
发明的效果
本发明的高频模块具有:由多块陶瓷薄片积层而形成的绝缘基体、以及在该绝缘基体上面形成的绝缘层,在上述绝缘层的上面上形成薄膜电路,该薄膜电路包括用薄膜形成的布线图形、以及与该布线图形相连接,用薄膜形成的至少由电阻或/和电容器构成的电子元件。与过去相比,能提供电子元件精度更高、性能更好的高频模块。
并且,在绝缘基体内安装IC芯片,所以能提供与过去相比厚度更薄,同时IC芯片破损更少的高频模块。
并且,由于绝缘基体由能在低温下烧结的陶瓷薄片形成,所以能用银来形成导电体、连接导体和电极部,能制成电损耗小,在电路板上焊接牢靠高频模块。
并且,由于绝缘层是由玻璃或聚酰亚胺形成的,所以,其表面光滑,能用薄膜方法形成高精度的布线图形和电子元件。
并且,由于连接导体的上端具有从绝缘基体上面突出来的突出部,该突出部与绝缘层的表面在同一平面上或者从绝缘层表面上突出来,使布线图形与突出部导通,所以,连接导体和布线图形容易导通,生产效率高。
并且,在安装IC芯片的绝缘基体的凹部内充填由绝缘材料构成的封装材料,所以,能可靠地保护IC芯片,制成IC芯片破损少的高频模块。
并且,由于IC芯片是裸芯片形成的,所以IC芯片价格低。

Claims (5)

1、一种高频模块,其特征在于具有:由多块陶瓷薄片积层而形成的绝缘基体、以及在该绝缘基体上面形成的绝缘层,在上述绝缘层的上面上形成薄膜电路,该薄膜电路包括:用薄膜形成的布线图形;以及与该布线图形相连接、用薄膜形成的至少由电阻或/和电容器构成的电子元件,上述绝缘基体至少具有:形成在层间的导电体、形成在厚度方向上的第1、第2连接导体、以及在与上述导电体相连接的状态下形成在侧面上的电极部,上述第1连接导体与上述布线图形相连接,并且上述第2连接导体与收容在上述绝缘基体内的IC芯片和上述布线图形相连接。
2、如权利要求1所述的高频模块,其特征在于:上述绝缘基体由能在低温下烧结的上述陶瓷薄片形成,同时,上述绝缘层由玻璃或聚酰亚胺形成。
3、如权利要求1所述的高频模块,其特征在于:上述连接导体的上端具有从上述绝缘基体的上面突出来的突出部,该突出部与上述绝缘层的表面为同一个平面,或者从上述绝缘层的表面上突出来,使上述布线图形与该突出部导通。
4、如权利要求1所述的高频模块,其特征在于:在收容上述IC芯片的上述绝缘基体的凹部内充填由绝缘材料构成的密封材料。
5、如权利要求1所述的高频模块,其特征在于:上述IC芯片由裸芯片形成。
CNB021578737A 2001-12-21 2002-12-23 Ic芯片破损少的薄型高频模块 Expired - Fee Related CN1264215C (zh)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100343965C (zh) * 2004-01-27 2007-10-17 卡西欧计算机株式会社 具有上下导电层的导通部的半导体装置及其制造方法

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7977785B2 (en) * 2009-03-05 2011-07-12 Freescale Semiconductor, Inc. Electronic device including dies, a dielectric layer, and a encapsulating layer
EP2698798B1 (en) * 2011-04-11 2018-04-25 Murata Manufacturing Co., Ltd. Laminated inductor element and method of manufacturing same
DE102020200421B4 (de) * 2020-01-15 2021-07-29 Albert-Ludwigs-Universität Freiburg Integrierte Schaltungsanordnung und Verfahren zum Herstellen einer integrierten Schaltungsanordnung

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3593174A (en) * 1969-06-05 1971-07-13 Westinghouse Electric Corp Solid state amplifier for microwave frequency signals
JPH04271161A (ja) 1991-02-27 1992-09-28 Mitsubishi Electric Corp 半導体装置
JPH05275609A (ja) 1992-03-26 1993-10-22 Hitachi Ltd 半導体モジュール基板
DE4404298A1 (de) 1994-02-11 1995-08-17 Sel Alcatel Ag Verfahren zur Herstellung eines Multilayers
JPH0818001A (ja) 1994-07-01 1996-01-19 Nippondenso Co Ltd Icパッケージ
JP3322575B2 (ja) * 1996-07-31 2002-09-09 太陽誘電株式会社 ハイブリッドモジュールとその製造方法
JPH1145977A (ja) 1997-07-28 1999-02-16 Hitachi Ltd マルチチップモジュールおよびその製造方法
JP2000058741A (ja) * 1998-08-12 2000-02-25 Taiyo Yuden Co Ltd ハイブリッドモジュール
JP2000252407A (ja) 1999-03-04 2000-09-14 Hitachi Ltd マルチチップモジュール
JP3407716B2 (ja) * 2000-06-08 2003-05-19 株式会社村田製作所 複合積層電子部品
US20020140081A1 (en) * 2000-12-07 2002-10-03 Young-Huang Chou Highly integrated multi-layer circuit module having ceramic substrates with embedded passive devices

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100343965C (zh) * 2004-01-27 2007-10-17 卡西欧计算机株式会社 具有上下导电层的导通部的半导体装置及其制造方法

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