CN1378269A - 双金属栅极互补金属氧化物半导体器件及其加工方法 - Google Patents
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Abstract
一种制造双金属栅极互补金属氧化物半导体(CMOS)的方法包括在栅极区形成栅极氧化物和在各个n阱和p阱沉积固定位置的栅极,去除固定位置的栅极和栅极氧化物,在栅极区沉积高k电介质,在p阱的栅极区沉积第一金属,在各个n阱和p阱的栅极区沉积第二金属,对通过上述步骤得到的结构进行绝缘和金属化,本发明的双金属栅极CMOS包括PMOS晶体管和NMOS晶体管。在NMOS中,栅极包括高k杯体,在高k杯体上形成的第一金属杯体,在第一金属杯体上形成的第二金属栅极。在PMOS中,栅极包括高k杯体和在高k杯体上形成的第二金属栅极。
Description
技术领域
本发明涉及一种MOS晶体管和IC的制造方法，特别地涉及双金属栅极CMOS器件及其制造方法。
背景技术
双金属栅极CMOS器件的提出是在1999年版的“InternationalTechnology Roadmap for Semiconductor”，然而该公开既没有告诉也没有建议任何加工工艺以制造这种器件，同时也没有指定制造双金属栅极CMOS器件的材料或参数。
目前CMOS器件使用多晶硅作为栅极电极用于NMOS和PMOS晶体管，其中N+多晶硅用于NMOS，而P+多晶硅用于PMOS。由于多晶硅存在栅极损耗问题，存在着用金属代替多晶硅以提供更可靠和有效的CMOS器件的期望。
目前有两种技术用于在IC器件上形成金属电极：一种是在硅带隙(band gap)的中间设置费米级的金属电极。第二个技术是使用双金属，一个金属的功能类似于NMOS晶体管的N+多晶硅，第二个不同的金属的功能类似于PMOS晶体管的P+多晶硅。
发明内容
一种制造双金属栅极互补金属氧化物半导体(CMOS)的方法包括制备形成器件区域的硅基片，其中各器件区域包括n阱和p阱；在栅极区形成栅极氧化物和在各个n阱和p阱沉积固定位置的栅极；在各个n阱和p阱掺杂离子形成源极区和漏极区；清除固定位置的栅极和栅极氧化物；在栅极区沉积高k电介质；在p阱的栅极区沉积第一金属；在所述各个n阱和p阱的栅极区沉积第二金属；对通过上述步骤得到的结构进行绝缘和金属化。
本发明的双金属栅极互补金属氧化物半导体(CMOS)包括具有形成PMOS晶体管的n阱和形成NMOS晶体管的p阱的基片，各晶体管包括栅极区、源极区和漏极区；在NMOS，栅极包括高k杯体、在高k杯体上形成的第一金属杯体和在第一金属杯体上形成的第二金属栅极；在PMOS，栅极包括高k杯体、在高k杯体上形成的第二金属栅极；其中第一金属是从由Pt和Ir组成的一组金属中选出的金属，第二金属是从由Al，Zr，Mo，Nb，Tl和TlN及V组成的一组金属中选出的金属。
本发明的目的是提供一种高效、可靠的双金属栅极CMOS器件。
本发明的另一目的是提供一种在栅极区不使用多晶硅的CMOS器件。
提出本发明的目的和概要使得可以快速理解本发明的性质。对本发明的更全面的了解可以参考下面的结合附图对本发明的优选
实施例的详细介绍。
附图说明
图1到7显示了根据本发明方法形成双金属栅极CMOS器件的步骤。
具体实施方式
本发明提供了集成双金属栅极CMOS器件的加工步骤和根据本发明方法制造的CMOS器件。现在转到图1，本发明的CMOS器件在p型硅晶片10上形成。晶片10被氧化物区11分割成隔离器件区，形成多个器件区域，其中一个通常显示为12。接下来采用目前的工艺技术形成用于PMOS晶体管的n-阱14，和用于NMOS晶体管的p-阱16。这些区域可以通过剂量大约为5×1013/cm2到5×1014/cm2，能级为50keV到200keV的条件下掺杂磷离子形成PMOS；可以通过剂量大约为5×1013/cm2到5×1014/cm2，能级为20keV到100keV的条件下掺杂硼离子形成NMOS。调整门槛电压。分别用于PMOS晶体管和NMOS晶体管的栅极氧化物层18，20通过热氧化形成。氮化硅(Si3N4)或多晶硅的厚度通过等离子增强化学气相沉积(PECVD)沉积到大约150到500nm之间，以形成所谓的“虚拟”栅极或位置固定栅极。位置固定栅极22，24分别在PMOS和NMOS上形成。这些都是通过在氮化物或多晶硅上进行照相平版印刷和各向异性等离子蚀刻形成的，蚀刻停止于栅极氧化物的水平。栅极氧化物可以部分蚀刻掉或在蚀刻过程中完全清除。氮化物层形成了栅极电极的替代物。
源极和漏极的接合点在PMOS和NMOS的上面。一种实现的技术是通过在剂量为大约为1×1015/cm2到5×1015/cm2，能级为30keV到50keV的条件下对n阱14掺杂BF2离子而形成PMOS的源极26和漏极28；在剂量为大约为1×1015/cm2到5×1015/cm2，能级为30keV到60keV的条件下对P阱16掺杂砷离子形成NMOS的源极30和漏极32。氧化物间隔通过在沉积硅化物后沉积氧化物和进行各向异性蚀刻来形成。
现在参见图2，氧化物层36是通过化学气相沉积进行沉积的。希望的厚度为图1所示氮化硅层的大约1.5倍到2倍。该结构是通过一磷酸胞苷(CMP)工艺掺杂的并停止于氮化硅的顶部。CMP工艺希望有高度选择性的浆状物。
现在看图3和4，优选去除固定位置的氮化物栅极22，24和栅极氧化物18，20。沉积高k栅极电介质38，如HfO2和ZrO2，至厚度大约为3到8nm之间，并经过传统的后沉积处理，包括在温度大约500到800℃的范围内进行大约10分钟到60分钟的退火，在各个n阱14和p阱16的栅极区形成杯状电介质。本发明方法的下一步可以用两个方法进行。
现在参考图3，第一种方法是使用光致抗蚀剂40在NMOS的栅极区域形成图案。然后用阴极真空喷镀进行沉积金属栅极电极的第一金属42。第一金属通常不是铂就是铱。金属形成了图案，然后进行蚀刻，只保留NMOS的栅极区的金属。然后将光致抗蚀剂清除。形成图5所示的结构，其包括在NMOS的高k杯体中形成的第一金属杯体。
现在参考图4，第二个方法是在整个晶片上沉积第一金属42，然后用光致抗蚀剂40在晶片和PMOS区形成图案。暴露的金属然后用蚀刻剂有选择地进行湿法蚀刻。蚀刻不会蚀刻掉高k栅极电介质。一种蚀刻剂是H2O2。所产生的结构与第一个方法的结构类似，其显示在图5。
本发明方法的下一步是沉积第二金属44，沉积的金属可以从由Al，Zr，Mo，Nb，Tl和TlN及V组成的一组金属中选出。该金属然后通过CMP使之平滑和减小，产生图6所示的结构，其中在NMOS的第一金属杯体和PMOS的高k杯体中形成金属电极。
现在参考图7，完成双金属栅极CMOS的其余工艺利用现有工艺技术进行清除剩余高k材料，沉积绝缘氧化物46，和金属化结构48，50，52和54。对栅极电极的金属化也同时完成，虽然该结构未在图7中显示。
因此对双金属栅极CMOS器件的系统以及其制造方法已经进行了介绍。应当了解进一步的变化和改进可以在不脱离所附权利要求限定的发明范围的情况下进行。
Claims (17)
1.一种制造双金属栅极互补金属氧化物半导体(CMOS)的方法，包括：
a)制备硅基片以形成器件区，其中各器件区包括n阱和p阱；
b)在栅极区形成栅极氧化物和在所述各个n阱和p阱沉积固定位置的栅极；
c)在所述各个n阱和p阱掺杂离子形成源极区和漏极区；
d)清除所述固定位置的栅极和所述栅极氧化物；
e)在所述栅极区沉积高k电介质；
f)在所述p阱的栅极区沉积第一金属；
g)在所述各个n阱和p阱的栅极区沉积第二金属；和
h)对通过上述步骤得到的结构进行绝缘和金属化。
2.根据权利要求1所述的方法，其特征在于，所述b)中沉积固定位置的栅极，包括将固定位置的材料厚度沉积到大约150至500nm之间。
3.根据权利要求2所述的方法，其特征在于，所述b)中沉积的固定位置的材料包括Si3N4。
4.根据权利要求2所述的方法，其特征在于，所述方法还包括在所述d)中的清除之前沉积氧化物层，其中所述氧化物层厚度为所述固定位置栅极厚度的大约1.5倍到2.0倍之间。
5.根据权利要求1所述的方法，其特征在于，所述e)中的沉积高k材料包括沉积从由HfO2和ZrO2组成的一组材料中选出的高k材料。
6.根据权利要求1所述的方法，其特征在于，所述e)中沉积高k材料包括将高k材料的厚度沉积到大约3到8nm之间。
7.根据权利要求1所述的方法，其特征在于，所述f)中沉积第一金属包括在所述p阱的所述栅极区制作图案和沉积所述第一金属，对所述第一金属制作图案，和有选择地蚀刻所述第一金属。
8.根据权利要求1所述的方法，其特征在于，所述f)中沉积第一金属包括在整个器件表面上沉积一层所述第一金属，在所述器件表面制作图案并在所述p阱的所述栅极区留下第一金属杯体。
9.根据权利要求1所述的方法，其特征在于，所述f)中沉积第一金属包括沉积从由Pt和Ir组成的一组金属中选出的金属。
10.根据权利要求1所述的方法，其特征在于，所述g)中沉积第二金属包括沉积从由Al，Zr，Mo，Nb，Tl和TlN及V组成的一组金属中选出的金属。
11.一种制造双金属栅极互补金属氧化物半导体(CMOS)的方法，包括：
a)制备硅基片以形成器件区域，其中各器件区域包括n阱和p阱；
b)在栅极区形成栅极氧化物和在所述各个n阱和p阱沉积固定位置的栅极；包括沉积Si3N4固定位置材料的厚度到大约150至500nm之间。
c)在所述各个n阱和p阱掺杂离子形成源极区和漏极区；
d)沉积氧化物层的厚度到大约225至1000nm之间；
e)清除所述固定位置的栅极和所述栅极物；
f)在所述栅极区沉积高k电介质；
g)在所述p阱的栅极区沉积从由Pt和Ir组成的一组金属中选出的第一金属；
h)在所述各个n阱和p阱的栅极区沉积从由Al，Zr，Mo，Nb，Tl和TlN及V组成的一组金属中选出的第二金属；和
i)对通过步骤a)到h)得到的结构进行绝缘和金属化。
12.根据权利要求11所述的方法，其特征在于，所述f)中的沉积高k材料包括沉积从由HfO2和ZrO2组成的一组材料中选出的高k材料。
13.根据权利要求11所述的方法，其特征在于，所述f)中沉积高k材料包括将高k材料的厚度沉积到大约3到8nm之间。
14.根据权利要求11所述的方法，其特征在于，所述g)中沉积第一金属包括在所述p阱的所述栅极区制作布线图案和沉积所述第一金属，对所述第一金属制作布线图案，和有选择地蚀刻所述第一金属。
15.根据权利要求11所述的方法，其特征在于，所述g)中沉积第一金属包括在整个器件区域上沉积一层所述第一金属，在所述器件区域制作布线图案并在所述p阱的所述栅极区留下第一金属杯体。
16.一种双金属栅极CMOS，包括：
一基片，具有可形成PMOS晶体管的n阱和可形成NMOS晶体管的p阱，各阱均具有栅极区，源极区和漏极区；
在NMOS中，栅极包括高k杯体，在所述高k杯体上形成的第一金属杯体，及在第一金属杯体上形成的第二金属栅极；
在PMOS中，栅极包括高k杯体和在所述高k杯体上形成的第二金属栅极；
其中，所述第一金属是从由Pt和Ir组成的一组金属中选出的金属；
其中，所述第二金属是从由Al，Zr，Mo，Nb，Tl和TlN及V组成的一组金属中选出的金属。
17.根据权利要求16所述的CMOS，其特征在于，所述高k材料是从由HfO2和ZrO2组成的一组材料中选出的高k材料。
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| US09/817834 | 2001-03-27 | ||
| US09/817,834 US6573134B2 (en) | 2001-03-27 | 2001-03-27 | Dual metal gate CMOS devices and method for making the same |
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Also Published As
| Publication number | Publication date |
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| KR20020075732A (ko) | 2002-10-05 |
| KR100529202B1 (ko) | 2005-11-17 |
| JP2002329794A (ja) | 2002-11-15 |
| US20020140036A1 (en) | 2002-10-03 |
| TW523914B (en) | 2003-03-11 |
| US20030205767A1 (en) | 2003-11-06 |
| US6573134B2 (en) | 2003-06-03 |
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