CN1339822A - 用三元素合金制作半导体器件的基板 - Google Patents

用三元素合金制作半导体器件的基板 Download PDF

Info

Publication number
CN1339822A
CN1339822A CN01124210A CN01124210A CN1339822A CN 1339822 A CN1339822 A CN 1339822A CN 01124210 A CN01124210 A CN 01124210A CN 01124210 A CN01124210 A CN 01124210A CN 1339822 A CN1339822 A CN 1339822A
Authority
CN
China
Prior art keywords
sample
alloy
layer
substrate
qualified
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN01124210A
Other languages
English (en)
Other versions
CN1245756C (zh
Inventor
洪淳盛
李志溶
朴炳俊
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Quan Heyuan
ACQUTEK SEMICONDUCTOR TECHNOLOGY Co Ltd
Original Assignee
Quan Heyuan
ACQUTEK SEMICONDUCTOR TECHNOLOGY Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Quan Heyuan, ACQUTEK SEMICONDUCTOR TECHNOLOGY Co Ltd filed Critical Quan Heyuan
Publication of CN1339822A publication Critical patent/CN1339822A/zh
Application granted granted Critical
Publication of CN1245756C publication Critical patent/CN1245756C/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/24—Reinforcing the conductive pattern
    • H05K3/244—Finish plating of conductors, especially of copper conductors, e.g. for pads or lands
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/142—Metallic substrates having insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
    • H01L23/49582—Metallic layers on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01028—Nickel [Ni]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/927—Electromigration resistant metallization

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Electroplating Methods And Accessories (AREA)
  • Other Surface Treatments For Metallic Materials (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)
  • Analysing Materials By The Use Of Radiation (AREA)

Abstract

一种基板,它包括银/金/微量元素的合金层,其中所述合金形成制品的外层。所述微量元素选自一组硒、锑、铋、镍、钴、铟及其混合物。本发明特别用于形成各种元件的外层,包括引线框架、球栅阵列、座、印刷电路板、簧片开关和连接器。

Description

用三元素合金制作半导体器件的基板
技术领域
本发明涉及包含三元素合金的基板，具体地说，涉及一种基板，其中把包含Au/Ag/微量元素的三元素合金加到镍层上，所述镍层被加在铜或铜合金，或者镍或镍合金上，以给出所需的改善结合能力、耐腐蚀性、对模型树脂的粘附力，以及成本效率特性。
背景技术
一般地说，半导体器件的基板使电子器件之间电连接，所述器件包括比如半导体芯片和印刷电路板(“PCB”)等器件。此外，良好的基板材料特性包括对连接导线的结合能力、耐腐蚀的性能、对模型树脂(通常起覆盖作用)的粘附力、和耐用性。
为实现这些特性，普通半导体器的基板都采用在还包括铜层和镍层之多层电镀结构的最外层是Sn-Pb。不过，铅普遍被认为是对健康有害的物质。铅对人体是有毒性的，它有很长的有关人和环境的不利影响的记录史。
按照惯例，作为最外层，可以代替Sn-Pb层的是钯层或金层。但钯层或金层在与导线的结合能力、对模型树脂的粘附力以及对PCB的附着特性等方面表现出很多问题。相应地，使用钯的成本和使用金的成本历来是相当高的。
发明内容
本发明的目的是提供一种无铅基板，同时，由此还顺便对环境提供所需要的改善结合能力、耐腐蚀性、对模型树脂的粘附力和成本效率等特性。
为实现这个目的，本发明采用包含金、银和选自硒、锑、铋、镍、INO1645钴和铟的微量元素的三元素合金。
附图说明
以下的描述将参照附图说明本发明的上述各方面和其它特征，其中：
图1是本发明应用三元素合金层的基板的示意图。
具体实施方式
本发明的基板包括：
制有图样的铜层；
厚度为10-300微吋镍层，它被沉积所述制有图样的铜层上；
包含金/银/微量元素、厚度为3-160微吋的三元素合金，它沉积在所述镍层上。
所述三元素合金层包含重量百分比50-95％的银、重量百分比4-49％金，以及重量百分比1％或更少的一种微量元素。所述微量元素选自一组硒、锑、铋、镍、钴和铟，最好为硒。加入微量元素有助于改善微粒的外形并减少沉积金属的多孔性。
对于本发明而言，镍层防止铜的扩散，并改善将半导体芯片的封装安装于印刷电路板上的焊料浸润性。镍层的厚度最好在10-300微吋范围。靠上面的三元素合金层防止下层金属因受热而扩散，避免上层氧化，并在导线与硅芯片结合的过程中，提高与金导线的结合能力。三元素合金层的厚度最好在3-160微吋范围。
本发明的基板具有无需电镀Pb/Sn合金即可安装用电器件或电子器件的特性。此外，正如以前所报道的那样，银存在的问题在于，由于吸湿性的缘故而使对模型树脂的粘附力下降；而由于本发明，则避免了这种问题。
可将本发明用于制作引线框架、球栅阵列、座、印刷电路板、簧片开关、连接器和各种电子元件。例
有如下面所详述的那样使本发明得到测试。采用金/银/硒合金进行所述测试，这是最佳的合金。准备样品
用酸除去铜或铜合金线圈的表面的油脂，并使之活化。依次将Ni和Au/Ag/硒合金电镀到整个铜或铜合金基材的表面上。结合能力的测试评估
在用导线焊接机实现导线的焊接之后，利用连接牵引测试计测量拉伸强度。焊料浸润性的测试评估
在175℃条件下经7.5小时的热处理后，使样品在95℃、相对湿度95％的条件下强制老化8小时。然后参照MIL-STD-883D进行对焊料浸润性的评估。对模型树脂粘附力的测试评估
在170℃模铸温度下以模型树脂密封样品90秒钟之后，再在175℃条件下加热处理6小时，参照MRT(防湿测试)利用SAT(扫描声学层析X射线摄影机)评估半导体器件与模型树脂之间的粘附力。例1和比较例1关于结合能力的评估测试
表1和2中示出每次评估测试的结果。该二表中，将每个样品的制备条件标记为“·”。表1表示对按照本发明电镀的层评估测试的结果，而表2表示对其上只沉积Au或Ag或Au/Ag合金的层评估测试的结果，用以比较。表2中的样品12-18只对Ag，样品19-24只对Au，而样品25-30对Au/Ag合金。表1
叠层结构          Ni        Au/Ag/Se  EDS分析(wt％) 导线焊接时的拉伸强度(g)
厚度(μin) 30  50  70  5  10  15
  样品1  ·  ·   Au11，Ag89     15.30
  样品2  ·  ·   Au16，Ag84     15.60
  样品3  ·  ·   Au22，Ag78     15.40
  样品4  ·  ·   Au27，Ag73     15.40
  样品5  ·  ·   Au30，Ag70     15.36
  样品6  ·  ·   Au35，Ag65     16.21
  样品7  ·  ·   Au30，Ag70     15.21
  样品8  ·  ·   Au33，Ag67     16.21
  样品9  ·  ·   Au32，Ag68     16.71
  样品10  ·  ·   Au34，Ag66     16.15
  样品11  ·  ·   Au31，Ag69     14.87
  样品12  ·   ·   Au31，Ag69     15.88
表2
叠层结构           Ni      Ag，Au或Au/Ag   EDS分析(wt％)   导线焊接时的拉伸强度(g)
  厚度(μin)   30   50   70   5   10   15
  样品13   ·  ·     Ag100       -
  样品14   ·   ·     Ag100       -
  样品15   ·    ·     Ag100       -
  样品16   ·   ·     Ag100       -
  样品17   ·   ·     Ag100       -
  样品18   ·   ·     Ag100       -
  样品19   ·  ·     Au100     11.25
  样品20   ·   ·     Au100     12.31
  样品21   ·   ·     Au100     12.33
  样品22   ·   ·     Au100     11.26
  样品23   ·     Au100     10.55
  样品24   ·   ·     Au100     10.99
  样品25   ·  ·   Au11，Ag89     9.66
  样品26   ·   ·   Au16，Ag84     9.55
  样品27   ·   ·   Au22，Ag78     10.25
  样品28   ·   ·   Au27，Ag73     10.22
  样品29   ·   ·   Au30，Ag70     11.23
  样品30    ·   ·   Au35，Ag65     10.56
从表1和2的结果清楚，具有Au/Ag/Se合金层的样品比只具有Au或Ag或Au/Ag合金的层表现出更高的导线焊接拉伸强度值。再有，作为只存在Ag的最外层，不能将金导线焊接在Ag层的表面上。虽然金导线能焊接在Au/Ag合金的表面上，但本发明的Au/Ag/Se合金层比Au/Ag合金表现出非常高的导线焊接拉伸强度值。表1中，由于只含少量的Se，所以不能通过能量分布能谱(EDS)分析测定Se的含量。例2和比较例2焊料浸润性的评估
对样品做关于焊料浸润性的评估。样品的条件与例1和比较例1相同。对本发明样品的评估结果示于表3中，而对其它样品的结果示于表4中。像表1中那样，不能通过EDS分析测定Se的含量。表3
叠层结构          Ni         Au/Ag/Se  EDS分析(wt％) 覆盖率(％)
厚度(μin) 30  50  70  5  10  15
  样品1  ·  ·   Au11，Ag89   99-100
  样品2  ·  ·  ·   Au16，Ag84   99-100
  样品3  ·  ·   Au22，Ag78   99-100
  样品4  ·  ·   Au27，Ag73   99-100
  样品5  ·  ·   Au30，Ag70   99-100
  样品6  ·  ·   Au35，Ag65   99-100
  样品7  ·  ·   Au30，Ag70   99-100
  样品8  ·  ·   Au33，Ag67   99-100
  样品9  ·  ·   Au32，Ag68   99-100
  样品10  ·  ·   Au34，Ag66   99-100
  样品11  ·  ·   Au31，Ag69   99-100
  样品12  ·  ·   Au31，Ag69   99-100
表4
叠层结构          Ni     Ag，Au或Au/Ag   EDS分析(wt％)   覆盖率(％)
厚度(μin) 30  50  70  5  10  15
  样品13  ·  ·   Cu3，Ni5，Ag92     58
  样品14  ·  ·   Cu2，Ni4，Ag94     65
  样品15  ·   ·   Cu1，Ni4，Ag95     70
  样品16  ·  ·   Cu4，Ni3，Ag93     55
  样品17  ·  ·   Cu2，Ni4，Ag94     65
  样品18  ·  ·   Cu1，Ni4，Ag95     75
  样品19  ·  ·   Cu2，Ni5，Ag93     72
  样品20  ·  ·   Cu1，Ni4，Ag95     80
  样品21  ·   ·   Cu1，Ni3，Ag96     89
  样品22  ·  ·   Cu4，Ni3，Ag93     77
  样品23  ·  ·   Cu1，Ni1，Ag98     80
  样品24  ·  ·   Cu1，Ni1，Ag98     90
  样品25  ·  ·   Ni5，Au11，Ag84     94
  样品26  ·  ·   Ni4，Au16，Ag80     95
  样品27  ·   ·   Ni2，Au22，Ag76     95
  样品28  ·  ·   Ni3，Au27，Ag70     94
  样品29  ·  ·   Ni4，Au30，Ag66     96
  样品30  ·  ·   Ni4，Au35，Ag61     94
按照表4的结果，通过EDS分析只在Au或Ag的表面上，或者只在样品13到24中的Au/Ag合金测定Ni和Cu。另外，在关于焊料浸润性的评估中，焊料的含量(％)受到限制，达不到超过95％。于是，Ni或Cu的扩散使基板在焊料的浸润性方面变差。另一方面，按照表3的结果，具有不受所有通过的Ni或Cu扩散污染的Au/Ag/Se合金最外层的样品，在关于焊料浸润性的评估中全部合格，表现出超过99％的覆盖率。例3和比较例3对模型树脂粘附力的评估
对样品评估关于其对模型树脂的粘附力。样品的条件与例1和比较例1相同。对本发明样品的评估结果示于表5中，而对其它样品的结果示于表6中。在比较例3中，不用Au/Ag合金层。表5
叠层结构          Ni        Au/Ag/Se  EDS分析(wt％) 对模型树脂的粘附力
厚度(μin) 30  50   70   5   10   15
  样品1  ·  ·   Au11，Ag89     合格
  样品2  ·   ·   Au16，Ag84     合格
  样品3  ·   ·   Au22，Ag78     合格
  样品4  ·  ·   Au27，Ag73     合格
  样品5  ·   ·   Au30，Ag70     合格
  样品6  ·   ·   Au35，Ag65     合格
  样品7  ·   ·   Au30，Ag70     合格
  样品8  ·   ·   Au33，Ag67     合格
  样品9  ·  ·   Au32，Ag68     合格
  样品10   ·   ·   Au34，Ag66     合格
  样品11   ·  ·   Au31，Ag69     合格
  样品12   ·   ·   Au31，Ag69     合格
表6
叠层结构          Ni        Ag或Au  EDS分析(wt％) 对模型树脂的粘附力
厚度(μin) 30  50  70  5  10  15
  样品13  ·  ·     Ag100     不合格
  样品14  ·  ·     Ag100     不合格
  样品15  ·  ·     Ag100     不合格
  样品16  ·  ·     Ag100     不合格
  样品17  ·  ·     Ag100     不合格
  样品18  ·  ·     Ag100     不合格
  样品19  ·  ·     Au100     合格
  样品20  ·  ·     Au100     合格
  样品21  ·  ·     Au100     合格
  样品22  ·  ·     Au100     合格
  样品23  ·  ·     Au100     合格
  样品24  ·  ·     Au100     合格
按照表5和6的结果，沉积在Ni镀层上的Au或Au/Ag/Se合金作为最外层，比起只有Ag沉积在Ni镀层上作为最外层的样品来，达到更好的对模型树脂的粘附力。如果在基板与模型树脂之间没有被检测的SAT系统，或者有空隙，则这样的样品被认为是不合格的。
可以理解，此前已经详细描述了所设定的各种特定的实施例，但这种描述只是为了说明的目的而给出的，而且将能理解，可以作出多种改变和改型，而不致脱离后附各权利要求的精髓或范围。

Claims (4)

1.一种半导体器件的基板，它包括：
制有图样的铜层；
厚度为10-300微吋镍层，它被沉积所述制有图样的铜层上；
包含金/银/微量元素、厚度为3-160微吋的三元素合金，它沉积在所述镍层上。
2.如权利要求1所述的基板，其特征在于，所述微量元素选自Se、At、Bi、Ni、Co和In。
3.如权利要求1或2所述的基板，其特征在于，所述三元素合金包含重量百分比50-96％的Ag，重量百分比4-49％的Au和小于重量百分比1％的微量元素。
4.如权利要求1至3任一项所述的基板，其特征在于，用于制作电子元件、印刷电路板、球栅阵列和引线框架。
CNB011242108A 2000-08-23 2001-08-15 用三元素合金制作半导体器件的衬底 Expired - Fee Related CN1245756C (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
KR10-2000-0048799A KR100379128B1 (ko) 2000-08-23 2000-08-23 삼원합금을 이용한 환경친화적 반도체 장치 제조용 기질
KR2000-0048799 2000-08-23
KR20000048799 2000-08-23

Publications (2)

Publication Number Publication Date
CN1339822A true CN1339822A (zh) 2002-03-13
CN1245756C CN1245756C (zh) 2006-03-15

Family

ID=19684599

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB011242108A Expired - Fee Related CN1245756C (zh) 2000-08-23 2001-08-15 用三元素合金制作半导体器件的衬底

Country Status (8)

Country Link
US (1) US6424046B1 (zh)
EP (1) EP1184904A3 (zh)
JP (1) JP2002173796A (zh)
KR (1) KR100379128B1 (zh)
CN (1) CN1245756C (zh)
AU (1) AU2001278818A1 (zh)
TW (1) TW529126B (zh)
WO (1) WO2002017396A1 (zh)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100359657C (zh) * 2002-03-26 2008-01-02 株式会社野毛电气工业 键合线和使用该键合线的集成电路装置
CN100468845C (zh) * 2005-08-12 2009-03-11 鸿富锦精密工业（深圳）有限公司 集电板及其制作方法
US7638873B2 (en) 2005-12-01 2009-12-29 Nitto Denko Corporation Wired circuit board
US7723617B2 (en) 2006-08-30 2010-05-25 Nitto Denko Corporation Wired circuit board and production method thereof
CN102312120A (zh) * 2011-09-01 2012-01-11 王一平 耐电迁移银铟合金键合丝及其制备方法
US8134080B2 (en) 2005-07-07 2012-03-13 Nitto Denko Corporation Wired circuit board
US8760815B2 (en) 2007-05-10 2014-06-24 Nitto Denko Corporation Wired circuit board

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10103294C1 (de) * 2001-01-25 2002-10-31 Siemens Ag Träger mit einer Metallfläche und mindestens ein darauf angeordneter Chip, insbesondere Leistungshalbleiter
KR100422271B1 (ko) * 2001-05-02 2004-03-10 이규한 마이크로 비지에이 방식 반도체 패키지의 빔 리드
US7021346B2 (en) * 2004-01-26 2006-04-04 Ao Yu Chang Bamboo mat board and method for producing the same
US9070392B1 (en) 2014-12-16 2015-06-30 Hutchinson Technology Incorporated Piezoelectric disk drive suspension motors having plated stiffeners
WO2017003782A1 (en) 2015-06-30 2017-01-05 Hutchinson Technology Incorporated Disk drive head suspension structures having improved gold-dielectric joint reliability

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SE312708B (zh) * 1966-01-21 1969-07-21 Engelhard Ind Inc
GB1461474A (en) * 1974-07-03 1977-01-13 Fulmer Res Inst Ltd Electrical connectors and a method of preparing stable electro platings
JPS5716193A (en) * 1980-05-23 1982-01-27 Furukawa Electric Co Ltd:The Silver coating material for electronic parts
EP0250146A1 (en) 1986-06-16 1987-12-23 Texas Instruments Incorporated Palladium plated lead frame for integrated circuit
JPH06184789A (ja) * 1992-12-22 1994-07-05 Asahi Glass Co Ltd 耐酸化性金属部材、メッキ液、及び回路装置
JPH09223771A (ja) * 1995-12-15 1997-08-26 Furukawa Seimitsu Kinzoku Kogyo Kk 電子部品用リード部材及びその製造方法
JPH09275182A (ja) * 1996-04-02 1997-10-21 Seiichi Serizawa 半導体装置用リ−ドフレ−ム
JPH1027873A (ja) * 1996-07-11 1998-01-27 Nippon Koujiyundo Kagaku Kk 半導体装置用リードフレーム
JPH118341A (ja) * 1997-06-18 1999-01-12 Mitsui High Tec Inc 半導体装置用リードフレーム

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100359657C (zh) * 2002-03-26 2008-01-02 株式会社野毛电气工业 键合线和使用该键合线的集成电路装置
US8134080B2 (en) 2005-07-07 2012-03-13 Nitto Denko Corporation Wired circuit board
CN100468845C (zh) * 2005-08-12 2009-03-11 鸿富锦精密工业（深圳）有限公司 集电板及其制作方法
US7638873B2 (en) 2005-12-01 2009-12-29 Nitto Denko Corporation Wired circuit board
US7723617B2 (en) 2006-08-30 2010-05-25 Nitto Denko Corporation Wired circuit board and production method thereof
US8266794B2 (en) 2006-08-30 2012-09-18 Nitto Denko Corporation Method of producing a wired circuit board
US8760815B2 (en) 2007-05-10 2014-06-24 Nitto Denko Corporation Wired circuit board
CN102312120A (zh) * 2011-09-01 2012-01-11 王一平 耐电迁移银铟合金键合丝及其制备方法

Also Published As

Publication number Publication date
KR20010088882A (ko) 2001-09-29
CN1245756C (zh) 2006-03-15
AU2001278818A1 (en) 2002-03-04
TW529126B (en) 2003-04-21
US20020074662A1 (en) 2002-06-20
WO2002017396A1 (en) 2002-02-28
JP2002173796A (ja) 2002-06-21
EP1184904A3 (en) 2006-05-17
KR100379128B1 (ko) 2003-04-08
US6424046B1 (en) 2002-07-23
EP1184904A2 (en) 2002-03-06

Similar Documents

Publication Publication Date Title
US5551626A (en) Diffusion joining method and a paste used therefor
CN1245756C (zh) 用三元素合金制作半导体器件的衬底
JP2007519261A (ja) 電子部品のスズ表面における半田付け性の保存及びウイスカ成長の阻止
EP0751564A2 (en) Ultra-thin noble metal coatings for electronic packaging
CN101981235A (zh) 连接零件用金属材料及其制造方法
DE102006017042A1 (de) Zuleitungsrahmen für ein Halbleiterbauteil
CN1321784A (zh) 高密度柱栅阵列连接及其方法
AU5645000A (en) High-strength solder joint
JP2001110971A (ja) 半導体パッケージ用リードフレーム及びその製造方法
JPH08111484A (ja) リードフレーム
US20050249969A1 (en) Preserving solderability and inhibiting whisker growth in tin surfaces of electronic components
US20050249968A1 (en) Whisker inhibition in tin surfaces of electronic components
CN103988301B (zh) 引线框架和使用该引线框架制造的半导体封装件
US6287896B1 (en) Method for manufacturing lead frames and lead frame material for semiconductor device
US20060237824A1 (en) Lead frame for semiconductor package and method of manufacturing the same
US7233072B2 (en) Electronic part and surface treatment method of the same
JPS6349382B2 (zh)
JP2781017B2 (ja) セラミックパッケージ
Baudrand Use of electroless nickel to reduce gold requirements
Baldwin et al. Gallium alloy interconnects for flip-chip assembly applications
WO2000078109A9 (en) Improved bga solder ball shear strength
KR100691337B1 (ko) 국부 도금을 이용한 반도체 장치 제조용 리드 프레임
Beigle Alternate metal finishes for wire bond and soldering applications
KR100708299B1 (ko) 전자장치 제조용 다층금속 기판
KR100691338B1 (ko) 반도체장치 제조용 리드프레임

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
C17 Cessation of patent right
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20060315

Termination date: 20130815