CN1314124C - 用于finfet和cmos器件的集成反熔断器结构及其制造方法 - Google Patents

用于finfet和cmos器件的集成反熔断器结构及其制造方法 Download PDF

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CN1314124C
CN1314124C CNB028300467A CN02830046A CN1314124C CN 1314124 C CN1314124 C CN 1314124C CN B028300467 A CNB028300467 A CN B028300467A CN 02830046 A CN02830046 A CN 02830046A CN 1314124 C CN1314124 C CN 1314124C
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J·H·兰金
W·W·阿巴蒂尔
J·S·布朗
K·V·查蒂
W·R·通蒂
R·J·小戈希尔
D·M·弗莱德
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GlobalFoundries Inc
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Abstract

本发明提供了与如FINFET或平面CMOS器件的半导体器件集成的反熔断器结构(100)及其制造方法。提供覆盖设置于衬底(10)上的绝缘体(3)的半导体材料区(11)；蚀刻工艺暴露半导体材料中的多个角(111-114)。氧化暴露的角，以在角处形成拉伸尖端(111t-114t)；除去覆盖尖端的氧化物(31)。然后，在半导体材料上形成例如栅极氧化物的氧化物层(51)并覆盖角；该层在角处具有减小的厚度。形成在角处与氧化物层(51)接触的导电材料层(60)，由此，在半导体材料和导电材料层之间穿过氧化物层，形成多个可能的击穿路径。向所述结构施加如老化电压的电压，以使击穿路径的至少一个转化为导电路径(103、280)。

Description

用于FINFET和CMOS器件的集成反熔断器结构及其制造方法
技术领域
本发明涉及超大规模集成器件的制造，更具体地说，涉及其中集成有电反熔断器(antifuse)的FINFET和平面CMOS器件。
背景技术
在对获得更小、更快和更有效的半导体器件正在进行的努力中，设计者和工程师曾试图按比例缩小器件的所有尺寸和特征。尤其在场效应晶体管(FETs)的设计和制造中，发现两种特征很难按比例缩小：器件电流(它涉及FET栅极的尺寸)和熔断器结构的尺寸。
为了解决器件在栅极设计中的缩放比例的限制，最近为了发展用于制造新颖栅极类型的制造方法，做了相当多的工作。“双栅极”或“环绕栅极”设计中的一个例子是FINFET器件，其中栅极氧化物生长在硅的垂直鳍片的正面上，而栅极在硅特征的两个侧面上，当栅极被激活时，它会充分耗尽硅。图1A示出了在绝缘体上硅(SOI)衬底上形成的两个这样的鳍片结构1、2，其中体硅衬底10的顶部具有在其上形成的掩埋氧化物(BOX)层3，而器件在覆盖BOX的另一硅层中形成。在通过使用用于图像转移的蚀刻硬掩膜12、22蚀刻该硅层下至BOX表面形成硅鳍片11、21之后，示出了硅鳍片11、21。然后可以在硅鳍片的两个正面(例如鳍片11的正面11a和11b)上生长栅极氧化物。在提供比常规平面CMOS器件更高的表面栅极密度，以及更好的器件性能和更低的功耗上，FINFET技术显示了希望。
同样，希望将熔断器和反熔断器的制造融合进用于制造各种FET结构的现有工艺中。如本领域所公开，熔断器是容易被除去(烧断)以形成开路电路的导体，而反熔断器是可以被电击穿以形成永久导电路径的介质区域。当芯片上器件的密度增加时，为了提供每个独立电路的具体寻址(addressing)，熔断器和反熔断器的数量也会增加。优选这样形成熔断器和反熔断器，使芯片面积的消耗最小并不需要附加光刻步骤。熔断器的最近缩放比例没有跟上其余硅特征的缩放比例速率，因此专用于熔断器的芯片区域占了总芯片面积的较大部分。
如果用浅沟槽隔离(STI)形成器件，那么隔离沟槽的蚀刻可以在硅中的沟槽侧壁与顶部硅表面或沟槽底部相遇的地方形成尖角。如果这些角没有被另外的工艺变圆，覆盖这些角的介质层会被变薄并出现可靠性问题(参见美国专利No.6,150,234)。同样，穿过介质层的接触孔的蚀刻可以导致带有尖角的沟槽。另一方面，由于电场通常在角处增强，尖沟槽角存在便利地形成反熔断器的可能性(沟槽在导电材料中形成或被导电材料覆盖)；而覆盖角的绝缘层被变薄(参见美国专利No.5,502,000；美国专利No.5,322,812；美国专利No.6,096,580和其中引用的参考文献；以及Chen等，IEEE Electron Device Letters 13，53(1992))。
因为需要明显更小的芯片面积，优选制造电熔断器而不是机械熔断器作为晶体管制造工艺的一部分。通过激光切除或其它机械方式“烧断”常规熔断器，以制造电开路。通过芯片中的内部电布线“烧断”电熔断器或反熔断器；从而用于电熔断器/反熔断器的面积需求非常小。另外，机械熔断器需要环绕并在它们之下的保护区，以防止熔断器烧断技术不对芯片电路造成其它有害影响。电熔断器和反熔断器没有这些要求。因此，为了节省芯片面积并因而减少制造成本，希望用最少的附加制造步骤，制造可以与FINFET和平面CMOS器件的制造集成的电熔断器或反熔断器。
发明内容
本发明通过提供一种用于制造与半导体器件集成的反熔断器结构的方法，用最少的附加工艺步骤解决了上述需求。提供覆盖设置于衬底上的绝缘体的半导体材料区；蚀刻工艺暴露半导体材料中的多个角。氧化暴露的角，以在其上形成氧化物，然后除去氧化物，在各个角上形成半导体材料的多个拉伸尖端；除去覆盖尖端的氧化物。然后，在半导体材料上形成例如栅极氧化物的氧化物层并覆盖角；该氧化物层具有额定厚度和在所述角处比所述额定厚度小的减小的厚度。形成在角处与氧化物层接触的导电材料层，由此，在半导体材料和导电材料层之间，穿过氧化物层，形成多个可能的击穿路径。当需要电激活一个具体的反熔断器时，向所述结构施加如老化电压的电压，以使击穿路径的至少一个转化为导电路径。
可以用FlNFET或平面CMOS器件实现该工艺，以使反熔断器结构与那些器件集成。
值得注意的是，用该工艺制造的反熔断器结构，每个具有多个电平行的可能的击穿路径。可以通过击穿在这些路径的任何一个处的氧化物层来形成导电路径。该冗余(redundancy)帮助确保器件将是可编程的。施加的电压通常是用于器件的额定电压的约1.5倍。
此外，根据本发明，提供了与半导体器件集成的反熔断器结构。该反熔断器结构包括覆盖设置于衬底上的绝缘体的半导体材料区；该半导体材料具有多个角，在各个角处具有半导体材料的多个拉伸尖端。氧化物层设置于半导体材料上并覆盖角；该氧化物层具有额定厚度和在角处比额定厚度小的减小的厚度。该结构还包括导电材料层，它在角处与氧化物层接触。该结构的特征是在半导体材料和导体材料层之间，穿过减小的厚度的氧化物层，在角处设置多个可能的击穿路径；以及通过氧化所暴露的角形成拉伸尖端然后去除所形成的氧化物，其中所形成的氧化物与氧化物层不同。同样值得注意的是，在硅级上集成反熔断器结构，并由此需要最小的芯片面积。相对于标准晶体管制造工艺，用于反熔断器的制造工艺只需要一个附加掩蔽层。
附图说明
图1A-G是根据本发明的第一实施例，用于在FINFET器件中集成的反熔断器的制造工艺步骤的示意图。
图2A-E是根据本发明的第二实施例，用于在平面CMOS器件中集成的反熔断器的制造工艺步骤的示意图。
具体实施方式
根据本发明，通过氧化暴露的角，在半导体栅极结构中形成多个反熔断器。该工艺既可以应用到FINFET，又可以应用到平面CMOS栅极结构中，如下面详细所述。
(1)用于FINFET器件的反熔断器
图1A示出了两个相邻的硅鳍片11、21，它们可以在栅电极工艺之后形成FINFETs的主体。在该图中，这些鳍片中的一个(鳍片11)替代地制作为反熔断器结构。用保护性抗蚀剂层25覆盖包括鳍片21和硬掩膜22的鳍片结构2；暴露并显影抗蚀剂，以暴露鳍片结构1。然后，使BOX层3的暴露部分经受底切硅鳍片11的各向同性蚀刻(参见图1B)。同样在该步骤中除去硬掩膜12。应该注意，蚀刻和底切在硅鳍片11上产生了四个暴露的角111-114。
然后，用低温氧化工艺氧化鳍片11的硅表面，以在其上形成氧化物层31。氧化工艺优选为本领域的技术人员公知的900℃下的干/湿/干工艺。在氧化工艺期间，角111-114处的二维应力导致形成图1C中按放大比例示出的硅的拉伸尖端111t、112t、113t、114t。在氧化期间由于角处的氧化物膜中的应力形成的这些尖端，减小了氧的扩散速率。然后用各向同性蚀刻工艺除去氧化物层31，在此之后剥离抗蚀剂25(参见图1D)。
在除去抗蚀剂25之前，有利地将n+离子注入到熔断器区中。虽然不需要将结构用作反熔断器的可操作性，但是该注入工艺使熔断器的硅部分成为了改善的导体，并且改善了鳍片在所需编程电压和可靠性方面的性能。
然后在硅鳍片11和21上实施标准栅极氧化物预清洁，在此之后，分别在鳍片11和21的暴露表面上生长栅极氧化物51、52。栅极氧化物的厚度通常在15-40的范围内。然后在鳍片上淀积多晶硅导体层60；该多晶硅层充当用于FINFET200的栅极导体，同时在反熔断器100中提供导电路径。在两个结构上淀积并构图抗蚀剂层65，以限定晶体管栅极，和熔断器的一个节点。如图1E所示，开口66分开了两种类型的结构。然后蚀刻在该开口中暴露的多晶硅层60的部分，并剥离掉抗蚀剂65。这样，就相互电隔离了FINFET结构200和反熔断器结构100(参见图1F)。
图1G是详细视图，示出了覆盖具有尖端111t、112t、113t、114t的鳍片11的角的栅极氧化物51，在角(尖端)处的氧化物相对于它的额定厚度具有减小的厚度。为了说明的目的，用放大的方式示出了角的尖端；相对于覆盖鳍片正面上的中心区域的氧化物，尖端处的氧化物实际变薄了约15％-30％。尖端在图1G中只示出了横截面；应该理解，拉伸尖端沿着鳍片的边缘形成，所以尖脊在与图平面正交的鳍片的长度方向上延伸。应该注意，图1G中有四个可能穿过变薄的氧化物的击穿路径，所以在反熔断器设计中有就地的冗余。所有这些击穿路径是电平行的，所以它们中的任何一个的实际击穿足以使反熔断器转化为可以用于在芯片中重新发送数据或指令的电短路。因此，对于反熔断器的编程或写操作(换句话说，将反熔断器转化为导电路径)包括在一个角上施加足以引起击穿的电压(例如图1G中的角113，形成击穿路径103)。据发现，使用用于FET器件的通常是额定电压的1.5倍的老化(burn-in)电压，可以有效地执行写操作。例如，对于约1.2V的额定电压，老化电压应该是约1.8V。因此，在不会相反影响芯片上其它器件的正常工作的情况下，可以在老化电压下执行反熔断器的写操作。
(2)用于平面CMOS器件的反熔断器
上述方法的主要特征可以适用于在SOI衬底上制造的平面COMS器件。图2A示出了三个硅栅极区211、212、213，其中区域211被制成反熔断器而不是FET。将硅区设置于衬底210上的掩埋氧化物(BOX)203上，并通过浅沟槽隔离区(STI)215将它们分开。在所有的硅区上淀积抗蚀剂层205，并接着构图它们，以使抗蚀剂中的开口220暴露硅区211和被制成反熔断器的隔离区215的部分。然后蚀刻STI材料215(通常为氧化物)，以暴露硅区211的角211a、211b。
然后实施低温氧化工艺，由此通过氧化物层231覆盖暴露的硅表面，如图2B所示。该氧化工艺促使形成角处的硅尖端211t，如图2C所示。如上所述，只在横截面中示出了尖端；尖脊在与图平面正交的区域211的长度方向上延伸。然后使用各向同性蚀刻工艺除去氧化物层231。此时，为了有利于反熔断器的编程(写)，优选但不需要将n+杂质注入硅区211(它将变成反熔断器)。然后除去抗蚀剂205。
然后，实施标准预清洁并分别在硅区211、212、213的表面上生长栅极氧化物251、252、253(参见图2D)。栅极氧化物通常为10-20厚。在所有硅区和隔离区上淀积多晶硅层260。然后用晶体管栅极图像构图该层，限定反熔断器的一个节点，并蚀刻该层，由此在隔离区215上形成开口266，将MOS器件区与反熔断器彼此之间电隔离。
图2E是用于平面CMOS器件的反熔断器结构的详细视图。为了说明的目的，放大了尖端211t附近的栅极氧化物的变薄；该位置的栅极氧化物通常比反熔断器中心区要薄15％-30％(也就是说，层254在角处具有比10-20的额定厚度减小15％-30％的厚度)。由于硅的至少两个暴露的角被氧化，所以在掺杂硅区211和多晶硅导体260之间至少具有两个潜在的击穿路径。使用与老化电压一样低的电压，编程(写)反熔断器形成了图2E示意性示出的导电路径280。
工业适用性
本发明通常适用于制造经常需要专用集成电路(ASICs)的现场可编程门阵列的问题。另外，反熔断器可以用于重新发送冗余的数据，例如在存储器电路或在先进微处理器中。更具体地说，本发明适用于采用FINFET或平面CMOS技术的门阵列或SRAMs。本发明的一个重要优点是在每个反熔断器位置上提供了多余的击穿点。此外，反熔断器制造工艺相对于标准晶体管制造工艺只需要一个附加掩蔽层。而且，反熔断器在硅级上(即，在制造相邻晶体管的工艺期间)制造，结果明显节省了芯片上的面积。
虽然结合具体实施例描述了本发明，但是，鉴于上述描述，明显地是，许多替换、修改和变化对于本领域的技术人员来说是显而易见的。因此，本发明旨在包含落入本发明和所附权利要求的范围和精神内的所有这些替换、修改和变化。

Claims (17)

1.一种用于制造与半导体器件集成的反熔断器结构(100)的方法，该方法包括以下步骤：
形成覆盖设置于衬底(10)上的绝缘体(3)的半导体材料的区域(11)；
实施蚀刻工艺，以暴露所述半导体材料中的多个角(111-114)；
通过氧化所述暴露的角(111、112、113、114)以在其上形成氧化物(31)，然后除去所述氧化物(31)，在所述各个角上形成所述半导体材料的多个拉伸尖端(111t、112t、113t、114t)；
随后在所述半导体材料上形成氧化物层(51)，并覆盖所述角，所述氧化物层具有额定厚度和在所述角处比所述额定厚度小的减小的厚度；以及
形成在所述角处与所述氧化物层(51)接触的导电材料层(60)，
由此，在所述半导体材料和所述导电材料层之间，穿过所述氧化物层，在所述角处形成多个可能的击穿路径。
2.根据权利要求1的方法，其特征在于所述半导体材料的区域(11)是在FINFET工艺中形成的鳍片。
3.根据权利要求1的方法，其特征在于所述半导体材料的区域(211)是在平面CMOS工艺中形成的栅极区。
4.根据权利要求2或权利要求3的方法，还包括掺杂所述半导体材料的区域(11、211)的步骤。
5.根据权利要求1的方法，其特征在于根据低温氧化工艺实施氧化所述暴露的角的步骤。
6.根据权利要求1的方法，其特征在于所述击穿路径是电平行的。
7.根据权利要求1的方法，还包括给所述反熔断器结构施加电压的步骤，从而将所述击穿路径的至少一个转化为穿过所述氧化物层(51、251)的导电路径(103、280)。
8.根据权利要求7的方法，其特征在于根据用于所述器件的老化工艺施加所述电压。
9.根据权利要求7的方法，其特征在于所述器件具有额定电压，而所述施加的电压是所述约额定电压的约1.5倍。
10.一种与半导体器件集成的反熔断器结构(100)，该结构包括：
半导体材料的区域(11)，覆盖设置于衬底(10)上的绝缘体(3)，所述半导体材料具有多个角(111-114)，在所述各个角处具有所述半导体材料的多个拉伸尖端(111t、112t、113t、114t)；
氧化物层(51)，在所述半导体材料上并覆盖所述角且与所述角接触，所述氧化物层具有额定厚度和在所述角处比所述额定厚度小的减小的厚度；以及
导电材料层(60)，与所述氧化物层(51)在所述角处接触，
其特征在于在所述半导体材料和所述导电材料层之间，穿过所述减小的厚度的氧化物层，在所述角处设置多个可能的击穿路径，以及
通过氧化所述暴露的角(111、112、113、114)形成所述拉伸尖端然后去除所形成的氧化物(31)，其中所形成的氧化物(31)与所述氧化物层(51)不同。
11.根据权利要求10的反熔断器结构，其特征在于所述半导体材料的区域(11)是在FINFET工艺中形成的鳍片。
12.根据权利要求10的反熔断器结构，其特征在于所述半导体材料的区域(211)是在平面CMOS工艺中形成的栅极区。
13.根据权利要求10的反熔断器结构，其特征在于所述半导体材料的区域(11、211)是掺杂材料区。
14.根据权利要求10的反熔断器结构，其特征在于所述击穿路径是电平行的。
15.根据权利要求10的反熔断器结构，其特征在于所述击穿路径的至少一个是通过对所述氧化物层(51、251)施加电压形成的穿过所述氧化物层的导电路径(103、280)。
16.根据权利要求15的反熔断器结构，其特征在于所述施加的电压是用于所述器件的老化电压。
17.根据权利要求16的反熔断器结构，其特征在于所述器件具有额定电压，而所述施加的电压是所述额定电压的约1.5倍。
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