CN1307689C - 用于使n－沟道与p－沟道晶体管个别最佳化的差别隔离层的形成方法 - Google Patents

用于使n－沟道与p－沟道晶体管个别最佳化的差别隔离层的形成方法 Download PDF

Info

Publication number
CN1307689C
CN1307689C CNB028249763A CN02824976A CN1307689C CN 1307689 C CN1307689 C CN 1307689C CN B028249763 A CNB028249763 A CN B028249763A CN 02824976 A CN02824976 A CN 02824976A CN 1307689 C CN1307689 C CN 1307689C
Authority
CN
China
Prior art keywords
channel transistor
channel
source
isolation layer
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
CNB028249763A
Other languages
English (en)
Chinese (zh)
Other versions
CN1605115A (zh
Inventor
D·H·琼
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of CN1605115A publication Critical patent/CN1605115A/zh
Application granted granted Critical
Publication of CN1307689C publication Critical patent/CN1307689C/zh
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/017—Manufacturing their source or drain regions, e.g. silicided source or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0184—Manufacturing their gate sidewall spacers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)
CNB028249763A 2001-12-14 2002-12-11 用于使n－沟道与p－沟道晶体管个别最佳化的差别隔离层的形成方法 Expired - Lifetime CN1307689C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/014,426 2001-12-14
US10/014,426 US6562676B1 (en) 2001-12-14 2001-12-14 Method of forming differential spacers for individual optimization of n-channel and p-channel transistors

Publications (2)

Publication Number Publication Date
CN1605115A CN1605115A (zh) 2005-04-06
CN1307689C true CN1307689C (zh) 2007-03-28

Family

ID=21765406

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB028249763A Expired - Lifetime CN1307689C (zh) 2001-12-14 2002-12-11 用于使n－沟道与p－沟道晶体管个别最佳化的差别隔离层的形成方法

Country Status (8)

Country Link
US (1) US6562676B1 (enExample)
EP (1) EP1454342A2 (enExample)
JP (1) JP2005513774A (enExample)
KR (1) KR100941742B1 (enExample)
CN (1) CN1307689C (enExample)
AU (1) AU2002359686A1 (enExample)
TW (1) TWI260731B (enExample)
WO (1) WO2003052799A2 (enExample)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6828219B2 (en) * 2002-03-22 2004-12-07 Winbond Electronics Corporation Stacked spacer structure and process
US7416927B2 (en) * 2002-03-26 2008-08-26 Infineon Technologies Ag Method for producing an SOI field effect transistor
US6894353B2 (en) * 2002-07-31 2005-05-17 Freescale Semiconductor, Inc. Capped dual metal gate transistors for CMOS process and method for making the same
US6677201B1 (en) * 2002-10-01 2004-01-13 Texas Instruments Incorporated Method of fabricating thermal CVD oxynitride and BTBAS nitride sidewall spacer for metal oxide semiconductor transistors
US6969646B2 (en) * 2003-02-10 2005-11-29 Chartered Semiconductor Manufacturing Ltd. Method of activating polysilicon gate structure dopants after offset spacer deposition
US6967143B2 (en) * 2003-04-30 2005-11-22 Freescale Semiconductor, Inc. Semiconductor fabrication process with asymmetrical conductive spacers
US7192876B2 (en) * 2003-05-22 2007-03-20 Freescale Semiconductor, Inc. Transistor with independent gate structures
US20050059260A1 (en) * 2003-09-15 2005-03-17 Haowen Bu CMOS transistors and methods of forming same
US7033897B2 (en) * 2003-10-23 2006-04-25 Texas Instruments Incorporated Encapsulated spacer with low dielectric constant material to reduce the parasitic capacitance between gate and drain in CMOS technology
JP4796747B2 (ja) * 2003-12-25 2011-10-19 富士通セミコンダクター株式会社 Ｃｍｏｓ半導体装置の製造方法
US20050275034A1 (en) * 2004-04-08 2005-12-15 International Business Machines Corporation A manufacturable method and structure for double spacer cmos with optimized nfet/pfet performance
US7687861B2 (en) * 2005-10-12 2010-03-30 Taiwan Semiconductor Manufacturing Company, Ltd. Silicided regions for NMOS and PMOS devices
US7476610B2 (en) * 2006-11-10 2009-01-13 Lam Research Corporation Removable spacer
DE102009021490B4 (de) * 2009-05-15 2013-04-04 Globalfoundries Dresden Module One Llc & Co. Kg Mehrschrittabscheidung eines Abstandshaltermaterials zur Reduzierung der Ausbildung von Hohlräumen in einem dielektrischen Material einer Kontaktebene eines Halbleiterbauelements
US9449883B2 (en) * 2009-06-05 2016-09-20 Renesas Electronics Corporation Semiconductor device and method for manufacturing the same
DE102010064284B4 (de) * 2010-12-28 2016-03-31 GLOBALFOUNDRIES Dresden Module One Ltd. Liability Company & Co. KG Verfahren zur Herstellung eines Transistors mit einer eingebetteten Sigma-förmigen Halbleiterlegierung mit erhöhter Gleichmäßigkeit
US20130026575A1 (en) * 2011-07-28 2013-01-31 Synopsys, Inc. Threshold adjustment of transistors by controlled s/d underlap
US10038063B2 (en) 2014-06-10 2018-07-31 International Business Machines Corporation Tunable breakdown voltage RF FET devices
JP6275559B2 (ja) 2014-06-13 2018-02-07 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
US10361282B2 (en) * 2017-05-08 2019-07-23 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming a low-K spacer

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1177207A (zh) * 1996-06-10 1998-03-25 Lg半导体株式会社 半导体器件的隔离区的制造方法
CN1215229A (zh) * 1997-06-05 1999-04-28 日本电气株式会社 一种半导体器件的制造方法
US5943565A (en) * 1997-09-05 1999-08-24 Advanced Micro Devices, Inc. CMOS processing employing separate spacers for independently optimized transistor performance
US6316302B1 (en) * 1998-06-26 2001-11-13 Advanced Micro Devices, Inc. Isotropically etching sidewall spacers to be used for both an NMOS source/drain implant and a PMOS LDD implant

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR970030891A (ko) * 1995-11-21 1997-06-26 윌리엄 이. 힐러 Mos 기술에서의 급속 열 어닐링 처리
JPH09167804A (ja) * 1995-12-15 1997-06-24 Hitachi Ltd 半導体装置及びその製造方法
US5846857A (en) * 1997-09-05 1998-12-08 Advanced Micro Devices, Inc. CMOS processing employing removable sidewall spacers for independently optimized N- and P-channel transistor performance
JP2000307015A (ja) * 1999-04-22 2000-11-02 Oki Electric Ind Co Ltd デュアルゲートｃｍｏｓｆｅｔの製造方法
US5981325A (en) * 1999-04-26 1999-11-09 United Semiconductor Corp. Method for manufacturing CMOS
JP3275896B2 (ja) * 1999-10-06 2002-04-22 日本電気株式会社 半導体装置の製造方法
KR20010065744A (ko) * 1999-12-30 2001-07-11 박종섭 모스형 트랜지스터 제조방법
TW459294B (en) * 2000-10-26 2001-10-11 United Microelectronics Corp Self-aligned offset gate structure and its manufacturing method

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1177207A (zh) * 1996-06-10 1998-03-25 Lg半导体株式会社 半导体器件的隔离区的制造方法
CN1215229A (zh) * 1997-06-05 1999-04-28 日本电气株式会社 一种半导体器件的制造方法
US5943565A (en) * 1997-09-05 1999-08-24 Advanced Micro Devices, Inc. CMOS processing employing separate spacers for independently optimized transistor performance
US6316302B1 (en) * 1998-06-26 2001-11-13 Advanced Micro Devices, Inc. Isotropically etching sidewall spacers to be used for both an NMOS source/drain implant and a PMOS LDD implant

Also Published As

Publication number Publication date
WO2003052799A3 (en) 2003-08-14
AU2002359686A1 (en) 2003-06-30
WO2003052799A2 (en) 2003-06-26
AU2002359686A8 (en) 2003-06-30
JP2005513774A (ja) 2005-05-12
TW200303069A (en) 2003-08-16
KR100941742B1 (ko) 2010-02-11
EP1454342A2 (en) 2004-09-08
KR20040064305A (ko) 2004-07-16
CN1605115A (zh) 2005-04-06
US6562676B1 (en) 2003-05-13
TWI260731B (en) 2006-08-21

Similar Documents

Publication Publication Date Title
CN1307689C (zh) 用于使n－沟道与p－沟道晶体管个别最佳化的差别隔离层的形成方法
KR100344735B1 (ko) 전계 효과 트랜지스터와 반도체 구조물 및 그의 제조 방법
JP2663402B2 (ja) Ｃｍｏｓ集積回路デバイスの製造方法
US6514810B1 (en) Buried channel PMOS transistor in dual gate CMOS with reduced masking steps
US20050056892A1 (en) Fully-depleted castellated gate MOSFET device and method of manufacture thereof
US20020055220A1 (en) Integration of high voltage self-aligned MOS components
TWI419207B (zh) 製造半導體裝置之方法
US7439139B2 (en) Fully-depleted castellated gate MOSFET device and method of manufacture thereof
JP3394408B2 (ja) 半導体装置及びその製造方法
JPH08250728A (ja) 電界効果型半導体装置及びその製造方法
EP0495329A2 (en) High performance/high density bicmos process
US20100327374A1 (en) Low cost transistors using gate orientation and optimized implants
CN119050141A (zh) 利用埋置绝缘层作为栅极介电质的高压晶体管
US6797555B1 (en) Direct implantation of fluorine into the channel region of a PMOS device
US10217838B2 (en) Semiconductor structure with multiple transistors having various threshold voltages
US6767778B2 (en) Low dose super deep source/drain implant
KR100638546B1 (ko) 트랜지스터 구조물 형성방법 및 트랜지스터 구조물
US20020153559A1 (en) Integrated circuit structure and method therefore
KR20050069579A (ko) 반도체 소자 및 그의 제조방법
JP3425043B2 (ja) Ｍｉｓ型半導体装置の製造方法
JP3114654B2 (ja) 半導体装置の製造方法
KR0155536B1 (ko) BiCMOS 소자의 제조방법
KR20040038379A (ko) 실리콘게르마늄 이종접합바이폴라소자가 내장된 지능형전력소자 및 그 제조 방법
KR100233707B1 (ko) 듀얼 게이트 씨모오스 트랜지스터의 제조방법
US7101746B2 (en) Method to lower work function of gate electrode through Ge implantation

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CX01 Expiry of patent term

Granted publication date: 20070328

CX01 Expiry of patent term