CN1301430A - Circuit for reducing leaking current - Google Patents
Circuit for reducing leaking current Download PDFInfo
- Publication number
- CN1301430A CN1301430A CN99806255A CN99806255A CN1301430A CN 1301430 A CN1301430 A CN 1301430A CN 99806255 A CN99806255 A CN 99806255A CN 99806255 A CN99806255 A CN 99806255A CN 1301430 A CN1301430 A CN 1301430A
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- China
- Prior art keywords
- voltage
- transistor
- circuit
- cut
- circuit arrangement
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0008—Arrangements for reducing power consumption
- H03K19/0016—Arrangements for reducing power consumption by using a control or a clock signal, e.g. in order to apply power supply
Abstract
The invention relates to a circuit made of parts (2,3) consisting of transistors with a low threshold voltage (NV transistors). In order to reduce leakage current from said circuit parts (2,3), each part is coupled to a supply voltage (VDD, VSS) by means of an intermediate switching transistor (MP1, MN1) with a high threshold voltage (HV transistor) and an NV control transistor (MNH1, MPH1) is connected in parallel to the HV switching transistor (MP1, MN1).
Description
The present invention relates to a kind of circuit arrangement, the sort circuit device has the circuit part of being made up of the transistor (NV-transistor) of low cut-ff voltage.
In move using, the low power consumption of microelectronic circuit arrangement is an ideal value especially, because under the situation of existing battery or battery capacity, this is corresponding to have prolonged the operating time.For example realized low power consumption, but this will reduce switching speed in MOS transistor by reducing supply voltage.If except low power consumption, also need transistor switch speed height simultaneously, so except supply voltage, also must reduce transistorized cut-ff voltage.For example when supply voltage is 1 volt, typical transistorized cut-ff voltage is necessary for 0.3 to 0.2 volt (be equivalent to supply voltage 1/4th), and during 3.3 volts of supply voltages, cut-ff voltage is 0.6 to about 0.4 volt by comparison.But when the transistor closure was not just controlled, low cut-ff voltage caused that leakage current significantly improves, and when circuit arrangement is in stand-by phase for a long time, this will cause battery or storage battery to have load especially.
Here advised multiple measure, can reduce the static leakage currents of circuit arrangement in stand-by phase.
For example people such as Shin ' ichiro Mutoh in 1996, the IEEE ISSCC uses the transistor with several cut-ff voltages, so-called many leakage voltages CMOS transistor from 168 pages of suggestions a circuit arrangement.At this moment, by the PMOS and/or the nmos pass transistor of high cut-ff voltage, microelectronic circuit arrangement is connected on supply voltage VDD or the VSS.In active state, control these transistors (grid voltage VDD and VSS are positioned on NMOS and/or the PMOS transistor), therefore line VDDL of locally supplied power source and VSSL are positioned on VDD or the VSS.In standby mode, transistor closure (VSS and VDD grid voltage are placed on NMOS and/or the PMOS transistor) therefore because the high cut-ff voltage of switching transistor has reduced leakage current, has reduced power consumption.
Therefore memory circuit partly keeps its information, and other safeguard measure generally should be arranged.Because if high-voltage switch transistor closure, cause circuit arrangement NV transistor (low cut-ff voltage transistor) high leakage current over time with the scope of circuit arrangement in all voltages adapt the information that will therefore lose storage element in the circuit part so.Avoid the possibility of information dropout to be: in the memory circuit part, to use high cut-ff voltage transistor.Yet because the coupling of memory circuit part, basically must the redesign circuit.
The other measure that reduces static leakage power consumption in stand-by phase is: biasing is used to improve the groove and the substrate electric potential of effective cut-ff voltage." biasing " expression down disclosed measure for example have at people's such as Tadahiro Kuroda IEEE ISSCC, 1996,166 pages were worked the measures that illustrate.In stand-by phase, with the voltage of groove bring up to supply voltage VDD above, with substrate electric potential be reduced to supply voltage VSS below.This causes PMOS and/or the high cut-ff voltage of nmos pass transistor, has corresponding low leakage current.The shortcoming of this measure is to need two other voltage, and does not rely on the duration of stand-by phase, always needs same electric energy to substrate and groove charging.Ifs circuit part inertia may only influence the transistorized cut-ff voltage that is arranged in groove (handle at the n groove, these transistors all are the PMOS transistors) so, and all is identical for all circuit part substrate electric potentials.
The circuit arrangement of power controlling MOSFET is disclosed in German laid-open document DE19515417A1, wherein, a control IC is connected on the supply voltage by a controllable switch, and concrete mode is: when power MOSFET disconnected, control IC connected by controllable switch.Therefore realized the remarkable quiescent current that reduced by control IC.
Based on task of the present invention be: can use one to be used in particular for moving the microelectronic circuit arrangement of using with low power consumption, wherein except guaranteeing a little current power consumption, also guarantee the switching speed that transistor is high simultaneously, wherein can reduce when circuit part transistor closure, leakage current when not having Be Controlled, special when circuit arrangement is in long stand-by phase, can reduce the load of battery or storage battery.
By finishing this task according to the circuit arrangement of claim 1.
According to the present invention, circuit part is coupled to supply voltage by the middle connection of the transistor (HV transistor) of a high cut-ff voltage, and (VDD, VSS), one of them NV oxide-semiconductor control transistors is parallel-connected to the HV switching transistor.
The present invention has the leakage current that high and low cut-ff voltage transistor can reduce circuit and circuit part by use, this circuit part comprises low cut-ff voltage transistor (NV transistor), and solution wherein according to the present invention had following advantage with respect to former measure:
-guaranteed to remain on the data in the storage element of circuit part, in the circuit part of storage, do not need other safeguard measure,
-do not need several supply voltages and/or supply voltage to control.
Realized the conversion from the activity pattern to the standby mode by data controlling signal, wherein the advantage according to measure of the present invention is can use alone for circuit part.
The design that is fit to that the present invention is other has been described in the dependent claims.
The embodiment of middle explanation describes the present invention in detail with reference to the accompanying drawings below.Illustrate respectively and illustrated:
Circuit arrangement of the present invention of Figure 1A according to first embodiment;
Figure 1B is according to the sketch of the time graph variation of the supply voltage VDDL of the circuit arrangement of first embodiment;
Device in a circuit according to the invention of Fig. 2 A according to second embodiment;
The sketch that Fig. 2 B changes according to the time graph of the supply voltage VDDL of the circuit arrangement of second embodiment and VSSL;
Device in a circuit according to the invention of Fig. 3 A according to the 3rd embodiment;
The sketch that Fig. 3 B changes according to the time graph of the supply voltage VDDL of the circuit arrangement of the 3rd embodiment and VSSL;
Device in a circuit according to the invention of Fig. 4 A according to the 4th embodiment;
The sketch that Fig. 4 B changes according to the time graph of the supply voltage VDDL of the circuit arrangement of the 4th embodiment and VSSL;
Device in a circuit according to the invention of Fig. 5 A according to the 5th embodiment;
The sketch that Fig. 5 B changes according to the time graph of the supply voltage VDDL of the circuit arrangement of the 5th embodiment and VSSL;
Fig. 6 is with respect to the curve shows figure of the PMOS leakage current of supply voltage Vds.
In the embodiments of the invention according to the figure explanation, identical reference number is represented identical circuit part below.The transistor (being that cut-ff voltage Vth is approximately 0.4V to 0.6V) that has high cut-ff voltage below is called HV transistor (high Vth transistor), and the transistor with low cut-ff voltage is called NV transistor (low Vth transistor).Illustrated embodiment is illustrated with sketch, and this checks according to simulation, and wherein the circuit part of Cun Chu circuit part and combination always is known as the piece circuit together, and it depends on pressure-wire VDDL of locally supplied power source and/or VSSL.The all crystals pipe that is included in storage in this so-called piece and combinational circuit part has low cut-ff voltage, for NMOS and/or the low cut-ff voltage lowVthn of PMOS transistor, and lowVthp ~ 0.25 volt.For switching transistor, use cut-ff voltage highVthn, the HV transistor of highVthp ~ 0.5 volt.
For each embodiment explanation about VDDL and VSSL in, operational phase reaches 0.5 μ s, after this, the beginning stand-by phase, this stand-by phase lasts till 65 μ s.Then begin another operational phase.
In all embodiment, the following part of following unified expression:
1 circuit block
2 memory circuit parts
3 combinational circuit parts
4 data inputs (data)
5 clocks inputs (clock)
The output of 6 combinational circuit parts 3
7,11 high voltage substrate
8,12 tank voltages
9,13 low pressure substrates
10,14 underlayer voltages
The data output of 15 memory circuit parts 2
The input of 16 combinational circuit parts 3
17,18 control signals, switching transistor
MP1, the switching transistor of the high cut-ff voltage of MN1 (HV transistor)
MNH1, MPH1 hangs down cut-ff voltage oxide-semiconductor control transistors (NV transistor)
In embodiment according to Figure 1A, install in a circuit according to the invention a NV-NMOS transistor MNH1 is parallel-connected to HV-PMOS switching transistor MP1, use global power voltage VDD to control this transistorized grid.NV transistor MNH1 represents a diode that is connected in parallel with HV switching transistor MP1, and polarity and NV transistor MNH1 are reverse.When the circuit arrangement active state, transistor MP1 conducting, the pressure-wire VDDL of locally supplied power source is positioned on the supply voltage VDD.If transistor MP1 closure, based on the transistorized high leakage current of NV of circuit part 2 in the piece 1 and 3, VDDL current potential decline (Figure 1B).If the current potential of VDDL reaches value VDD-lowVthn
*, transistor MNH1 conducting so.Therefore current potential remains on this value, so memory circuit part 2 can keep its data.This value lowVthn* is the transistorized cut-ff voltage of NV that improves by substrate control effect, because substrate is positioned on the source electrode electronegative potential than transistor MNH1.
Can realize reducing leakage current from leakage current to the dependence of drain-source voltage.In Fig. 6 according to this fact of measurement shows.Wherein source-drain electrode voltage Vds upwards swells with PMOS leakage current (cut-ff voltage Vth=0.2V) to the right.If source-drain electrode voltage Vds for example is reduced to 0.5 volt from 1 volt, leakage current for example reduces about 70% so.This means that voltage is supplied with needn't provide the leakage current of piece 1 in the operating state (when 1 volt), is reduced to 1/3rd leakage current but only need to provide.If drain-source voltage Vds is also lower, so once clear and definite reduction is feasible.
In the circuit arrangement according to second embodiment of Fig. 2 A, in the circuit arrangement scope, the groove current potential is supplied with VBDL with voltage and is separated output, and is connected with VDD, by the Vds dependence, may reduce leakage current in addition.In active state according to Fig. 2 A current device, transistor MP1 and MN1 conducting, equipotential line VDDL and VSSL are positioned on current potential VDD and/or the VSS.If transistor MP1 closure, so based on the transistorized high leakage current of the NV of piece 1, the current potential of VDDL decline (Fig. 2 B) so.If the current potential of VDDL reaches value VDD-lowVthn*, transistor begins the conducting electric current so.If VSSL occurs equally for current potential: if current potential VSS reaches value VSS+lowVthp*=lowVthp* (because VSS=0), transistor MPH1 begins conducting so.Therefore, current potential VDDL and VSSL remain on this value, so memory circuit part 2 can keep its data.Value lowVthn* and lowVthp* are the transistorized cut-ff voltages of NV (groove and substrate are positioned at than the higher or lower current potential of each source electrode) that improves by substrate control effect.Here the source-drain electrode voltage for closed transistor in switch sections 2 and 3 clearly is reduced to below half of VDD, and this will form next lower leakage current.Improved the transistorized effective cut-ff voltage of NV in the piece 1 simultaneously, because substrate electric potential and groove current potential remain on VSS and/or the VDD.This is corresponding to the bias voltage of substrate when not having additional voltage source.Therefore the cut-ff voltage that improves causes further reducing the leakage current of circuit part 2 and 3, and this supplies with VDD by power supply and provides.According to simulation, 1/15 when leakage current can be reduced to 1 volt.
Fig. 3 A illustrates the 3rd embodiment who revised, and wherein, compares with second embodiment of above explanation, only needs to use (numeral) HV switching transistor MN1, has one and is parallel to switch NV transistor MNH1 as diode.Advantage is: compare with embodiment described above, the area that switching transistor MN1 and " diode transistors " MPH1 need reduces half.In this case, in the N raceway groove NV transistor of the circuit part 2 of piece 1 and 3, only improve cut-ff voltage by the substrate control effect.In the P raceway groove NV transistor that blocks, reduce leakage current by low drain-source voltage.According to simulation and 1 volt of comparison, leakage current can be determined and will hang down to 1/10.Fig. 3 B explanation VDDL and VSSL are in the variation of stand-by phase.
In above-mentioned embodiment, use opposite polarity switch NV transistor as diode (with respect to the HV switching transistor).This will cause the current potential of VDDL and/or VSSL to reduce and/or rising lowVthp* and/or lowVthn*, and it controls effect by means of substrate, improves the transistorized cut-ff voltage of NV.Yet can also preferably the NV switching transistor be connected in parallel in the same manner with the NV transistor polarity that is connected as diode equally.This situation illustrates in Fig. 4 A as the 4th embodiment.In circuit arrangement according to Fig. 4 A, potential shift lowVthp or the lowVthn of VDDL and VSSL, skew just has the transistorized cut-ff voltage of NV of substrate and groove current potential VSS and/or VDD (not having substrate control effect in MNH1 and MPH1).Fig. 4 B explanation is in the variation of stand-by phase VDDL and VSSL.
Situation for VDDL and VSSL skew lowVthp and/or lowVthn, picture does not prove absolutely in above embodiment, just the transistorized source-drain voltage of NV is too high in the piece 1, solution below providing according to the embodiment of Fig. 5 A: by the series circuit of the NV transistor (having and HV transistor identical polar) that connects as diode, the potential shift lowVthp of VDDL and VSSL and/or the several times of lowVthn.Therefore in the embodiment according to Fig. 5 A, two NV transistor MPH1, MPH2 and/or MNH1 and MNH2 parallel connection attach on switching transistor MP1 and/or the MN1.Fig. 5 B illustrates VDDL and the VSSL change curve in stand-by phase once more.
Claims (7)
1, circuit arrangement has circuit part (2,3) that low cut-ff voltage transistor (NV transistor) constitutes,
Wherein in order to reduce the leakage current of circuit part (2,3), circuit part by high cut-ff voltage switching transistor (MP1, MN1) as the centre connect be coupled to supply voltage (VDD, VSS),
It is characterized in that,
(MNH1, MPH1) (MP1's low cut-ff voltage oxide-semiconductor control transistors MN1) is connected in parallel with high cut-ff voltage switching transistor.
2, according to the circuit arrangement of claim 1,
It is characterized in that
(VDD, (MN1, (MPH1 MNH1) is connected with circuit part low cut-ff voltage oxide-semiconductor control transistors MP1) another supply voltage VSS) to be parallel-connected to a high cut-ff voltage switching transistor by one.
3, according to the circuit arrangement of claim 1 or 2,
It is characterized in that
High cut-ff voltage switching transistor (MP1, MN1) opposite with low cut-ff voltage oxide-semiconductor control transistors (MNH1, MPH1) polarity.
4, according to the circuit arrangement of one of claim 1 to 3,
It is characterized in that
Circuit part has an activity and passive (standby) operating state, realizes conversion by digital controlled signal in these two operating states.
5, according to the circuit arrangement of one of claim 1 to 4,
It is characterized in that
A plurality of low cut-ff voltage oxide-semiconductor control transistors (MNH1, MNH2, MNP1, MNP2) (MP1, MN1) polarity is connected in parallel in the same manner with high cut-ff voltage switching transistor.
6, according to the circuit arrangement of one of claim 1 to 5,
It is characterized in that
Forming circuit part (2,3) on a Semiconductor substrate, and Semiconductor substrate and all groove scope that on Semiconductor substrate, constitutes and local supply voltage (VSSL and/or VDDL) be coupled (Figure 1A).
7, according to the circuit arrangement of one of claim 1 to 5,
It is characterized in that,
Forming circuit part (2,3) on a Semiconductor substrate, and the groove scope that on Semiconductor substrate, constitutes and local supply voltage (VSSL and/or VDDL) be coupled (Fig. 2 A to Fig. 5 A).
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE19811353.6 | 1998-03-16 | ||
| DE19811353A DE19811353C1 (en) | 1998-03-16 | 1998-03-16 | Circuit arrangement for reducing leakage current |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN1301430A true CN1301430A (en) | 2001-06-27 |
Family
ID=7861059
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN99806255A Pending CN1301430A (en) | 1998-03-16 | 1999-03-11 | Circuit for reducing leaking current |
Country Status (8)
| Country | Link |
|---|---|
| EP (1) | EP1064726A1 (en) |
| JP (1) | JP2002507852A (en) |
| KR (1) | KR20010041927A (en) |
| CN (1) | CN1301430A (en) |
| BR (1) | BR9909652A (en) |
| DE (1) | DE19811353C1 (en) |
| RU (1) | RU2000125907A (en) |
| WO (1) | WO1999048208A1 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100340063C (en) * | 2000-09-27 | 2007-09-26 | 株式会社东芝 | Semiconductor integrated circuit |
| CN108028653A (en) * | 2015-07-22 | 2018-05-11 | 辛奥普希斯股份有限公司 | Internet of Things (IoT) electric power and performance management technology and circuit methods |
Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6166985A (en) * | 1999-04-30 | 2000-12-26 | Intel Corporation | Integrated circuit low leakage power circuitry for use with an advanced CMOS process |
| DE10128732C1 (en) * | 2001-06-13 | 2002-05-29 | Infineon Technologies Ag | Current requirement estimation method for gating circuit summates currents for all switched gates in each time interval into which switching process is divided |
| US6515935B1 (en) * | 2001-10-19 | 2003-02-04 | Hewlett-Packard Company | Method and apparatus for reducing average power in memory arrays by switching a diode in or out of the ground path |
| FR2838256A1 (en) * | 2002-04-08 | 2003-10-10 | St Microelectronics Sa | Method for putting in waiting mode a component and associated integrated circuit |
| US6611451B1 (en) * | 2002-06-28 | 2003-08-26 | Texas Instruments Incorporated | Memory array and wordline driver supply voltage differential in standby |
| WO2004075406A1 (en) * | 2003-02-19 | 2004-09-02 | Koninklijke Philips Electronics, N.V. | Leakage power control |
| EP1743422B1 (en) * | 2004-02-19 | 2019-08-07 | Conversant Intellectual Property Management Inc. | Low leakage and data retention circuitry |
| US7227383B2 (en) | 2004-02-19 | 2007-06-05 | Mosaid Delaware, Inc. | Low leakage and data retention circuitry |
| WO2009144661A1 (en) * | 2008-05-27 | 2009-12-03 | Nxp B.V. | Integrated circuit and integrated circuit control method |
| DE102008053533A1 (en) * | 2008-10-28 | 2010-04-29 | Atmel Automotive Gmbh | Circuit, method for controlling and using a circuit for a sleep mode and an operating mode |
| DE102014107545A1 (en) * | 2014-05-28 | 2015-12-03 | Phoenix Contact Gmbh & Co. Kg | POWER SUPPLY UNIT |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5614847A (en) * | 1992-04-14 | 1997-03-25 | Hitachi, Ltd. | Semiconductor integrated circuit device having power reduction mechanism |
| US5596286A (en) * | 1993-11-12 | 1997-01-21 | Texas Instruments Incorporated | Current limiting devices to reduce leakage, photo, or stand-by current in an integrated circuit |
| JP3725911B2 (en) * | 1994-06-02 | 2005-12-14 | 株式会社ルネサステクノロジ | Semiconductor device |
| DE19515417C2 (en) * | 1995-04-26 | 1998-10-15 | Siemens Ag | Circuit arrangement for driving a power MOSFET |
-
1998
- 1998-03-16 DE DE19811353A patent/DE19811353C1/en not_active Expired - Fee Related
-
1999
- 1999-03-11 WO PCT/DE1999/000677 patent/WO1999048208A1/en not_active Application Discontinuation
- 1999-03-11 RU RU2000125907/09A patent/RU2000125907A/en not_active Application Discontinuation
- 1999-03-11 KR KR1020007010235A patent/KR20010041927A/en not_active Application Discontinuation
- 1999-03-11 BR BR9909652-8A patent/BR9909652A/en not_active IP Right Cessation
- 1999-03-11 CN CN99806255A patent/CN1301430A/en active Pending
- 1999-03-11 JP JP2000537311A patent/JP2002507852A/en not_active Withdrawn
- 1999-03-11 EP EP99919067A patent/EP1064726A1/en not_active Withdrawn
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100340063C (en) * | 2000-09-27 | 2007-09-26 | 株式会社东芝 | Semiconductor integrated circuit |
| CN108028653A (en) * | 2015-07-22 | 2018-05-11 | 辛奥普希斯股份有限公司 | Internet of Things (IoT) electric power and performance management technology and circuit methods |
| US11599185B2 (en) * | 2015-07-22 | 2023-03-07 | Synopsys, Inc. | Internet of things (IoT) power and performance management technique and circuit methodology |
Also Published As
| Publication number | Publication date |
|---|---|
| EP1064726A1 (en) | 2001-01-03 |
| KR20010041927A (en) | 2001-05-25 |
| RU2000125907A (en) | 2002-09-10 |
| BR9909652A (en) | 2000-11-21 |
| JP2002507852A (en) | 2002-03-12 |
| DE19811353C1 (en) | 1999-07-22 |
| WO1999048208A1 (en) | 1999-09-23 |
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| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |