WO1999048208A1

WO1999048208A1 - Circuit for reducing leaking current

Info

Publication number: WO1999048208A1
Application number: PCT/DE1999/000677
Authority: WO
Inventors: Jörg BERTHOLD; Martin Eisele; Matthias Eberlein
Original assignee: Infineon Technologies Ag
Priority date: 1998-03-16
Filing date: 1999-03-11
Publication date: 1999-09-23
Also published as: KR20010041927A; RU2000125907A; DE19811353C1; JP2002507852A; CN1301430A; EP1064726A1; BR9909652A

Abstract

The invention relates to a circuit made of parts (2,3) consisting of transistors with a low threshold voltage (NV transistors). In order to reduce leakage current from said circuit parts (2,3), each part is coupled to a supply voltage (VDD, VSS) by means of an intermediate switching transistor (MP1, MN1) with a high threshold voltage (HV transistor) and an NV control transistor (MNH1, MPH1) is connected in parallel to the HV switching transistor (MP1, MN1).

Description

description

Circuit arrangement for reducing the leakage current

The invention relates to a circuit arrangement with circuit parts consisting of transistors of low threshold voltage (NV transistors).

In particular in portable applications, a low current consumption of microelectronic circuit arrangements is desirable, since the service life is correspondingly prolonged for a given battery or accumulator capacity. The current consumption is reduced, for example, by reducing the supply voltage, which, however, leads to reduced switching speeds in the case of MOS transistors. If a high switching speed of the transistors is required in addition to the low current consumption, the threshold voltage of the transistors must be reduced in addition to the supply voltage. With a supply voltage of, for example, 1 volt, threshold voltages of the transistors of typically 0.3 to 0.2 volt (corresponding to a value of a quarter of the supply voltage) are required, compared with 0.6 to approximately 0.4 volt threshold voltage at a supply voltage of 3 , 3 volts. Such low operating voltages, however, lead to greatly increased leakage currents with closed, i.e. uncontrolled transistors, which leads to a load on the battery or the accumulator, particularly in the case of long idle phases ("standby") of the circuit arrangements.

Various measures have been proposed which are intended to allow the static leakage current consumption to be reduced in the idle phases of the circuit arrangement. For example, Shin ^x ichiro Mutoh et al., IEEE International Solid-State Circuits Conference, 1996, p. 168 et seq. Proposed using transistors with multiple threshold voltages in a circuit arrangement, so-called multi-threshold voltage CMOS transistors. Here, the microelectronic circuit arrangement is connected to the supply voltages VDD or VSS via PMOS and / or NMOS transistors with a high threshold voltage. In the active state, these transistors are activated (the gate voltages of VDD and VSS are at the NMOS or PMOS transistor), the local supply lines VDDL and VSSL are thus at VDD or VSS. In standby mode, the transistors are closed (there are gate voltages from VSS and VDD at the NMOS or PMOS transistor), and the current consumption is then reduced to the low leakage currents due to the high threshold voltages of the switching transistors.

However, further precautions must be taken so that circuit parts that store the data retain their information. If the high-voltage switching transistors are closed, the high leakage currents of the NV transistors (transistors of low threshold voltage) of the circuit arrangement lead to an equalization of all voltages within the circuit arrangement after some time, as a result of which the information of the storing elements in the circuit parts is lost. One way to prevent the loss of information is to use transistors with a high threshold voltage in the storing circuit parts. However, this basically requires new circuit designs because of the adaptation of the storing circuit parts.

Another measure to reduce the static leakage current consumption in the idle phase is to pretension the tub and substrate potentials to increase the effective operating voltage. This also under the name "back 3

Biasing "known measure is described for example from Tadahiro Kuroda et al., IEEE International Solid-State Circuits Conference, 1996, p. 166 ff. During the standby phase, the well is increased to voltages above the supply voltage VDD, the substrate potential reduced to values below the supply voltage VSS. This leads to higher threshold voltages of the PMOS or NMOS transistors, with the correspondingly lower leakage currents. However, the disadvantage of this measure is that two additional voltages are required and that regardless of the duration of the standby If the circuit parts are only to be deactivated, only the threshold voltages of the transistors in the wells can be influenced (in the case of n-well processes, these are the PMOS transistors), and the substrate potential is the same for all circuit parts.

From the German patent application DE 195 15 417 AI a circuit arrangement for driving a power MOSFET is known in which a control IC is connected to a supply voltage via a controllable switch in such a way that the control IC is switched via the controllable switch when the power MOSFET is switched off. As a result, the control IC drastically reduces the quiescent current.

The invention has for its object to provide a microelectronic circuit arrangement, in particular for portable applications with a low current consumption, in which, in addition to a low current consumption, a high switching speed of the transistors is guaranteed at the same time, and in which the leakage currents when the transistor is closed are not 4 controlled transistors of the circuit parts and thus the

Load on the battery or accumulator ^{capacity can} in particular be reduced during long periods of rest of the circuit arrangement.

This object is achieved by a circuit arrangement according to claim 1.

According to the invention, the circuit part is coupled to a supply voltage (VDD, VSS) by interposing a switching transistor with a high threshold voltage (HV transistor), an NV control transistor being connected in parallel with the HV switching transistor.

By using transistors with high and low threshold voltages, the invention enables the leakage current of circuits and circuit parts consisting of transistors with low threshold voltages (LV transistors) to be reduced, the solution according to the invention having the following advantages over the previously known measures:

- The preservation of data in the storage elements of the circuit parts is guaranteed without precautions being required in the storage circuit parts, and

- Without multiple supply voltages and / or supply voltage regulations being required.

Switching from the active mode to the standby mode takes place here using digital control signals, the measures according to the invention also being advantageously applicable to the circuit parts themselves.

Further expedient developments of the invention result from the subclaims. The invention is based in the drawing Darge further explained ^¬ imputed embodiments. The schematic diagrams show in detail:

Figure 1A shows a circuit arrangement according to the invention according to a first embodiment;

FIG. 1B shows a schematic curve over time of the supply voltage VDDL of the circuit arrangement according to the first exemplary embodiment;

Figure 2A shows a circuit arrangement according to the invention according to a second embodiment;

FIG. 2B shows a schematic course of the curve over time

Supply voltages VDDL and VSSL of the circuit arrangement according to the second exemplary embodiment;

Figure 3A shows a circuit arrangement according to the invention according to a third embodiment;

FIG. 3B shows a schematic course of the curve over time

Supply voltages VDDL and VSSL of the circuit arrangement according to the third exemplary embodiment;

FIG. 4A shows a circuit arrangement according to the invention in accordance with a fourth exemplary embodiment;

FIG. 4B shows a schematic course of the curve over time

Supply voltages VDDL and VSSL of the circuit arrangement according to the fourth embodiment;

FIG. 5A shows a circuit arrangement according to the invention in accordance with a fifth exemplary embodiment; FIG. 5B shows a schematic course of the curve over time

Supply voltages VDDL and VSSL of the circuit arrangement according to the fifth embodiment; and

FIG. 6 shows a schematic diagram of the PMOS leakage current versus the supply voltage Vds.

In the exemplary embodiments of the invention explained below with reference to the figures, the same reference numbers denote the same circuit components. In the following, transistors with a high threshold voltage (ie threshold voltages Vth from approximately 0.4 V to approximately 0.6 V) are referred to as HV transistors (high Vth transistors), those with a low threshold voltage as NV transistors (enieder- Vth transistors). The exemplary embodiments shown represent schematic example circuits which have been checked on the basis of simulations, the storage circuit parts and the combinatorial circuit parts each being referred to collectively as block circuits which are connected to local supply voltage lines VDDL and / or VSSL. All the transistors in these storing and combinatorial circuit parts combined to form the block mentioned have a low threshold voltage of IowVthn, IowVthp ~ 0.25 volts for MOS or PMOS transistors. HV transistors with the threshold voltages highVthn, highVthp ~ 0.5 volts are used for the switching transistors.

In the case of the VDDL and VSSL voltage curve shown for each exemplary embodiment, the active phase extends to 0.5 μs, after which a stand-by phase begins, which lasts up to 65 μs. This is followed by another active phase. 7 In all of the exemplary embodiments, the following connections are uniformly designated as follows:

1 circuit block 2 storing circuit part

3 combinatorial circuit part

4 data input (datain)

5 clock input (clock)

6 output of the combinatorial circuit part 3 7, 11 high voltage substrate

8, 12 pan tension

9, 13 low voltage substrate

10, 14 substrate tension

15 Data output of the storing circuit part 2 16 Input of the combinatorial circuit part 3

17, 18 control signals, switching transistors

MPl, MN1 switching transistors with high threshold voltage (HV transistors)

MNH1, MPH1 control transistors low threshold voltage (NV control transistors).

In the exemplary embodiment according to FIG. 1A, in the circuit arrangement according to the invention, a V-NMOS transistor MNH1 is connected in parallel to the HV-PMOS switching transistor gate MPl, the gate 19 of which is driven by the global supply voltage VDD. The NV transistor MNH1 thus represents a diode connected in parallel with the HV switching transistor MPl, consisting of an NV transistor MNH1 of opposite polarity. When the circuit arrangement is active, the transistor MP1 is conductive, the local supply voltage line VDDL is at the supply voltage VDD. If the transistor MPl is closed, the potential of VDDL drops in FIG. 1 due to the higher leakage currents of the NV transistors of the circuit parts 2 and 3 (FIG. IB). If the potential of VDDL reaches the value VDD - IowVthn *, the transistor MNH1 begins To conduct electricity. As a result, the potential VDDL is kept at this value, as a result of which the storing circuit parts 2 can hold their data. The value IowVthn * is the threshold voltage of the low voltage transistors which is increased by the substrate control effect, since the substrate is at a lower potential than the source node of the transistor MΝH1.

The reduction of the leakage current results from its dependence on the drain-source voltage. This situation is shown in FIG. 6 on the basis of measurement results, the source-drain voltage Vds being plotted on the right and the PMOS leakage current (threshold voltage Vth = 0.2 V) being plotted on the right. If the source-drain voltage Vds is reduced from 1 volt to 0.5 volt, for example, the leakage current decreases by approximately 70%. This means that the voltage supply does not have to supply the leakage current of block 1 in the operating state (at 1 volt), but only a leakage current reduced to one third. If the drain-source voltage Vds is even lower, a more pronounced reduction is possible.

In the circuit arrangement according to the second exemplary embodiment according to FIG. 2A, in which the well potential is conducted separately from the voltage supply VDDL and is connected to VDD within the circuit arrangement, a further reduction in the leakage current is possible in addition to the Vds dependency. In the active state of the circuit arrangement according to FIG. 2A, the transistors MPl and MΝ1 are conductive, the potential lines VDDL and VSSL are at the potentials VDD and VSS. If the transistor MP1 is closed, the potential of VDDL drops due to the higher leakage current of the NV transistors of block 1 (FIG. 2B). If the potential of VDDL reaches the value VDD - IowVthn *, the transistor MΝH1 begins to conduct current. The same applies to the potential VSSL: If the potential VSS reaches the value VSS + IowVthp * = IowVthp (because of VSS = 0), the transistor MPH1 begins to conduct 9 th. The potentials VDDL and VSSL on this

Values held, whereby storing circuit parts 2 can hold their data. The values IowVthn * and IowVthp * are the threshold voltages of the NV transistors which are increased due to the substrate control effect (well and substrate are at a higher or lower potential than the respective source nodes). Here too, the drain-source voltage for the closed transistors in the circuit parts 2 and 3 is reduced to significantly below VDD, which results in a lower leakage current. At the same time, the effective threshold voltage of the NV transistors in block 1 is increased, since the substrate potential and the well potential remain at VSS and VDD, respectively. This corresponds, however, without an additional voltage source, a pretensioning of the substrate (back-biasing) and trough. The thereby increased threshold voltage leads to a further reduction in the leakage currents of the circuit parts 2 and 3, which is supplied by the voltage supply VDD. Using simulations, the leakage current was reduced to 1/15 compared to 1 volt.

FIG. 3A shows a modified, third exemplary embodiment, in which only one (number word) HV switching transistor MΝ1 with an NV transistor MPH1 connected in parallel as a diode is used in comparison with the second exemplary embodiment explained above. The advantage here is that the area requirement is halved due to the switching transistor MΝ1 and the "diode transistor" MPH1 compared to the aforementioned embodiments. In this case, only in the Ν-channel low-voltage transistors of circuit parts 2 and 3 of block 1 does the threshold voltage increase due to the substrate control effect. In the case of the blocking P-channel NV transistors, the leakage currents are only reduced by the lower drain-source voltage. Using simulations, the leakage current was reduced to 1/10 compared to 1 volt. 3B shows the 10 course of VDDL and VSSL during a standby phase,

In the aforementioned exemplary embodiments, NV transistors of opposite polarity (compared to the HV switching transistors) connected as diodes are used. This leads to the lowering or raising of the potential of VDDL or VSSL by IowVthp * or IowVthn *, the higher threshold voltages of the NV transistors due to the substrate control effect. However, it is also advantageous to connect the HV switching transistors as diodes-connected NV transistors of the same polarity in parallel. This case is shown as the fourth exemplary embodiment of the invention in FIG. 4A. In the circuit arrangement according to FIG. 4A, the potential of VDDL and VSSL is shifted by IowVthp and IowVthn, i.e. the operating voltages of the NV transistors with substrate and well potential of VSS or VDD (no substrate control effect with MΝH1 and MPHl). 4B shows the course of VDDL and VSSL during a standby phase.

In the event that a shift of VDDL and VSSL by

IowVthp or IowVthn as explained in the above embodiment is not sufficient, i.e. The source-drain voltage of the NV transistors in block 1 is still too high, the fifth exemplary embodiment according to FIG. 5A offers the following solution: This is achieved by connecting NV transistors connected in series as diodes (with the same polarity as the HV transistors) Potential of VDDL and VSSL shifted by the corresponding multiple of IowVthp and IowVthn, respectively. In the embodiment according to FIG. 5A, two ΝV transistors MPH1, MPH2 or MΝH1 and MΝH2 are connected in parallel to the switching transistors MPl and MN1. 5B again shows the course of VDDL and VSSL during a standby phase.

Claims

11 claims

1.Circuit arrangement with circuit parts (2, 3) consisting of transistors with a low threshold voltage (NV transistors), in which, in order to reduce the leakage current of the circuit parts (2, 3), the circuit parts by interposing a switching transistor (MPl, MNl) high threshold voltage to a supply voltage (VDD, VSS) are coupled, characterized in that a control transistor (MNHl, MPHl) low threshold voltage is connected in parallel with the switching transistor (MPl, MNl) of high threshold voltage.

2. Circuit arrangement according to claim 1, characterized in that the other supply voltage (VSS, VDD) is also connected to the circuit parts by a control transistor (MPHl, MNHl) of low switching voltage connected in parallel with a switching transistor (MNl, MPl).

3. Circuit arrangement according to claim 1 or 2, characterized g e k e n n z e i c h n e t that the switching transistors (MPl, MNl) high threshold voltage and the control transistors (MNHl, MPHl) low threshold voltage have opposite polarity.

4. Circuit arrangement according to one of claims 1 to 3, characterized in that the circuit parts have an active and a passive ("standby") operating state, and the switching between the two operating states is carried out by digital control signals. 12

5. Circuit arrangement according to one of claims 1 to 4, characterized in that several control transistors of low threshold voltage (MNHl, MNH2, MNP1, MNP2) of the same polarity are connected in parallel to a switching transistor (MPl, MNl) of high threshold voltage.

6. Circuit arrangement according to one of claims 1 to 5, characterized in that the circuit part (2, 3) is formed in a semiconductor substrate, and the semiconductor substrate and all well regions formed in the semiconductor substrate are coupled to the local supply voltages (VSSL or VDDL) (Fig. 1A).

7. Circuit arrangement according to one of claims 1 to 5, characterized in that the circuit part (2, 3) is formed in a semiconductor substrate, and the well regions formed in the semiconductor substrate are coupled to a global supply voltage (VSS or VDD) ( 2A to 5A).