CN1263089C - 制造半导体基质的方法 - Google Patents
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- 238000000034 method Methods 0.000 title claims abstract description 43
- 239000000758 substrate Substances 0.000 title claims abstract description 14
- 239000004065 semiconductor Substances 0.000 title claims description 11
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims abstract description 161
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 44
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 44
- 239000010703 silicon Substances 0.000 claims abstract description 44
- 238000000151 deposition Methods 0.000 claims abstract description 32
- 238000000137 annealing Methods 0.000 claims abstract description 25
- 239000012298 atmosphere Substances 0.000 claims abstract description 14
- 150000002500 ions Chemical class 0.000 claims abstract description 14
- 230000008021 deposition Effects 0.000 claims description 30
- 239000011159 matrix material Substances 0.000 claims description 17
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 16
- 238000004519 manufacturing process Methods 0.000 claims description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 10
- 229910052786 argon Inorganic materials 0.000 claims description 9
- 239000007789 gas Substances 0.000 claims description 9
- 238000002360 preparation method Methods 0.000 claims description 7
- 238000002347 injection Methods 0.000 claims description 6
- 239000007924 injection Substances 0.000 claims description 6
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 4
- 239000001301 oxygen Substances 0.000 claims description 3
- 229910052760 oxygen Inorganic materials 0.000 claims description 3
- 239000001257 hydrogen Substances 0.000 description 19
- 229910052739 hydrogen Inorganic materials 0.000 description 19
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 18
- 239000010408 film Substances 0.000 description 15
- 238000002441 X-ray diffraction Methods 0.000 description 10
- 238000009826 distribution Methods 0.000 description 7
- 239000001307 helium Substances 0.000 description 7
- 229910052734 helium Inorganic materials 0.000 description 7
- 238000005516 engineering process Methods 0.000 description 6
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 6
- 239000011248 coating agent Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 238000002513 implantation Methods 0.000 description 3
- 230000006911 nucleation Effects 0.000 description 3
- 238000010899 nucleation Methods 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 230000002950 deficient Effects 0.000 description 2
- 238000000407 epitaxy Methods 0.000 description 2
- 230000001965 increasing effect Effects 0.000 description 2
- 230000003993 interaction Effects 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 229910008310 Si—Ge Inorganic materials 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 239000012300 argon atmosphere Substances 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 238000004299 exfoliation Methods 0.000 description 1
- -1 helium ion Chemical class 0.000 description 1
- 150000002431 hydrogen Chemical class 0.000 description 1
- 125000004435 hydrogen atom Chemical group [H]* 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000011835 investigation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 238000010008 shearing Methods 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- 230000003746 surface roughness Effects 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
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Abstract
一种制造半导体基质的方法,其包括形成具有相对高的Ge含量的SiGe层的方法,其包括制备硅基质;沉积SiGe层至厚度约100nm-500nm,其中SiGe层的Ge含量以摩尔分数计算等于或者大于22%;以大约1·1016cm-2-5·1016cm-2的剂量和大约20keV-45keV的能量,把H+离子注入到SiGe层;在惰性气氛下,在约650℃-950℃热退火硅基质和SiGe层30秒钟到30分钟,以松弛SiGe层;和在松弛的SiGe层上沉积一层厚度约5nm-30nm的拉应变的硅层。
Description
相关申请
本申请涉及于2000年4月3日提交的、序列号为09/541,255的“在Si上形成厚松弛的SiGe层的方法”,和于2001年2月13日提交的、序列号为09/783,817的“降低Si1-xGexCMOS漏泻电流的方法”。
技术领域
本发明涉及一种制作半导体基质的方法,例如CMOS高速集成电路,并且特别涉及一种制作半导体基质的方法,该方法包括一个使用注氢来形成SiGe层的步骤。
背景技术
在增强迁移率的MOSFET装置的应用中,厚松弛的Si1-xGex缓冲层已经作为实际上的基质被用于薄应变的硅层以既增加nMOS装置的载体迁移率,Welser等.,Strain dependence of the performance enhancement instrained-Si n-MOSFETs,IEDM Conference Proceedings,373页(1994);Rim等.,Fabrication and analysis of Deep submicron strained-Si N-MOSFETs,IEEE Transactions on Electron Devices,47卷,1406,(2000);和Rim等.,Strained Si NMOSFETs for high performance CMOS technology,2001Symposium on VLSI Technology Digest of Technical Papers,59页,IEEE2001;又增加pMOS装置的载体迁移率,Rim等.,Enhanced hole mobilitiesin surface-channel strained-Si p-MOSFETs,IEDM Conference Proceedings,p.517(1995);和Nayak等.,High-mobility Strained-Si PMOSFETs,IEEETransactions on Electron Devices,Vol.43,1709(1996)。Rim等,2001报道了:与块硅装置相比,Leff<70nm的装置的电子迁移率有70%的提高。Nayak等也已经发现:对于长通道装置,高强度电场空穴迁移率有高达40%的提高。
在厚Si1-xGex层中,通过形成错配位错,应变(应力)被塑性地松弛,R.Hull等,Nucleation of misfit dislocations in strained-layer epitaxy in theGexSi1-x/Si system,J.Vac Sci.Technol.,A7,2580,1989;Houghton,Strainrelaxation kinetics in Si1-xGex/Si heterostructures,J.Appl.Phys.,70,2136,1991;Wickenhauser等.,Determination of the activation energy for theheterogeneous nucleation of misfit dislocations in Si1-xGex/Si deposited byselective epitaxy,Appl.phys.Lett.,70,324,1997;Matthews等.,Defects inepitaxial multilayers,J.Cryst.Growth,27,118,1974;和Tang等.,Investigation of dislocations in Si1-xGex/Si heterostructures grown byLPCVD,J.Cryst.Growth,125,301,1992。在这一过程中,常常产生螺纹位错。螺纹位错的存在使装置的性能下降并且明显降低了装置的产率。
制作高质量应力-松弛Si1-xGex缓冲层的技术现状是增长几个μm厚度(等级)的层,其中的组合物沿着厚度方向变化。Rim等.,2000;Nayak等.;Schffler等.,High-electron-mobility Si/SiGe heterostructures:influence ofthe relaxed SiGe buffer layer,Semiconductor.Sci.Technol.,7.260,1992;和Fitzgerald等.,Totally relaxed GexSi1-xlayers with lowthreading dislocationdensities grown on Si substrates,Appl.Phys.Lett.,59,811,1991。但是,螺纹位错的密度依然很高,例如典型地>106cm-2。此外,将几个μm厚度的Si1-xGex层结合到商用装置的制造中是不实际的。同样对增长在注氧隔离(SIMOX)片上的SiGe进行了研究,在这种情况下,Si/SiGe双层表现为游离漂浮的薄片,其被基质限制以保持平坦。但是必须精确地控制硅与SiGe层之间的厚度比率以将成核作用和位错滑移从SiGe层移动到硅层。同样,该技术需要被扩展到包含更高的Ge含量从而对大多数的技术应用有效,LeGouse等.,Relaxation of SiGe thin films grown on Si/SiO2 substrates,J.Appl.Phys.75(11)1994.Powell等.,New approach to the growth of lowdislocation relaxed SiGe material,Appl.Phys.Lett.,vol.64,1856(1994)。
在硅和Ge及其合金中,由注氦和退火形成的空穴被发现与位错之间具有强烈的短期、有吸引力的相互作用。在SiGe/Si界面引入空穴大大地提高了应力松弛率并且改变了位错微结构。但是,没有观察到螺纹位错的密度降低,Follstaedt等.,Cavity-dislocation interactions in Si-Ge andimplications for heterostructure relaxation,Appl.Phys.Lett.,69,2059,1996。为了得到80%的松弛,需要在大约1000℃退火1个小时。
已有报道:注氢引起硅脱落并且引起宏观硅层的剪切,Weldon等,Onthe mechanism of the hydrogen-induced exfoliation of silicon,J.Vac.Sci.Technol.B.15,1065,1997。这被应用于高质量硅-绝缘体(SOI)片的制造,并且被称作SmartCutTM方法。近来德国合作者S.Mantl等和H.Trinkaus等的出版物报道了使用注氢来增加SiGe松弛度和降低螺纹位错密度的优点,S.Mantl等.,Strain relaxation of epitaxial SiGe layers on Si(100)improved by hydrogen implantation,Nuclear Instruments and Methods inPhysics Research B 147,29,(1999),和H.Trinkaus等,Strain relaxationmechanism for hydrogen-implantedSi1-xGex/Si(100)heterostructures,Appl.Phys.Lett.,76,3552,2000。但是,这些研究者报道了厚度仅为2000-2500、以分子量计的Ge浓度小于22%的SiGe层的松弛。这种厚度的SiGe层不足以用于商业装置应用。制作较厚的膜的方法公开在相关申请序列No.09/541,255,而通过适当绝缘来减少漏泻电流的方法被公开在相关申请序列No.09/783,817中。相关申请序列No.09/541,255中描述了带有大约21%Ge的SiGe薄膜的制作。为了增加帽硅通路中的应力并且因而进一步提高电子和空穴迁移率,需要较高的Ge含量。
德国的合作者已经报道:注氦对于制造高度松弛的、具有高达30%的Ge的SiGe层有效,M.Luysberg等.,Relaxation of Si1-xGex buffer layerson Si(100)through Helium implantation,Abstracts of the 2001 MRS SpringMeeting,Abstract P5.4,April 18,2001。在该论文的口述中,特别报道了通过以1·1016cm-2-3·1016cm-2的剂量注入18keV氦离子并且RTA为750℃-1000℃,在100nm厚度、30%Ge含量的SiGe层中得到了80%的应力松弛。演讲者特别陈述了当Ge的含量超过22%的时候,氢灌输不起作用。为了产生光滑的,100nm-500nm厚度、Ge含量超过22%的应力松弛层,据报道注入氦是必需的,注入氢不起作用。
发明内容
根据本发明的一个方面,提供了一种制作半导体基质的方法,其包括形成具有相对高Ge含量的SiGe层的方法,该方法包括:制备硅基质;沉积SiGe层至厚度约100nm-500nm,其中SiGe层的Ge含量以摩尔分数计算等于或者大于22%;以大约1·1016cm-2-5·1016cm-2的剂量,和大约20keV-45keV的能量,将H+离子注入到SiGe层;在惰性气氛下,在650℃-950℃热退火该硅基质和SiGe层30秒钟到30分钟,以松弛SiGe层;在松弛的SiGe层上沉积一层大约5nm-30nm厚度的拉应变的硅层。
在本发明的一个实施方案中,所述的沉积SiGe层包括在温度大约400℃-600℃沉积SiGe层。
在本发明的另一个实施方案中,该方法还包括在所述的注入前,在SiGe层上沉积一层厚度为大约50-300的氧化硅。
在本发明的另一个实施方案中,该方法还包括在所述的热退火之后,在松弛的SiGe层上沉积一层厚度为大约100nm的松弛的SiGe层。
在本发明的另一个实施方案中,所述的热退火在氩氛围下进行。
根据本发明的另一方面,提供了一种制作半导体基质的方法,其包括形成具有相对高Ge含量的SiGe层的方法,该方法包括:制备硅基质,其中的硅基质来自由块硅和SIMOX组成的基质组;沉积SiGe层至厚度约100nm-500nm,其中SiGe层的Ge含量以摩尔分数计算等于或者大于25%,而且所述的沉积在大约400℃-600℃的温度范围内进行;以大约1·1016cm-2-5·1016cm-2的剂量,和大约20keV-45keV的能量,将H+离子注入到SiGe层;在氩气气氛下,在约650℃-950℃热退火该硅基质和SiGe层约30秒钟到30分钟,以松弛SiGe层;在松弛的SiGe层上沉积一层大约5nm-30nm厚度的拉应变的硅层。
在本发明的一个实施方案中,该方法还包括在所述的注入前,在SiGe层上沉积一层厚度为大约50-300的氧化硅。
在本发明的另一个实施方案中,该方法还包括在所述的热退火之后,如果松弛的SiGe层的厚度小于300nm,那么在松弛的SiGe层上沉积一层厚度为大约100nm的松弛的SiGe层。
根据本发明的另一方面,提供了一种制作半导体基质的方法,其包括形成具有相对高Ge含量的SiGe层的方法,该方法包括:制备硅基质;沉积SiGe层至厚度约100nm-500nm,其中SiGe层的Ge含量以摩尔分数计算等于或者大于22%,而且所述的沉积在大约400℃-600℃的温度范围内进行;以大约1·1016cm-2-5·1016cm-2的剂量和大约20keV-45keV的能量,把H+离子注入到SiGe层;在惰性氛围下,在约650℃-950℃热退火该硅基质和SiGe层30秒钟到30分钟,以将SiGe层松驰到至少70%松弛;并且在松弛的SiGe层上沉积一层大约5nm-30nm厚度的拉应变的硅层。
在本发明的一个实施方案中,该方法还包括在所述的注入前,在SiGe层上沉积一层厚度为大约50-300的氧化硅。
在本发明的另一个实施方案中,所述的热退火在氩气气氛下进行。
在本发明的另一个实施方案中,该方法还包括在所述的热退火之后,在松弛的SiGe层上沉积一层厚度为大约100nm的松弛的SiGe层。
在本发明的另一个实施方案中,只有在松弛的SiGe层的厚度小于300nm的时候,才在松弛的SiGe层上沉积一层厚度为大约100nm的松弛的SiGe层。
本发明的目的是采用注入氢来生产一种厚的例如100nm-500nm的应力-松弛的、光滑的、具有高Ge含量(>22%(摩尔分数))的SiGe层(膜),该层作为张力应变的硅膜缓冲层用于高速MOSFET应用。
为了能够使得快速理解本发明的性质,在此提供了本发明的概述和发明目的。通过参考下面对本发明优选实施方案的详细描述和附图,可以对本发明有更彻底的理解。
附图说明
图1-5描述了本发明的SiGe沉积方法。
图6描述了在注入氢和热松弛以后,厚度为200nm-220nm的、具有Ge浓度为大约28-30%的SiGe膜的Nomarski显微图象。
图7描述了图6的SiGe膜的X射线衍射。
图8描述了在注入氢和退火以后,厚度为300nm的、带有分级Ge分布的SiGe膜的400X的Nomarski显微图象。
图9描述了在注入氢和退火以后,厚度为300nm的、带有分级Ge分布的SiGe膜的1000X的Nomarski显微图象。
图10描述了图8和图9的SiGe层的X射线衍射。
图11描述了厚度为300nm、用分级分布制作的SiGe层的Nomarski显微图象。
图12描述了图11的300nm厚度的SiGe层的1000X的X射线衍射。
具体实施方式
本发明证实:与现有技术的教导相反,注入氢对于生产高应变-松弛(应力松弛)的、具有等于或者大于22%Ge含量的SiGe膜非常有效。此处描述的技术在Ge浓度大于22%(摩尔分数)的SiGe层上进行,但是,没有指出使用本发明方法的Ge浓度的上限。此外,对于商业装置应用,注入氢比注入氦优选,这是因为氦不能够钝化缺陷,而众所周知氢能够钝化缺陷。本发明的方法采用注入氢的方法来产生厚的例如100nm-500nm的应力-松弛的、光滑的、具有高Ge含量(>22%(摩尔分数))和具有低螺纹位错密度的SiGe层。
对本发明方法的描述从图1开始。制备硅基质10,它可以是块硅或者注氧隔离(SIMOX)。在硅基质10上沉积一层具有约100nm-500nm厚度的应变的SiGe层12。应变SiGe层12的Ge含量以原子比(摩尔分数)计算可以是22%或者更高。本发明方法的优选实施方案产生了Ge浓度为大约30%的SiGe层12。或者,可以使用分级的Ge分布,即:可以使用SiGe层12,其中Ge浓度沿着厚度方向变化以使SiGe层12中更高的等级具有更高的Ge浓度。应该对生长条件和源气体进行选择以将表面粗糙度最小化而同时保证良好的结晶度。这通常意味着低温度如400℃-600℃的生长以产生亚稳定的,应变的SiGe膜。
再看图2,H+离子被注入。H+的剂量范围为大约1·1016cm-2-5·1016cm-2。能量水平依赖于SiGe的厚度,但是典型范围为大约20keV-45keV。为了避免在注入步骤中的污染,可以在SiGe层12上沉积一个薄的牺牲氧化硅层,厚度范围为大约50-300(5nm-30nm)。
图3描述了热退火步骤,其将应变的SiGe层12转变为第一应变-松弛(应力-松弛)SiGe层14。退火在惰性环境氛围例如Ar下、在温度约650℃-950℃的范围内进行30秒钟-30分钟。
如果需要,任选地,在松弛的SiGe层14上沉积一个厚度为大约100nm或者更高的应变-松弛SiGe的第二SiGe层16。确定该任选层是否为必要的标准,是松弛的SiGe层14的厚度。如果SiGe层14的厚度小于300nm,则需要附加的应变-松弛SiGe层16以将最终整个SiGe松弛层的厚度增加到至少300nm。
本发明方法的最后步骤被描述在图5中,其中的厚度为大约5nm-30nm的拉应变的硅层18被沉积在松弛的SiGe层14上或者第二SiGe层16上。
图6,7和8-10描述了在注入氢和热松弛之后,厚度为200nm-220nm、以摩尔分数计算Ge含量为25%-30%的SiGe膜。图6描述了在注入氢和热松弛以后,厚度为200nm-220nm的、Ge浓度为大约28-30%的SiGe层的Nomarski显微图象。图7描述了图6的SiGe层的X射线衍射。图8描述了在注入氢和退火以后,厚度为300nm的、带有分级Ge分布的SiGe膜的400X的Nomarski显微图象,其中的组成沿着厚度方向变化。图9描述了在注入氢和退火以后,厚度为300nm的、带有分级Ge分布的SiGe膜的1000X的Nomarski显微图象。图10描述了图8和图9的SiGe层的X射线衍射。
Nomarski显微图象,图6,8和9,描述了一个非常平的表面形态。图7和10描述了X射线衍射的倒晶格空间图,其证实了晶格是高度应变-松弛的,至少70%-85%。在图7中,硅(224)峰和SiGe(224)峰之间的偏移表明了这种松弛状态,如虚线所示。
图11描述了在注入氢和退火之后,厚度为大约300nm、伴随分级Ge分布的SiGe膜的Nomarski显微图象。图12描述了图11的SiGe层的X射线衍射。从硅基质中的21%到表面的30%,Ge含量近似线性地变化。分级Ge分布的使用,促进了SiGe层厚度的增加而且还提供了带有光滑表面的高度应变-松弛的SiGe层。该SiGe层的厚度很厚,通常足以不需要第二SiGe沉积,因此提高了整体SiGe层的质量。
根据本发明方法所构建的所有的应变-松弛SiGe层,都可以被用作拉应变的硅膜生长的基质。这些可以随后被用于制作具有增强的空穴和电子迁移率的nMOS和pMOS晶体管。图6和7的SiGe薄膜具有的Ge浓度为28.6%。它的厚度大约为200nm,而且是用能量为大约25keV和离子剂量为大约3·1016cm-2的H+离子注入制造的。在氩气气氛下,在RTA室中,将晶片在大约800℃退火10分钟。Nomarski显微图象是在1000X,其描述出了一个相当光滑的表面。图7的X射线衍射倒晶格空间图显示了一个大的中央峰,这是硅(-2-24)基质峰。下面的和右边的较小的峰来自部分松弛的SiGe层。从这两个峰的相对位置来看,SiGe层有28.2%±0.5%的Ge,而且是75.8%±3%应力松弛的。
图8,9,10描述了高度应力松弛例如大约85%的、具有大约30%Ge浓度的、光滑的第一SiGe层。该实例在SiGe层中具有的Ge浓度是大约30%,此SiGe层的厚度为大约220nm。大约20nm厚度的SiO2帽由PECVD形成。在大约26keV的能量进行H+离子注入,离子的剂量为大约3·1016cm-2。在氩气气氛下,在RTA室中,将晶片在大约800℃退火9分钟。图9描述了在400X,在晶片中心拍摄的Nomarski显微图象。图9是在1000X,也是在晶片的中心拍摄的相同晶片的Nomarski显微图象。图10描述了该晶片的X射线衍射,其证实了SiGe膜具有浓度为29.7%±0.5%的Ge,而且是85.2%±3%应力松弛的。
图11和12描述了一个高度松弛的、带有光滑表面的分级Ge样品。图11是一个高度松弛例如大约82%的、光滑的第一SiGe层的Nomarski显微图象,它是在1000X、在晶片中心拍摄的。图12描述了图11的晶片的X射线衍射。该SiGe层的厚度为大约301nm,其具有大约21%-30%生长状态的Ge分级分布。在大约32keV的能量水平进行H+离子注入,离子的剂量为大约2·1016cm-2。在氩气气氛下,在RTA室中,将晶片在大约800℃退火约9分钟。该SiGe层有27.8%±0.5%的Ge,而且是82.2%±3%应力松弛的。
备选实施方案
本发明的方法可以通过以下方式被修改:用表面Ge含量超过22%的分级Ge分布增长超过300nm厚度的SiGe层+H-II+RTA(以松弛SiGe层应力)+张力表-硅帽/通路。这不需要第二SiGe层的沉积。
本发明方法的另一个实施方案包括使用或者恒定的或者分级的Ge分布增长第一SiGe层+H-II+RTA(以松弛SiGe层的应力)+表面Ge含量超过22%的或者恒定的或者分级的Ge分布的第二SiGe层+张力表-硅帽/通路。在本发明方法的此实施方案中,整个SiGe层的厚度应该是300nm或者更高。
这样,本发明公开了形成具有高Ge浓度的松弛SiGe层的方法。应该注意到,在附加权利要求中所定义的本发明的范围内,该方法可以被进一步的变更和修改。
Claims (13)
1、一种制造半导体基质的方法,其包括形成具有相对高的Ge含量的SiGe层的步骤,包括:
制备硅基质;
沉积SiGe层至厚度为约100nm-500nm,其中SiGe层的Ge含量以摩尔分数计算等于或者大于22%;
以大约1·1016cm-2-5·1016cm-2的剂量和大约20keV-45keV的能量,把H+离子注入到SiGe层;
在惰性气氛下,在约650℃-950℃热退火硅基质和SiGe层约30秒钟到30分钟,以松弛SiGe层;和
在松弛的SiGe层上沉积一层厚度约5nm-30nm的拉应变的硅层。
2、根据权利要求1的方法,其中所述的沉积SiGe层包括在温度大约400℃-600℃之间沉积SiGe层。
3、根据权利要求1的方法,其还包括在所述的注入前,在SiGe层上沉积一层厚度为大约50-300的氧化硅层。
4、根据权利要求1的方法,其还包括在所述的热退火之后,在松弛的SiGe层上沉积一层厚度为大约100nm的松弛的SiGe层。
5、根据权利要求1的方法,其中所述的热退火在氩气气氛下进行。
6、一种制造半导体基质的方法,其包括形成具有相对高的Ge含量的SiGe层的步骤,包括:
制备硅基质,其中的硅基质来自由块硅和注氧隔离片组成的基质组;
沉积SiGe层至厚度为约100nm-500nm,其中SiGe层的Ge含量以摩尔分数计算等于或者大于25%,而且所述的沉积在大约400℃-600℃的温度范围内进行;
以大约1·1016cm-2-5·1016cm-2的剂量,和大约20keV-45keV的能量,将H+离子注入到SiGe层;
在氩气气氛下,在约650℃-950℃热退火硅基质和SiGe层30秒钟到30分钟,以松弛SiGe层;和
在松弛的SiGe层上沉积一层厚度约5nm-30nm厚度的拉应变的硅层。
7、根据权利要求6的方法,其还包括在所述的注入前,在SiGe层上沉积一层厚度为大约50-300的氧化硅层。
8、根据权利要求6的方法,其还包括在所述的热退火之后,如果松弛的SiGe层的厚度小于300nm,那么在松弛的SiGe层上沉积一层厚度为大约100nm的松弛的SiGe层。
9、一种制造半导体基质的方法,其包括形成具有相对高的Ge含量的SiGe层的步骤,包括:
制备硅基质;
沉积SiGe层至厚度约100nm-500nm,其中SiGe层的Ge含量以摩尔分数计算等于或者大于22%,而且所述的沉积在大约400℃-600℃的温度范围内进行;
以大约1·1016cm-2-5·1016cm-2的剂量和大约20keV-45keV的能量,把H+离子注入到SiGe层;
在惰性气氛下,在约650℃-950℃热退火该硅基质和SiGe层30秒钟到30分钟,以将SiGe层松驰到至少70%松弛;和
在松弛的SiGe层上沉积一层厚度约5nm-30nm的拉应变的硅层。
10、根据权利要求9的方法,其还包括在所述的注入前,在SiGe层上沉积-层厚度为大约50-300的氧化硅层。
11、根据权利要求9的方法,其中所述的热退火在氩气气氛下进行。
12、根据权利要求9的方法,其还包括在所述的热退火之后,在松弛的SiGe层上沉积一层厚度为大约100nm的松弛的SiGe层。
13、根据权利要求12的方法,其中只有在松弛的SiGe层的厚度小于300nm的时候,才在松弛的SiGe层上沉积一层厚度为大约100nm的松弛的SiGe层。
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US6562703B1 (en) * | 2002-03-13 | 2003-05-13 | Sharp Laboratories Of America, Inc. | Molecular hydrogen implantation method for forming a relaxed silicon germanium layer with high germanium content |
US6841457B2 (en) * | 2002-07-16 | 2005-01-11 | International Business Machines Corporation | Use of hydrogen implantation to improve material properties of silicon-germanium-on-insulator material made by thermal diffusion |
US6699764B1 (en) * | 2002-09-09 | 2004-03-02 | Sharp Laboratories Of America, Inc. | Method for amorphization re-crystallization of Si1-xGex films on silicon substrates |
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2002
- 2002-01-31 US US10/062,319 patent/US6746902B2/en not_active Expired - Lifetime
- 2002-12-04 JP JP2002353127A patent/JP4386333B2/ja not_active Expired - Fee Related
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2003
- 2003-01-28 TW TW092101846A patent/TW580726B/zh not_active IP Right Cessation
- 2003-01-30 KR KR10-2003-0006093A patent/KR100521708B1/ko not_active IP Right Cessation
- 2003-01-30 CN CNB031034594A patent/CN1263089C/zh not_active Expired - Fee Related
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Also Published As
Publication number | Publication date |
---|---|
JP2003229360A (ja) | 2003-08-15 |
TW580726B (en) | 2004-03-21 |
US6746902B2 (en) | 2004-06-08 |
JP4386333B2 (ja) | 2009-12-16 |
US20040087119A1 (en) | 2004-05-06 |
KR100521708B1 (ko) | 2005-10-14 |
US20030143783A1 (en) | 2003-07-31 |
TW200302512A (en) | 2003-08-01 |
CN1435862A (zh) | 2003-08-13 |
US6780796B2 (en) | 2004-08-24 |
KR20030066387A (ko) | 2003-08-09 |
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