CN1245755C - 薄膜基板、半导体器件、电路基板及其制造方法 - Google Patents
薄膜基板、半导体器件、电路基板及其制造方法 Download PDFInfo
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Abstract
一种薄膜基板,具备:在将来要分离的区域的外周线上边具有切缝部分,装载半导体器件芯片的绝缘性薄片;在上述绝缘性薄片上边形成,横穿上述切缝部分,连接到上述半导体器件芯片的外部端子上的导电性图形。
Description
技术领域
本发明涉及预定要装载半导体器件芯片的薄膜基板、半导体器件、薄膜的制造方法、半导体器件的制造方法和带半导体器件的电路基板的制造方法。
背景技术
参看图18A和图18B到图22A以及图22B,对把半导体器件芯片装载到已形成了导电性图形的绝缘性薄膜上边的现有方法的一个例子进行说明。
图18A是示出了半导体器件芯片1(半导体集成电路器件芯片等)的外观的斜视图,图18B是沿图18A的B-B线的剖面图。在半导体器件芯片1的表面上,作为外部端子(# external terminal #)形成有多个柱状突点2。
图19A的平面图示出了已形成了导电性图形(布线图形(# wiringpattern #))4的带状绝缘性薄膜3,图19B是沿图19A的B-B线的剖面图。图19A和图19B所示的构造,可以采用借助于光刻和刻蚀,使已用粘接剂5粘贴到绝缘性薄膜3(厚度25到75微米左右)上边的导电性金属箔(例如,厚度35微米左右的铜箔或铝箔)图形化的办法得到。
其次,如图20A和图20B所示,把各向异性导电树脂(# anisotropicconductive resin #)6粘贴到上述这样地得到的带导电性图形的绝缘性薄膜3表面的芯片装载区域上。然后,如图21A和图21B所示,借助于倒装芯片方式,把半导体器件芯片1装载到各向异性导电性树脂6上边。这样就可以得到带状薄膜基板(# substrate #)。
之后,如图22A所示,用冲压装置等从带状薄膜基板上分离出规定的形状。借助于此,如图22B所示,就可以得到薄膜基板。
象这样地得到的薄膜基板,经以下那样地处理后就被装配到PCB(印刷电路基板)或FPC(柔性印刷电路基板)等的电路基板(# Circuit Board)上。
首先,如图23A和图23B所示,把导电性粘接剂10粘贴到已形成了无源元件(# passive element #)7和连接端子9等的电路基板8上边。作为导电性粘接剂10可以使用各向异性导电树脂。
接着,如图24所示,用吸附(# adsorption #)工具11把在图22A和图2B的工序中得到的薄膜基板片装载到电路基板8上边,用导电性粘接剂把的薄膜基板片上形成的导电性图形4和在电路基板8上形成的连接端子9连接起来。在进行连接时,用热压接合(# thermocompression bonding #)工具12进行热压接合(200℃,约20秒)。
但是,若用上述的方法,由于要把薄膜基板片从带状薄膜基板分离出来,并把分离出来的薄膜基板片装载到电路基板上,故存在着以下那样的问题。
就是说,由于必须一个一个地处理薄膜基板片,故薄膜基板片的处理是困难的。为此要进行由自动化进行的生产性的提高是困难的。此外,当薄膜基板片的尺寸减小时,就不能同时设置吸附工具11和热压接合工具12。为此,如图25A和图25B所示,就必须进行2个步骤的工序,招致工序的增加。此外,如图26所示,还存在着导电性粘接剂10从薄膜基板片的周缘部分往上爬,例如附着到热压接合工具12上的可能性。为防止这种可能,就必须增大薄膜基板片,这与小型化的要求是背道而驰的。
如上所述,在现有技术的情况下,由于在从带状薄膜基板上分离出薄膜基板片之后必须把薄膜基板片装载到电路基板上边,故存在着难于处理、难于小型化、生产性恶化等的问题。
另一方面,在特开平3-84955号公报和特开平6-53288号公报中,公开了预先在已装载上半导体器件芯片的带状薄膜基板上形成切缝(# slit #)的技术。在切缝的内侧的区域上设置有半导体器件芯片和已连接到半导体器件芯片上的导电性图形。归因于预先形成好切缝,从带状薄膜基板上分离薄膜基板就变得容易了起来。
但是,在这些现有技术公开的方法中,切缝内侧的区域和切缝外侧的区域,仅仅用相邻的切缝间的部分进行连接。就是说,在分离之前,切缝的内侧的区域仅仅借助于切缝间的部分进行保持。因此,存在着切缝的内侧的区域的保持强度弱,难于进行带状薄膜基板的处理的问题。
发明的概述
本发明的的第1方面是一种薄膜基板,具备:在将来要分离的区域的外周线上边具有切缝部分,装载半导体器件芯片的绝缘性薄片;在上述绝缘性薄片上边形成,横穿上述切缝部分,连接到上述半导体器件芯片的外部端子上的导电性图形。
本发明的第2方面是一种半导体器件,具备:在将来要分离的区域的外周上边具有切缝部分的绝缘性薄片;在上述绝缘性薄片上边形成,横穿上述切缝部分的导电性图形;装载到上述绝缘性薄片上边,并具有已电连接到上述导电性图形上的外部端子的半导体器件芯片。
本发明的第3方面是一种薄膜基板的制造方法,具备:准备要装载半导体器件芯片的绝缘性薄片的工序;在上述绝缘性薄片的将来要分离的区域的外周线上边形成切缝部分的工序;在上述绝缘性薄片上边,形成横穿上述切缝部分,连接到上述半导体器件芯片的外部端子上的导电性图形的工序。
本发明的第4方面是一种半导体器件的制造方法,具备:准备要装载半导体器件芯片的绝缘性薄片的工序;在上述绝缘性薄片的将来要分离的区域的外周线上边形成切缝部分的工序;在上述绝缘性薄片上边,形成横穿上述切缝部分的导电性图形的工序;把半导体器件芯片装载到上述绝缘性薄片上边,把上述半导体器件芯片的外部端子电连接到上述导电性图形上的工序。
本发明的第5方面是一种带半导体器件的电路基板的制造方法,具备:准备要装载半导体器件芯片的绝缘性薄片的工序;在上述绝缘性薄片的将来要分离的第1区域的外周线上边形成切缝部分的工序;在上述绝缘性薄片上边,形成横穿上述切缝部分的导电性图形的工序;把半导体器件芯片装载到上述绝缘性薄片上边,把上述半导体器件芯片的外部端子电连接到上述导电性图形上的工序;把已装载上述半导体器件芯片的绝缘性薄片的上述第1区域的至少一部分粘接到电路基板上的工序;从第1区域分离上述第1区域的外侧的第2区域,在上述电路基板上边剩下上述第1区域的工序。
附图的简单说明
图1A和图1B是用来说明本发明的实施形态的制造方法的说明图。
图2A到图2C是用来说明本发明的实施形态的制造方法的说明图。
图3A和图3B是用来说明本发明的实施形态的制造方法的说明图。
图4A和图4B是用来说明本发明的实施形态的制造方法的说明图。
图5A和图5B是用来说明本发明的实施形态的制造方法的说明图。
图6A和图6B是用来说明本发明的实施形态的制造方法的说明图。
图7A和图7B是用来说明本发明的实施形态的制造方法的说明图。
图8是用来说明本发明的实施形态的制造方法的说明图。
图9是用来说明本发明的实施形态的制造方法的说明图。
图10是用来说明本发明的实施形态的制造方法的说明图。
图11是用来说明本发明的实施形态的制造方法的说明图。
图12是用来说明本发明的实施形态的制造方法的说明图。
图13A和图13B是用来说明本发明的实施形态的制造方法的说明图。
图14A到图14D是用来说明本发明的实施形态的变更例的说明图。
图15A和图15B是用来说明本发明的实施形态的另外的变更例的说明图。
图16A和图16B是用来说明本发明的实施形态的另外的变更例的说明图。
图17A和图17B是用来说明本发明的实施形态的另外的变更例的说明图。
图18A和图18B是用来说明现有技术的制造方法的说明图。
图19A和图19B是用来说明现有技术的制造方法的说明图。
图20A和图20B是用来说明现有技术的制造方法的说明图。
图21A和图21B是用来说明现有技术的制造方法的说明图。
图22A和图22B是用来说明现有技术的制造方法的说明图。
图23A和图23B是用来说明现有技术的制造方法的说明图。
图24是用来说明现有技术的制造方法的说明图。
图25A和图25B是用来说明现有技术的问题的说明图。
图26是用来说明现有技术的问题的说明图。
发明的详细说明
以下,参看附图说明本发明的实施形态。
首先,参照图1A和图1B~图13A和图13B,说明本发明实施形态的制造方法例。
首先,如图1A和图1B所示,用金属刀片(例如,汤姆森刀片)在聚酰亚胺或PET(聚对苯二甲酸酯)等的带状绝缘性薄膜(相当于绝缘性薄片)3上形成贯通绝缘性薄膜3的切缝。
图2A是这样地形成了切缝15的绝缘性薄膜3的平面图,图2B是沿图2A中B-B的剖面图,图2C是图2A的虚线内的放大图。切缝15,如图2A所示,沿着预定将来要分离的区域(假定是最终所需要的目的区域)的外周线,(与外周线对应地)部分地形成。就是说,切缝15并不是在整个预定分离区域的外周线上边形成,在那些与外周线对应的部分之内,也存在着未形成切缝15的部分。该切缝15是为了在后边的工序中分离切缝15的内侧部分的切缝。切缝15的内侧部分,为了使之在分离工序中易于分离,而且在分离工序之前不会剥落下来,切缝15的长度,理想的是相对于整个外周线的长度来说在70%以上而且不到100%(理想地说为99%以下)。此外,在图示的例子中,虽然有4个未形成切缝的地方,但是该地方应设置1个地方以上,理想地说,应设置2个地方以上。
另一方面,如图3A和图3B所示,准备用来在绝缘性薄膜3上边形成导电性图形(布线图形)的导电性金属箔14,向该金属箔14上边涂敷粘接剂5。金属箔14例如可以使用铜箔或铝箔。此外,粘接剂5,例如可以使用东レ生产的#7100或巴川制纸制的X等。
然后,如图4A和图4B所示,用粘接剂5把具有切缝15的绝缘性薄膜3和金属箔14粘贴起来。
其次,如图5A和图5B所示,借助于先刻和刻蚀使金属箔14图形化,形成导电性图形(布线图形)4。在作为金属箔14使用铜箔或铝箔的情况下,可以用氯化铁等的溶液进行刻蚀。这时,导电性图形4被形成为横穿切缝15。这样一来,就可以得到在具有切缝15的绝缘性薄膜3上边形成了导电性图形4的带状的薄膜基板。
其次,如图6A和图6B所示,把具有粘接性的各向异性导电性树脂6粘贴到已形成了导电性图形4的绝缘性薄膜3表面的芯片装载区域上。然后,用倒装芯片方式,把半导体器件芯片1装载到各向异性导电性树脂6上边。半导体器件芯片1是与例如图18A和图18B所示的芯片同样的芯片,作为外部端子在背面一侧形成了多个柱状突点。各个柱状突点通过各向异性导电性树脂6连接到对应的导电性图形4上。
如上所述,就可以得到已装载上半导体器件芯片的带状薄膜基板。这样的带状薄膜基板可以以卷线筒或滚筒的状态连续地进行制造,可以连续地形成图6A所示的单位构造(用虚线围起来的部分)。
其次,用这样地得到的带状薄膜基板,如下所述那样地把薄膜基板装配到PCB或FPC等的电路基板上。
首先,如图7A和图7B所示,准备已形成了无源元件7和连接端子9等的电路基板8,把导电性粘接剂10粘贴到已形成了连接端子9的区域上边。作为导电性粘接剂10,可以使用各向异性导电性树脂(例如,日立化成生产的FC-262B)等。
接着,如图8所示,将图6A及图6B所示的搭载有半导体器件芯片的带状薄膜基板装在如图7A及图7B所示的电路基板8上。然后,使用导电性粘接剂10,把在带状薄膜基板上形成的导电性图形连接到电路基板8上形成的连接端子9上。
具体地说,如图9所示,在进行了以滚筒16和17保持的装载有半导体器件芯片的带状薄膜基板和电路基板8之间的定位后,把带状薄膜基板连接到电路基板8上。在进行连接时,用热压接合工具12进行(200℃,约20秒)。借助于此,设置在半导体器件芯片1上的各个柱状突点2(外部端子),就可以通过对应的导电性图形5与在电路基板8上形成的对应的连接端子9进行电连接。另外,在图9中,为了节约纸面而省略未画出粘接剂5和导电性粘接剂10,但是由图5A和图5B到图7A和图7B等可知,实际上也形成了它们(以后的图也如此)。图10示出了把已装载有半导体器件芯片的带状薄膜基板和电路基板8连接起来后的状态。
接着,如图11所示,使滚筒16和17向上方移动,把带状薄膜基板往上拉。这时,由于带状薄膜基板上已形成了切缝15,故仅仅切缝的内侧部分作为薄膜基板片被分离开来,残存于电路基板8上边。除此之外的部分则变成为图12所示的形状被切离。
这样一来,如图13A和图13B所示,可以得到已装载上半导体器件芯片1的薄膜基板的电路基板。
然后,用一方的滚筒(例如滚筒17),把带状薄膜基板仅仅卷绕图6A所示的一个单位构造的量。就是说,在图11的工序之后,使带状薄膜基板仅仅移动1个单位构造的量。然后,采用进行与上边所说的工序同样的工序的办法,把薄膜基板片装载到别的电路基板上边。以后,采用反复进行同样的工序的办法,就可以依次把各个薄膜基板片装载到各个电路基板上边。
如上所述,倘采用本实施形态,由于在绝缘薄膜上已预先形成有切缝15,故可以在已把带状薄膜基板连接到电路基板8上的状态下容易地使薄膜基板片进行分离。因此,不必使每个薄膜基板片分离开来就可以对带状薄膜基板进行处理,就可以实现由自动化进行的生产性的提高。此外,由于可以防止在现有技术中所述的那些问题,就是说不能同时设置吸附工具和热压接合工具的问题(参看图26)、导电性粘接剂从薄膜基板片的周缘部分爬上来的问题,故可以把薄膜基板片形成得小。此外,由于把导电性图形形成为使之横穿切缝15(参看图5A和图5B,图6A和图6B),故一直到最终把薄膜基板片分离开来为止都可以确实地保持薄膜基板片。因此,使得带状薄膜基板的处理变得容易起来。
另外,在本实施形态中,如下所述,可以进行种种的变形予以实施。
图14A到图14D示出了对于切缝15的形状的种种的变形。在采用这些切缝形状的情况下,也可以得到与上边所说的效果同样的效果。
图15A和图15B示出了对于导电性图形4的形状的种种的变形。在本例中,如图15B(图15A的虚线内的放大图)所示,导电性图形4的线宽在横穿切缝15的部分处变窄。归因于采用这样的构成,就可以确实且容易地分离薄膜基板片。
图16A和图16B是在绝缘薄片上边形成与导电性图形4不同的另外的附加性的导电性图形18的图。导电性图形18也被形成为使之横穿切缝15。该导电性图形18,在导电性图形4的图形化工序中同时进行图形化。但是,导电性图形18与半导体器件芯片的外部端子(柱状突点)是电隔离的。如上所述,归因于形成附加性的导电性图形18,一直到最终分离薄膜基板片为止,都可以确实地保持薄膜基板片。
图17A和图17B示出了导电性图形4和与之对应的切缝15的图形的例子。图17A是导电性图形4在3个方向上配置的例子。图17B是下侧的导电性图形4条数比上侧的导电性图形4还多,密度也高的情况下的例子。不论哪一个例子,与上边所说的实施形态的情况下(参看图5A和图5B等)比较,虽然起因于导电性图形4的配置形状而使得切缝15的图形变得复杂起来,但是,即便是在这样的情况下,仍可以收到与上边所说的实施形态同样的效果。
对于那些本专业的熟练的技术人员来说还存在着另外一些优点和变形。因此,本发明就其更为广阔的形态来说并不限于上述附图和说明。此外,就如所附权利要求及其等效要求所限定的那样,还可以有许多变形而不偏离总的发明的宗旨。
Claims (13)
1.一种薄膜基板,具备:具有分离用切缝,在上述分离用切缝内侧装载有半导体器件芯片的绝缘性薄片;
在上述绝缘性薄片上边形成,横穿上述分离用切缝,连接到上述半导体器件芯片的外部端子上的导电性图形。
2.根据权利要求1所述的薄膜基板,上述导电性图形的宽度,在横穿上述分离用切缝的部分处变窄。
3.根据权利要求1所述的薄膜基板,还具备在上述绝缘性薄片上边形成,横穿上述分离用切缝、不连接到上述半导体器件芯片的外部端子上的导电性图形。
4.一种半导体器件,具备:具有分离用切缝,在上述分离用切缝内侧装载有半导体器件芯片的绝缘性薄片;在上述绝缘性薄片上边形成,电连接到上述半导体器件芯片的外部端子上,横穿上述分离用切缝地配置的导电性图形。
5.根据权利要求4所述的半导体器件,上述导电性图形的宽度,在横穿上述分离用切缝的部分处变窄。
6.根据权利要求4所述的半导体器件,还具备在上述绝缘性薄片上边形成,横穿上述分离用切缝、不连接到上述半导体器件芯片的外部端子上的导电性图形。
7.一种薄膜基板的制造方法,具备:
准备要装载半导体器件芯片的绝缘性薄片的工序;
在上述绝缘性薄片的上述半导体器件芯片的外侧上边形成分离用切缝的工序;
在上述绝缘性薄片上边,形成横穿上述分离用切缝,连接到上述半导体器件芯片的外部端子上的导电性图形的工序。
8.根据权利要求7所述的薄膜基板的制造方法,上述导电性图形的宽度,在横穿上述分离用切缝的部分处变窄。
9.根据权利要求7所述的薄膜基板的制造方法,上述形成导电性图形的工序,还包括在上述绝缘性薄片上边形成,横穿上述分离用切缝、不连接到上述半导体器件芯片的外部端子上的附加的导电性图形的工序。
10.一种半导体器件的制造方法,具备:
准备要装载半导体器件芯片的绝缘性薄片的工序;
在上述绝缘性薄片的上述半导体器件芯片的外侧形成分离用切缝的工序;
在上述绝缘性薄片上边,形成横穿上述分离用切缝的导电性图形的工序;
把半导体器件芯片装载到上述绝缘性薄片上边,把上述半导体器件芯片的外部端子电连到上述导电性图形上的工序。
11.根据权利要求10所述的半导体器件的制造方法,上述导电性图形的宽度,在横穿上述分离用切缝的部分处变窄。
12.根据权利要求10所述的半导体器件的制造方法,上述形成导电性图形的工序,还包括在上述绝缘性薄片上边形成,横穿上述分离用切缝、不连接到上述半导体器件芯片外部端子上的附加的导电性图形的工序。
13.一种带半导体器件的电路基板的制造方法,具备:
准备要装载半导体器件芯片的绝缘性薄片的工序;
在上述绝缘性薄片的第1区域的外侧形成分离用切缝的工序;
在上述绝缘性薄片上边,形成横穿上述分离用切缝的导电性图形的工序;
把半导体器件芯片装载到上述绝缘性薄片上边,把上述半导体器件芯片的外部端子电连到上述导电性图形上的工序;
把已装载有上述半导体器件芯片的绝缘性薄片的上述第1区域的至少一部分粘接到电路基板上的工序;
从第1区域分离上述第1区域的外侧的第2区域,在上述电路基板上边剩下上述第1区域的工序。
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JPH0653288A (ja) * | 1992-07-29 | 1994-02-25 | Sony Corp | タブテープ及びタブテープの実装方法 |
JP2852178B2 (ja) * | 1993-12-28 | 1999-01-27 | 日本電気株式会社 | フィルムキャリアテープ |
JPH0982752A (ja) * | 1995-09-14 | 1997-03-28 | Sony Corp | 半導体装置 |
US6171888B1 (en) * | 1996-03-08 | 2001-01-09 | Lsi Logic Corp. | Multi-layer tab tape having distinct signal, power and ground planes, semiconductor device assembly employing same, apparatus for and method of assembling same |
JP3442978B2 (ja) | 1997-10-15 | 2003-09-02 | シャープ株式会社 | テープキャリアパッケージ半導体装置及びそれを用いた液晶パネル表示装置 |
JP2001007239A (ja) * | 1999-06-17 | 2001-01-12 | Nec Corp | 半導体装置およびその製造方法 |
-
2001
- 2001-09-27 JP JP2001297041A patent/JP3825664B2/ja not_active Expired - Fee Related
-
2002
- 2002-09-24 TW TW091121903A patent/TW558802B/zh not_active IP Right Cessation
- 2002-09-26 KR KR1020020058485A patent/KR100550171B1/ko not_active IP Right Cessation
- 2002-09-26 US US10/254,779 patent/US6911725B2/en not_active Expired - Fee Related
- 2002-09-27 CN CNB021439133A patent/CN1245755C/zh not_active Expired - Fee Related
-
2004
- 2004-09-16 US US10/941,908 patent/US20050029635A1/en not_active Abandoned
Also Published As
Publication number | Publication date |
---|---|
TW558802B (en) | 2003-10-21 |
JP3825664B2 (ja) | 2006-09-27 |
US6911725B2 (en) | 2005-06-28 |
US20050029635A1 (en) | 2005-02-10 |
CN1411056A (zh) | 2003-04-16 |
US20030057543A1 (en) | 2003-03-27 |
KR100550171B1 (ko) | 2006-02-10 |
JP2003100813A (ja) | 2003-04-04 |
KR20030027757A (ko) | 2003-04-07 |
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