CN1245351A - 具有表面掩蔽层的半导体芯片 - Google Patents

具有表面掩蔽层的半导体芯片 Download PDF

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CN1245351A
CN1245351A CN99117959A CN99117959A CN1245351A CN 1245351 A CN1245351 A CN 1245351A CN 99117959 A CN99117959 A CN 99117959A CN 99117959 A CN99117959 A CN 99117959A CN 1245351 A CN1245351 A CN 1245351A
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circuit
semiconductor chip
wiring
lead
layer
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CN1165992C (zh
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R·阿林格
W·波克兰德特
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Infineon Technologies AG
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Siemens AG
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/57—Protection from inspection, reverse engineering or tampering
    • H01L23/573—Protection from inspection, reverse engineering or tampering using passive means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

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  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Storage Device Security (AREA)
  • Structure Of Printed Boards (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
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Abstract

半导体芯片,该芯片具有在半导体衬底(1)的至少一个层内实现的,在至少一个组内安置的电路(T1、T2)以及具有在电路(T1、T2)上方的至少一个布线层面(3)内分布的电源线和信号线(Vss、Vdd、SL1、SL2),其中在至少一个电路组上方的至少一个布线层面(3)内,电源线和信号线(Vss、Vdd、SL1、SL2)具有一最大宽度,使得每两个导线之间的距离最小。

Description

具有表面掩蔽层的半导体芯片
本发明涉及一种半导体芯片，该种芯片具有在半导体衬底的至少一个层内实现的，在至少一个组内安置的电路以及具有在电路上方的至少一个布线层面内分布的电源线和信号线。
以EP 0 378 306 A2已知这样一种类型的半导体芯片，在该种半导体芯片上一个第一电路组被安置在一受保护的区域内和一个第二电路组被安置在一个未被保护的区域内。在已知的半导体芯片上该第一区域的保护是通过一个导电层实现的，此导电层被安置在第一电路组的布线层面的上方。此导电层与电路组导电连接，其中只有在导电层完好无损的情况下才能给出该电路组正常的功能。
这里，第一电路组包括一种微处理器以及所属的外围电路，如存储器和一个转换逻辑电路。在存储器中尤其可以存放着保密信息。也可以想象微处理器有一种特殊的结构，该种结构特别好地适用于与安全保护有关的功能。通过其完好性不断受到检测的导电层可以防止借助例如一种扫描电子显微镜在电路工作期间进行探密。
然而，在制造半导体芯片时，这种导电层需要一外加的工艺步骤。此外，为检测导电层的完好性还需要相应的分析处理电路。
因此本发明的任务是，提供一种排除了该缺点的半导体芯片。
根据本发明该任务是如此解决的，即在一所述类型的半导体芯片上，在至少一个电路组上面的至少一个布线层面内电源线和信号线有尽可能大的宽度，使两个导线之间的距离最大约为当时技术水平可实现的最小距离的两倍。在一个优先的结构中，其两个导线之间的距离基本上相当于当时技术水平可实现的最小距离。
在此主要意味着，沿着有关导线长度的大部分导线之间的距离最小，或者最大是最小距离的一倍。通过这种小的距离一方面芯片表面几乎完全由不管怎样都是需要的导线布线层所掩蔽，并且在光学的以及电子光学的检测中受到保护。另一方面为了能够进行光学的表面检测而大面积去除导线，则如若没有其它探测器电路时将导致这些电路不再工作。
仅是局部地去除导线，例如围绕某些电路部分的剥离是不能实现的，因为由于小的距离将可能导致相邻导线的熔接。
在设计半导体芯片的电路布线技术时实现导线加宽。在此首先设计接地导线尽可能地加宽，以便保证地线与衬底之间实现最佳的电路的电容性耦合以及保证其余信号导线相互之间在最小耦合的情况下的低阻供电。下一步将加宽电源线。只是到最后才加宽信号导线，以便确保信号导线相互之间尽可能小的耦合。
根据本发明在至少一个布线层面内的导线的加宽至少是在需严格保密的电路部分的上方实现的，如在密码存储器或特殊密码电路的上方。然而，整个表面的导线都加宽是有利的，以便不为可能的探密者提供有关的保密电路部分在何处的可能的说明。
如果存在多个布线层面，就有可能在不同的布线层面内掩蔽不同的线路组，其中这里也可能出现掩蔽层的重叠。此外，当有多个布线层面时也可能不需附加花费就可设置多个掩蔽层。
下面借助一实施例和附图，进一步说明本发明。
这些附图是：
图1半导体芯片的具有电路层面和布线层面的原理性截面图，
图2按当前技术的布线层面的局部和
图3按本发明的布线层面同样的局部。
图1的截面图示出一个P型导电的半导体衬底1，其中作为电路的实例制成一CMOS反相器，此反相器由一个n沟道晶体管T1和一个P沟道晶体管T2组成。在半导体衬底1的有源层的上方安置一绝缘层2，该层大多数情况下由二氧化硅组成。在此绝缘层2的上方安置一布线层面3。此布线层面是由接地导线Vss、电源线Vdd以及信号线SL1、SL2组成。为了实现CMOS反相器，n沟道晶体管T1的源区S1穿过绝缘层2与接地导线Vss连接。n沟道晶体管T1的漏区D1和P沟道晶体管T2的漏区D2穿过绝缘层2与信号线SL1连接。P沟道晶体管T2的源区S2与电源线Vdd连接。栅电极G1和G2安置在绝缘层2内，这些电极与一个信号导线SL2连接。在布线层面3的上方通常安置一钝化层4形式的另一保护层。虽然在图1中仅示出了一个有源区和一个布线层面3，然而本发明也可以在多个有源层和/或多个布线层面的情况下加以实现。
在图2中示出按当前技术水平制造的布线层面的局部。正如所看到的那样，在导线之间有很大的空隙，所以在某些条件下通过光学途径可以探测到位于下方的电路结构。
与此相反图3示出本发明的一布线层面，在此层面上所有的导线扩展到如此宽，使得在它们之间达到按当前工艺技术水平可以实现的最小距离。由此一方面不再可能光学检测布线层面下的电路结构，另一方面在试图去除导体时将出现各个导线的熔接，以致形成短路。全部去除导线就意味着中止了位于下面的电路的功能。

Claims (2)

1.半导体芯片，该种芯片具有在半导体衬底(1)的至少一个层内实现的，在至少一个组内安置的电路(T1、T2)以及具有在电路(T1、T2)上方的至少一个布线层面(3)内分布的电源线和信号线(Vss、Vdd、SL1、SL2)，
其特征在于，
在至少一个电路组上方的至少一个布线层面(3)内，电源线和信号线(Vss、Vdd、SL1、SL2)具有尽可能大的宽度，使得在每两个导线之间的距离最大约等于按当前技术水平可实现的最小距离的两倍。
2.按权利要求1的半导体芯片，
其特征在于，
导线(Vss、Vdd、SL1、SL2)的宽度是这样限定的，使得在两个导线之间的距离基本上约等于按当前技术水平可实现的最小距离。
CNB991179595A 1998-08-19 1999-08-19 具有表面掩蔽层的半导体芯片 Expired - Fee Related CN1165992C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP98115621A EP0981162B1 (de) 1998-08-19 1998-08-19 Halbleiterchip mit Oberflächenabdeckung gegen optische Untersuchung der Schaltungsstruktur
EP98115621.9 1998-08-19

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CN1245351A true CN1245351A (zh) 2000-02-23
CN1165992C CN1165992C (zh) 2004-09-08

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US (1) US6392259B1 (zh)
EP (1) EP0981162B1 (zh)
JP (1) JP3728389B2 (zh)
KR (1) KR100382250B1 (zh)
CN (1) CN1165992C (zh)
AT (1) ATE356436T1 (zh)
BR (1) BR9903781A (zh)
DE (1) DE59813938D1 (zh)
UA (1) UA58535C2 (zh)

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DE10106836B4 (de) 2001-02-14 2009-01-22 Infineon Technologies Ag Integrierte Schaltungsanordnung aus einem flächigen Substrat
JP4758621B2 (ja) 2003-08-28 2011-08-31 パナソニック株式会社 基本セル、端部セル、配線形状、配線方法、シールド線の配線構造
DE102004015546B4 (de) * 2004-03-30 2011-05-12 Infineon Technologies Ag Halbleiterchip mit integrierter Schaltung und Verfahren zum Sichern einer integrierten Halbleiterschaltung
KR100665574B1 (ko) * 2004-12-14 2007-01-09 남유근 링형상 히터 및 그 제조방법

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NL7413264A (nl) * 1974-10-09 1976-04-13 Philips Nv Geintegreerde schakeling.
FR2471051A1 (fr) * 1979-11-30 1981-06-12 Dassault Electronique Circuit integre a transistors mos protege contre l'analyse et carte comprenant un tel circuit
US4933898A (en) * 1989-01-12 1990-06-12 General Instrument Corporation Secure integrated circuit chip with conductive shield
WO1996016445A1 (en) * 1994-11-23 1996-05-30 Motorola Ltd. Integrated circuit structure with security feature
US5783846A (en) * 1995-09-22 1998-07-21 Hughes Electronics Corporation Digital circuit with transistor geometry and channel stops providing camouflage against reverse engineering

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BR9903781A (pt) 2000-09-05
KR100382250B1 (ko) 2003-05-01
ATE356436T1 (de) 2007-03-15
UA58535C2 (uk) 2003-08-15
EP0981162A1 (de) 2000-02-23
KR20000017384A (ko) 2000-03-25
CN1165992C (zh) 2004-09-08
DE59813938D1 (de) 2007-04-19
EP0981162B1 (de) 2007-03-07
JP2000101030A (ja) 2000-04-07
US6392259B1 (en) 2002-05-21
JP3728389B2 (ja) 2005-12-21

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