CN1215892A - 能执行高速写入操作的半导体存储装置 - Google Patents
能执行高速写入操作的半导体存储装置 Download PDFInfo
- Publication number
- CN1215892A CN1215892A CN98123538.7A CN98123538A CN1215892A CN 1215892 A CN1215892 A CN 1215892A CN 98123538 A CN98123538 A CN 98123538A CN 1215892 A CN1215892 A CN 1215892A
- Authority
- CN
- China
- Prior art keywords
- signal
- data
- array selecting
- semiconductor memory
- yswi
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
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Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
- G11C7/1039—Read-write modes for single port memories, i.e. having either a random port or a serial port using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
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- Dram (AREA)
- Static Random-Access Memory (AREA)
Abstract
Description
Claims (9)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP09293816A JP3090104B2 (ja) | 1997-10-27 | 1997-10-27 | 半導体メモリ装置 |
JP293816/1997 | 1997-10-27 | ||
JP293816/97 | 1997-10-27 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1215892A true CN1215892A (zh) | 1999-05-05 |
CN1169154C CN1169154C (zh) | 2004-09-29 |
Family
ID=17799531
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB981235387A Expired - Fee Related CN1169154C (zh) | 1997-10-27 | 1998-10-27 | 能执行高速写入操作的半导体存储装置 |
Country Status (3)
Country | Link |
---|---|
US (1) | US6014333A (zh) |
JP (1) | JP3090104B2 (zh) |
CN (1) | CN1169154C (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN100498971C (zh) * | 2002-06-13 | 2009-06-10 | 松下电器产业株式会社 | 半导体存储设备和半导体存储设备的写入方法 |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04107907U (ja) * | 1991-03-01 | 1992-09-17 | 日本電業工作株式会社 | 誘電体共振器 |
JP4112729B2 (ja) * | 1999-02-16 | 2008-07-02 | 株式会社ルネサステクノロジ | 半導体装置 |
JP2001093289A (ja) * | 1999-09-24 | 2001-04-06 | Nec Corp | 多段階読み出し回路および多段階読み出し方法 |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61148692A (ja) * | 1984-12-24 | 1986-07-07 | Nippon Telegr & Teleph Corp <Ntt> | 記憶装置 |
JP2795846B2 (ja) * | 1987-11-25 | 1998-09-10 | 株式会社東芝 | 半導体装置 |
DE69023258T2 (de) * | 1989-03-15 | 1996-05-15 | Matsushita Electronics Corp | Halbleiter-Speichereinrichtung. |
JPH0536277A (ja) * | 1991-07-30 | 1993-02-12 | Fujitsu Ltd | 半導体メモリ装置 |
US5309395A (en) * | 1992-10-22 | 1994-05-03 | At&T Bell Laboratories | Synchronous static random access memory |
JP2707953B2 (ja) * | 1993-09-14 | 1998-02-04 | 日本電気株式会社 | 半導体メモリ回路 |
US5539696A (en) * | 1994-01-31 | 1996-07-23 | Patel; Vipul C. | Method and apparatus for writing data in a synchronous memory having column independent sections and a method and apparatus for performing write mask operations |
TW367656B (en) * | 1994-07-08 | 1999-08-21 | Hitachi Ltd | Semiconductor memory device |
KR0165159B1 (ko) * | 1994-07-28 | 1999-02-01 | 사또 후미오 | 반도체 기억 장치 |
KR0164395B1 (ko) * | 1995-09-11 | 1999-02-18 | 김광호 | 반도체 메모리 장치와 그 리이드 및 라이트 방법 |
US5668760A (en) * | 1996-04-23 | 1997-09-16 | Intel Corporation | Nonvolatile memory with a write protection circuit |
US5784331A (en) * | 1996-12-31 | 1998-07-21 | Sgs-Thomson Microelectronics, Inc. | Multiple access memory device |
-
1997
- 1997-10-27 JP JP09293816A patent/JP3090104B2/ja not_active Expired - Fee Related
-
1998
- 1998-10-27 US US09/179,098 patent/US6014333A/en not_active Expired - Lifetime
- 1998-10-27 CN CNB981235387A patent/CN1169154C/zh not_active Expired - Fee Related
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN100498971C (zh) * | 2002-06-13 | 2009-06-10 | 松下电器产业株式会社 | 半导体存储设备和半导体存储设备的写入方法 |
Also Published As
Publication number | Publication date |
---|---|
JP3090104B2 (ja) | 2000-09-18 |
CN1169154C (zh) | 2004-09-29 |
US6014333A (en) | 2000-01-11 |
JPH11134863A (ja) | 1999-05-21 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C06 | Publication | ||
PB01 | Publication | ||
ASS | Succession or assignment of patent right |
Owner name: NEC ELECTRONICS TAIWAN LTD. Free format text: FORMER OWNER: NONE Effective date: 20030425 |
|
C41 | Transfer of patent application or patent right or utility model | ||
TA01 | Transfer of patent application right |
Effective date of registration: 20030425 Address after: Tokyo, Japan Applicant after: NEC Corp. Co-applicant after: NEC Corp. Address before: Tokyo, Japan Applicant before: NEC Corp. |
|
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
ASS | Succession or assignment of patent right |
Owner name: ERBIDA MEMORY CO., LTD. Free format text: FORMER OWNER: NIPPON ELECTRIC CO., LTD. Effective date: 20041029 |
|
C41 | Transfer of patent application or patent right or utility model | ||
TR01 | Transfer of patent right |
Effective date of registration: 20041029 Address after: Tokyo, Japan Patentee after: Elpida Memory Inc. Address before: Japan Tokyo enihy electronic Limited by Share Ltd Patentee before: NEC Corp. |
|
ASS | Succession or assignment of patent right |
Owner name: PS4 LASCO CO., LTD. Free format text: FORMER OWNER: ELPIDA MEMORY INC. Effective date: 20130826 |
|
C41 | Transfer of patent application or patent right or utility model | ||
TR01 | Transfer of patent right |
Effective date of registration: 20130826 Address after: Luxemburg Luxemburg Patentee after: PS4 Russport Co.,Ltd. Address before: Tokyo, Japan Patentee before: Elpida Memory Inc. |
|
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20040929 Termination date: 20151027 |
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EXPY | Termination of patent right or utility model |