CN120981885A - 半导体器件的制造方法以及接合晶片 - Google Patents

半导体器件的制造方法以及接合晶片

Info

Publication number
CN120981885A
CN120981885A CN202380095859.2A CN202380095859A CN120981885A CN 120981885 A CN120981885 A CN 120981885A CN 202380095859 A CN202380095859 A CN 202380095859A CN 120981885 A CN120981885 A CN 120981885A
Authority
CN
China
Prior art keywords
wafer
wafers
bonding
sic
segmented
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202380095859.2A
Other languages
English (en)
Chinese (zh)
Inventor
田中贵规
中西洋介
渡边宽
三谷阳一郎
丹羽弘树
秋好恭兵
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Publication of CN120981885A publication Critical patent/CN120981885A/zh
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19Preparing inhomogeneous wafers
    • H10P90/1904Preparing vertically inhomogeneous wafers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H10P95/11Separation of active layers from substrates
    • H10P95/112Separation of active layers from substrates leaving a reusable substrate, e.g. epitaxial lift off
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/832Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
    • H10D62/8325Silicon carbide
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P10/00Bonding of wafers, substrates or parts of devices
    • H10P10/12Bonding of semiconductor wafers or semiconductor substrates to semiconductor wafers or semiconductor substrates
    • H10P10/128Bonding of semiconductor wafers or semiconductor substrates to semiconductor wafers or semiconductor substrates by direct semiconductor to semiconductor bonding
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement

Landscapes

  • Crystals, And After-Treatments Of Crystals (AREA)
  • Recrystallisation Techniques (AREA)
CN202380095859.2A 2023-03-27 2023-03-27 半导体器件的制造方法以及接合晶片 Pending CN120981885A (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2023/012178 WO2024201649A1 (ja) 2023-03-27 2023-03-27 半導体デバイスの製造方法および接合ウェハ

Publications (1)

Publication Number Publication Date
CN120981885A true CN120981885A (zh) 2025-11-18

Family

ID=92904161

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202380095859.2A Pending CN120981885A (zh) 2023-03-27 2023-03-27 半导体器件的制造方法以及接合晶片

Country Status (5)

Country Link
JP (1) JPWO2024201649A1 (https=)
KR (1) KR20250150609A (https=)
CN (1) CN120981885A (https=)
DE (1) DE112023006051T5 (https=)
WO (1) WO2024201649A1 (https=)

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4715470B2 (ja) * 2005-11-28 2011-07-06 株式会社Sumco 剥離ウェーハの再生加工方法及びこの方法により再生加工された剥離ウェーハ
EP1835533B1 (en) * 2006-03-14 2020-06-03 Soitec Method for manufacturing compound material wafers and method for recycling a used donor substrate
US9923063B2 (en) * 2013-02-18 2018-03-20 Sumitomo Electric Industries, Ltd. Group III nitride composite substrate and method for manufacturing the same, laminated group III nitride composite substrate, and group III nitride semiconductor device and method for manufacturing the same
DE102017119568B4 (de) 2017-08-25 2024-01-04 Infineon Technologies Ag Siliziumkarbidbauelemente und Verfahren zum Herstellen von Siliziumkarbidbauelementen
CN112839813A (zh) * 2018-10-16 2021-05-25 麻省理工学院 在升华的sic基底上使用碳缓冲的外延生长模板
JP7512641B2 (ja) * 2020-03-27 2024-07-09 住友金属鉱山株式会社 接合基板の製造方法

Also Published As

Publication number Publication date
JPWO2024201649A1 (https=) 2024-10-03
DE112023006051T5 (de) 2026-02-05
KR20250150609A (ko) 2025-10-20
WO2024201649A1 (ja) 2024-10-03

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