JPWO2024201649A1 - - Google Patents
Info
- Publication number
- JPWO2024201649A1 JPWO2024201649A1 JP2025509280A JP2025509280A JPWO2024201649A1 JP WO2024201649 A1 JPWO2024201649 A1 JP WO2024201649A1 JP 2025509280 A JP2025509280 A JP 2025509280A JP 2025509280 A JP2025509280 A JP 2025509280A JP WO2024201649 A1 JPWO2024201649 A1 JP WO2024201649A1
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
- H10P90/19—Preparing inhomogeneous wafers
- H10P90/1904—Preparing vertically inhomogeneous wafers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
- H10P95/11—Separation of active layers from substrates
- H10P95/112—Separation of active layers from substrates leaving a reusable substrate, e.g. epitaxial lift off
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
- H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
- H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
- H10D62/8325—Silicon carbide
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P10/00—Bonding of wafers, substrates or parts of devices
- H10P10/12—Bonding of semiconductor wafers or semiconductor substrates to semiconductor wafers or semiconductor substrates
- H10P10/128—Bonding of semiconductor wafers or semiconductor substrates to semiconductor wafers or semiconductor substrates by direct semiconductor to semiconductor bonding
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/JP2023/012178 WO2024201649A1 (ja) | 2023-03-27 | 2023-03-27 | 半導体デバイスの製造方法および接合ウェハ |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPWO2024201649A1 true JPWO2024201649A1 (https=) | 2024-10-03 |
| JPWO2024201649A5 JPWO2024201649A5 (https=) | 2025-06-05 |
Family
ID=92904161
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2025509280A Pending JPWO2024201649A1 (https=) | 2023-03-27 | 2023-03-27 |
Country Status (5)
| Country | Link |
|---|---|
| JP (1) | JPWO2024201649A1 (https=) |
| KR (1) | KR20250150609A (https=) |
| CN (1) | CN120981885A (https=) |
| DE (1) | DE112023006051T5 (https=) |
| WO (1) | WO2024201649A1 (https=) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007149907A (ja) * | 2005-11-28 | 2007-06-14 | Sumco Corp | 剥離ウェーハの再生加工方法及びこの方法により再生加工された剥離ウェーハ |
| JP2007251129A (ja) * | 2006-03-14 | 2007-09-27 | Soi Tec Silicon On Insulator Technologies Sa | 複合材料ウェハの製造方法および使用済みドナー基板のリサイクル方法 |
| WO2014125688A1 (ja) * | 2013-02-18 | 2014-08-21 | 住友電気工業株式会社 | Iii族窒化物複合基板およびその製造方法、積層iii族窒化物複合基板、ならびにiii族窒化物半導体デバイスおよびその製造方法 |
| JP2021158248A (ja) * | 2020-03-27 | 2021-10-07 | 住友金属鉱山株式会社 | 接合基板の製造方法 |
| JP2022504927A (ja) * | 2018-10-16 | 2022-01-13 | マサチューセッツ インスティテュート オブ テクノロジー | 昇華させられたsic基板上のカーボンバッファを用いたエピタキシャル成長テンプレート |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE102017119568B4 (de) | 2017-08-25 | 2024-01-04 | Infineon Technologies Ag | Siliziumkarbidbauelemente und Verfahren zum Herstellen von Siliziumkarbidbauelementen |
-
2023
- 2023-03-27 KR KR1020257030679A patent/KR20250150609A/ko active Pending
- 2023-03-27 CN CN202380095859.2A patent/CN120981885A/zh active Pending
- 2023-03-27 DE DE112023006051.7T patent/DE112023006051T5/de active Pending
- 2023-03-27 JP JP2025509280A patent/JPWO2024201649A1/ja active Pending
- 2023-03-27 WO PCT/JP2023/012178 patent/WO2024201649A1/ja not_active Ceased
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007149907A (ja) * | 2005-11-28 | 2007-06-14 | Sumco Corp | 剥離ウェーハの再生加工方法及びこの方法により再生加工された剥離ウェーハ |
| JP2007251129A (ja) * | 2006-03-14 | 2007-09-27 | Soi Tec Silicon On Insulator Technologies Sa | 複合材料ウェハの製造方法および使用済みドナー基板のリサイクル方法 |
| WO2014125688A1 (ja) * | 2013-02-18 | 2014-08-21 | 住友電気工業株式会社 | Iii族窒化物複合基板およびその製造方法、積層iii族窒化物複合基板、ならびにiii族窒化物半導体デバイスおよびその製造方法 |
| JP2022504927A (ja) * | 2018-10-16 | 2022-01-13 | マサチューセッツ インスティテュート オブ テクノロジー | 昇華させられたsic基板上のカーボンバッファを用いたエピタキシャル成長テンプレート |
| JP2021158248A (ja) * | 2020-03-27 | 2021-10-07 | 住友金属鉱山株式会社 | 接合基板の製造方法 |
Also Published As
| Publication number | Publication date |
|---|---|
| DE112023006051T5 (de) | 2026-02-05 |
| CN120981885A (zh) | 2025-11-18 |
| KR20250150609A (ko) | 2025-10-20 |
| WO2024201649A1 (ja) | 2024-10-03 |
Similar Documents
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20250324 |
|
| A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20250324 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20260217 |
|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20260409 |
|
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20260421 |