CN1207578A - 结构化方法 - Google Patents

结构化方法 Download PDF

Info

Publication number
CN1207578A
CN1207578A CN98116749A CN98116749A CN1207578A CN 1207578 A CN1207578 A CN 1207578A CN 98116749 A CN98116749 A CN 98116749A CN 98116749 A CN98116749 A CN 98116749A CN 1207578 A CN1207578 A CN 1207578A
Authority
CN
China
Prior art keywords
thin layer
structuring
mask
treat
gas
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN98116749A
Other languages
English (en)
Inventor
M·恩格尔哈德特
V·维恩里希
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Publication of CN1207578A publication Critical patent/CN1207578A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041Cleaning
    • H01L21/02043Cleaning before device manufacture, i.e. Begin-Of-Line process
    • H01L21/02052Wet cleaning only
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274Photolithographic processes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/31051Planarisation of the insulating layers
    • H01L21/31053Planarisation of the insulating layers involving a dielectric removal step
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
    • H01L21/31105Etching inorganic layers
    • H01L21/31111Etching inorganic layers by chemical means
    • H01L21/31116Etching inorganic layers by chemical means by dry-etching
    • H01L21/31122Etching inorganic layers by chemical means by dry-etching of layers not containing Si, e.g. PZT, Al2O3
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
    • H01L21/31144Etching the insulating layers by chemical or physical means using masks
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321After treatment
    • H01L21/3213Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40Capacitors
    • H01L28/60Electrodes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40Capacitors
    • H01L28/55Capacitors with a dielectric comprising a perovskite structure material
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00Semiconductor device manufacturing: process
    • Y10S438/959Mechanical polishing of wafer
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00Semiconductor device manufacturing: process
    • Y10S438/963Removing process residues from vertical substrate surfaces

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Drying Of Semiconductors (AREA)
  • Semiconductor Memories (AREA)
  • Preparing Plates And Mask In Photomechanical Process (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)

Abstract

本发明提出一种使至少一层待结构化薄层结构化的方法,该方法包括下列步骤:在待结构化的薄层上覆盖上掩膜,在使用掩膜的情况下,使该待结构化薄层结构化,去除掩膜,此时该待结构化薄层的材料的再沉积物被遗留,和该待结构化薄层的材料的再沉积物被机械抛光或化学机械抛光去除。

Description

结构化方法
本发明涉及一种结构化方法,特别是涉及一种难以或不能以等离子体化学或干化学刻蚀的薄层的结构化方法,例如这种薄层是由贵金属,铁电材料以及高的相对介电常数的介电材料所组成。
开发高集成存储器芯片时,如DRAM或FRAM,要求在进一步小型化时,应保持或改善单元电容。为了达到这个目的,采用越来越薄的介电层和折叠式的电容器极板[(夹层式-单元(Trench-Zelle),堆积式-单元(Stack-Zelle))]。近年来采用新型材料来代替惯用的氧化硅类材料,新型材料特别是指介于存储器单元的电容器极板之间的顺电体和铁电体。例如钡锶钛酸盐(BST,(Ba,Br)TiO3),铅锆酸盐·钛酸盐(PZT,Pb(Zr,Ti)O3)以及掺杂镧的铅锆酸盐·钛酸盐或锶铋钽酸盐(SBT,SrBi2Ta2O9)用于DRAM或FRAM存储器单元的电容器。
在此方法中,这些材料通常是沉积在准备好的极板(底部极板)上。该过程是在高温下进行,这样,通常形成的电容器极板的材料,如掺杂的多晶硅,易于被氧化,并失去其导电性能,从而导至存储器单元的损坏。
从良好的氧化稳定性和/或形成导电氧化物看,4d和5d过渡金属,特别是铂族金属(Ru、Rh、Pd、Os、Ir、Pt)和尤其是铂本身以及铼可作为富有希望的候选材料,可能代替掺杂多晶硅作为上述存储器单元中的极板材料。
器件的进一步微型化的结果同样需要对至今在导体线路上采用的铝材料寻找替代材料。这种取代材料应比铝的电阻率小以及有较小的电迁移。铜是其中最富有希望的候选材料。
再者,磁性的“随机存取存储器”(MRAM)的开发需要在微电子线路中磁性薄层(例如Fe,Co,Ni或坡莫合金)的集成化。
为了所述的、至今在半导体工艺中尚未推广的材料能制成集成电路,必须使这些材料的薄层能结构化。
直到目前所用材料的结构化一般是用所谓的等离子体增强的各向异性的刻蚀方法。这里通常应用物理化学的方法,在这些方法中所采用的气体混合物为一种或多种反应性的气体,如氧、氯、溴、氯化氢、溴化氢以及卤素化碳氢化合物和惰性气体(如Ar,He)。通常这种气体混合物在电磁交变场中在低气压下受激。
图4是一个刻蚀室的工作原理图,它是作为一种平行板反应器20的实例。气体混合物,例如Ar和Cl2经过气体入口21进入实际的反应室22,并用泵从气体出口29抽出。平行板反应器的下板24经电容器27与高频源28相连,同时作为基片架,在平行板反应器的上板和下板23,24上施加高频交变电场下将气体混合物转换成等离子体25。由于电子的迁移率大于气体阳离子迁移率,因此上板和下板23和24相对等离子体25来说带负电。因而两平板23,24对带正电的气体阳离子产生强的引力,使这些平板受到这些离子例如Ar+的持续性轰击。在此期间由于气体压力保持较低,典型值为0.1-10Pa,所以离子彼此和与中性粒子只发生很少的散射,同时离子几乎垂直地打在平行板反应器下板24上的基片26的表面上。这样可在处于掩膜下面的基片26的待刻蚀薄层上形成良好的掩膜图象(未示出)。
通常应用光刻胶作为掩膜材料,由于它经过爆光和显影步骤能相对简单的结构化。
刻蚀作用的物理机理部分是通过入射离子(例如Cl2 +,Ar+)的动量和动能作用。此外,在挥发性反应物形成的情况下,还由此引发或加强了基片和反应性气体粒子(离子,分子,原子,自由基)之间的化学反应(刻蚀作用的化学机理部分)。基片粒子和气体粒子之间的这种化学反应决定着刻蚀工艺的高刻蚀选择性。
可惜实验表明上所述的,在集成电路中所用的新材料属于化学上很难或者不可能刻蚀的材料,在此过程中,其刻蚀量以及在应用“反应性”气体的情况下,大部分的或者近乎所有的均由刻蚀作用的物理机理部分产生。
由于较少或者缺少刻蚀的化学组分,故待结构化的薄层的刻蚀量与掩膜或底层(Unterlage)(刻蚀中止薄层)的刻蚀量处于同一数量级,也就是说,刻蚀掩膜或底层的刻蚀选择性一般较小(约0.3-3.0)。其结果是,由于顺倾斜侧面的掩膜的侵蚀以及掩膜的难免的刻面形成(Facettierung)(斜切、锥度)只能保证结构形成的较小尺寸的稳定性。此刻面限制了在结构形成时达到最小的结构形成尺寸,以及限制了在待形成结构的薄层上剖面侧壁可达到的陡度。
其中在掩膜上的刻面,和从而还有待结构化薄层的刻面,当在混合气体中反应气体(特别是氯)的成分越大时这种刻面也越大,该混合气体是在等离子化学刻蚀工艺期间所使用的气本。与此相对应使用不具有反应气体分量的混合气体。例如纯氩气等离子体,可以在待结构化薄层中制造最陡的剖面侧壁。
除所述待结构化薄层的刻面之外,在结构化时还可出现待结构化薄层材料的不希望有的再沉积物。例如这种再沉积物出现在光刻胶掩膜的侧壁上,并且这些再沉积物在随后的工艺步骤中常常是只能用很多的费用才能去除,可惜在等离子体化学刻蚀工艺期间所用混合气体中反应气体的成分越小这种再沉积物出现的越多。根据这种情况,到目前为止的工艺实施,例如在一种氯-氩等离子体中大多限于较少的氩成分。然而在刻蚀混合气体中氯成分的增加又导致增加掩膜的刻面形成。
在用光刻胶掩膜刻蚀铂的情况下,使用反应气体如氯或HBr导致形成中间反应物的沉积,该种中间反应物的沉积在进一步的刻蚀过程中重又消失。这种结构也导致一种CD-展宽并且导致缓的铂边缘。当前,这些视为是使用氯及光刻胶掩膜工艺的最大缺点。
如果使用一种所谓的“硬掩膜”代替光刻胶掩膜用于结构化待结构化的薄层,那么许多所述困难可以明显减少。然而“硬掩膜”的结构化需要附加使整个工艺费用增加的工艺步骤。
因此,本发明的任务是提供一种结构化方法,该方法可以避免或者减少所述的现有方法的缺点。此任务是通过下述方法解决的。
根据本发明提供一种使至少一个待结构化薄层结构化的方法,该方法包括下列步骤:
在待结构化薄层上覆盖一掩膜,
应用掩膜使待结构化薄层结构化,
去除掩膜,其中留下待结构化掩膜的材料的再沉积物,和
待结构化薄层的材料的再沉积物将通过机械抛光或通过化学机械抛光去除。这是权利要求1的内容。
实验证明,通过机械抛光,用通常的化学方法很难除去的待结构化的薄层材料的再沉积物,可以比较简单地和可靠地去除,而不会对已在晶片上制造的结构有所伤害或破坏。因此本发明方法的优点是,用于使待结构化薄层的真正结构化的方法,例如等离子体化学刻蚀方法可被选用,而不必顾虑是否该种方法会导致大量再沉积。这样就可以例如使用有纯氩气的等离子体化学刻蚀方法。这种情况导致的结果是,现在也可以使用常规的光刻胶掩膜,而不会像使用反应气体那样导致在掩膜上形成过量的刻面。
此外,根据本发明提出了一种使至少一个待结构化薄层结构化的方法,该方法包括下列步骤:
在待结构化的薄层上覆上一掩膜,
该待结构化薄层在使用掩膜的情况下结构化,
该掩膜和待结构化薄层的材料的再沉积物被通过化学机械抛光去除。这是权利要求3的内容。
通过同时去除掩膜和再沉积物可以省去一道工艺步骤。这种可能性特别是当使用一种所谓的“硬掩膜”作掩膜时可以实现。这种掩膜优先包括硅,一种硅氧化物,尤其是SiO2、一种金属、特别是铝或钨、一种金属氮化物、优先是一种氮化钛特别是TiNx 0.8<x<1.2或者一种金属硅化物。
在去除再沉积物之后,优先进行一种“洗涤机(Scrubber)”清洁处理。附加地或者代替地,在去除再沉积物之后,也可以进行一种湿化学法清洁处理,尤其是用声波作用(超声波,精细声波(finesonic))增强处理。
待结构化薄层优先含有铜、铁、钴、镍、一种4d或5d过渡金属、尤其是一种铂族金属。
另外,待结构化的薄层优先含有一种铁电材料、一种高的相对介电常数(>20)的材料、一种钙钛矿或者这些材料的前级材料。在此,对这些所述材料的前级材料应理解为这样的一种材料,即该种材料通过适当的热加工(例如热处理),必要时引入氧气,可转变成所述材料。
这样,待结构化薄层优先含有锶铋钽酸盐(SBT,SrBi2Ta2O3),锶铋铌酸盐·钽酸盐(SBNT,SrBi2Ta2-xNbxO9,x=0-2),铅锆酸盐·钛酸盐(PZT,Pb(Zr,Ti)O3)或者衍生物以及钡锶钛酸盐(BST,BaxSr1-xTiO3,x=0-1),铅镧钛酸盐(PLT,(Pb,La)TiO3),铅镧锆酸盐·钛酸盐(PLZT,(Pb,La)(Zr,Ti)O3)或衍生物。
此外,待结构化薄层优先含有铂、金、银、铜、铱、钯、钌、铼或其氧化物。
为使待结构化薄层结构化,优先采用一种干法刻蚀,尤其是一种等离子体刻蚀法。
在此,在待结构化薄层干法刻蚀期间,优先使用一种不含反应气体的混合气体。
此外,在待结构化薄层干法刻蚀期间,优先采用一种惰性气体,特别是氩气。
下面借助附图进一步阐述本发明。这些附图示出:
图1至图3本发明方法的示意图,和
图4一种平行板反应器结构的刻蚀室示意图。
图1至图3示出一种本发明方法的示意图。在衬底1上覆盖一SiO2层2。随后覆盖上由钛或氮化钛组成的附着层或阻挡层3。在附着层或阻挡层3上覆盖上一层铂层4用作待结构化薄层,例如通过溅射。在铂层4上形成一光刻胶层,以后该层用作铂层4结构化的掩膜5。光刻胶层通过曝光工艺和显影工艺实现结构化。由此得到的结构是在图1中示出的。
随后进行离子刻蚀或者溅射刻蚀,使铂层4经受物理的干法刻蚀。在此,用纯氩气作为刻蚀气体。也可以用其它等离子体刻蚀方法代替离子刻蚀法,如反应离子刻蚀(RIE,Reactive Ion Etching)、磁场增强反应离子刻蚀(MERIE,Magnetically Enhanced RIE)、ECR-刻蚀(ECR,电子回旋共振Electron Cyclotron Resonance)或电感耦合等离子体刻蚀法(ICP、TCP)。
因为纯氩气可以用作刻蚀气体,所以不形成掩膜5的明显的刻面。与此相对应掩膜经受的侵蚀也是小的。由于较小的掩膜侵蚀所以产生较高的结构化的尺寸稳定性。此时,由于还可实现待结构化薄层的陡的刻蚀侧壁。可以制造具有大于80°的侧壁角的刻蚀侧壁。
由于缺少化学分量,在干法刻蚀期间,在胶掩膜5的侧壁上出现铂的再沉积物6。到目前为止,这些铂的再沉积物6用常规化学方法很难再去除。
为了去除胶掩膜5进行一种胶灰化工艺。在此在已结构化的铂薄层4的表面上遗留下孤立的铂再沉积物6。由此得到的结构示于图2中。
随后通过机械抛光去除这些再沉积物6。为此,例如可以使用Logitech公司的抛光机。使抛光布(例如Chemcloth ELCON 136)与图2中示出的结构相接触。图2示出的结构与抛光布相对以每分钟10转速度转动3分钟。同时在水悬浮液(pH≈9)中加入约0.25μm大的Al2O3微粒。
随后进行“洗涤机”清洁处理。在去除再沉积物6之后,附加地或替代地也可以进行湿法化学清洁处理,例如用高稀释的HF酸并优先用声波作用来增强清洗。这种清洁处理导致对铂结构之间暴露的SiO2表面的化学溶解,并导致从这些区域机械辅助的对微小颗粒的去除。由此得到的结构在图3中示出。

Claims (14)

1.用于结构化至少一层待结构化薄层的方法具有如下步骤:
在待结构化薄层上覆盖一掩膜,
在使用掩膜的条件下,将待结构化薄层结构化,
去除掩膜,此时待结构化薄层的材料的再沉积物被遗留,和
待结构化薄层的材料的再沉积物,通过机械抛光或化学机械抛光被去除。
2.根据权利要求1的方法,其特征在于,该掩膜是一种光刻胶掩膜,此掩膜优先通过灰化去除。
3.用于结构化至少一层待结构化薄层的方法具有如下步骤:
在待结构化薄层上覆盖一掩膜,
在使用掩膜的条件下,将待结构化薄层结构化,
该掩膜及待结构化薄层的材料的再沉积物通过化学机械抛光去除。
4.根据权利要求1至3之一的方法,其特征在于,在去除再沉积物之后进行“洗涤机”清洁处理。
5.根据权利要求1至4之一的方法,其特征在于,在去除再沉积物之后进行湿化学法清洁处理。
6.根据权利要求4或5之一的方法,其特征在于,清洁处理经声波作用予以增强。
7.根据权利要求1至6之一的方法,其特征在于,该结构化薄层含有铜、铁、钴、镍、一种4d或5d过渡金属、尤其一种铂族金属。
8.根据权利要求1至6之一的方法,其特征在于,该待结构化薄层含有一铁电材料、一高介电常数的介电材料、一种钙钛矿或者这些材料的前级材料。
9.根据权利要求8的方法,其特征在于,该待结构化的薄层含有锶铋钽酸盐(SBT,SrBi2Ta2O9),锶铋铌酸盐·钽酸盐(SBNT,SrBi2Ta2-xNbxO9,x=0-2),铅锆酸盐·钛酸盐(PZT,Pb(Zr,Ti)O3)或衍生物或钡锶钛酸盐(BST,BaxSr1-xTiO3,X=0-1),铅镧钛酸盐(PLT,(Pb,La)TiO3),铅镧锆酸盐·钛酸盐(PLZT,(Pb,La)(Zr,Ti)O3)或衍生物。
10.根据权利要求7的方法,其特征在于,该待结构化薄层含有铂、金、银、铱、钯、钌、铼或其氧化物。
11.根据上述权利要求之一的方法,其特征在于,在干法刻蚀待结构化薄层期间,使用一种混合气体,这种气体不含反应气体。
12.根据上述权利要求之一的方法,其特征在于,在干法刻蚀待结构化薄层期间,使用一种混合气体,这种气体除含有惰性气体和氮气外,仅还含氧气。
13.根据上述权利要求之一的方法,其特征在于,在干法刻蚀待结构化薄层期间,使用一种惰性气体,特别是氩气。
14.根据权利要求1至13之一的方法,其特征在于,该掩膜含有硅、一种硅氧化物特别是SiO2、一种金属特别是铝或钨、一种金属氮化物、优先是钛氮化物、特别是TiNx 0.8<x<1.2或者一种金属硅化物。
CN98116749A 1997-08-01 1998-07-31 结构化方法 Pending CN1207578A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19733391.5 1997-08-01
DE19733391A DE19733391C2 (de) 1997-08-01 1997-08-01 Strukturierungsverfahren

Publications (1)

Publication Number Publication Date
CN1207578A true CN1207578A (zh) 1999-02-10

Family

ID=7837753

Family Applications (1)

Application Number Title Priority Date Filing Date
CN98116749A Pending CN1207578A (zh) 1997-08-01 1998-07-31 结构化方法

Country Status (7)

Country Link
US (1) US6454956B1 (zh)
EP (1) EP0901157B1 (zh)
JP (1) JPH11126778A (zh)
KR (1) KR100538910B1 (zh)
CN (1) CN1207578A (zh)
DE (2) DE19733391C2 (zh)
TW (1) TW574424B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106803486A (zh) * 2012-11-06 2017-06-06 华邦电子股份有限公司 非易失性存储器的制造方法

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0907203A3 (de) * 1997-09-03 2000-07-12 Siemens Aktiengesellschaft Strukturierungsverfahren
JP3974697B2 (ja) * 1997-11-28 2007-09-12 ローム株式会社 キャパシタおよびその製法
DE10022656B4 (de) * 2000-04-28 2006-07-06 Infineon Technologies Ag Verfahren zum Entfernen von Strukturen
DE10109328A1 (de) 2001-02-27 2002-09-12 Infineon Technologies Ag Verfahren zur Entfernung einer Maskenschicht von einem Halbleitersubstrat
DE10118422B4 (de) 2001-04-12 2007-07-12 Infineon Technologies Ag Verfahren zur Herstellung einer strukturierten metallhaltigen Schicht auf einem Halbleiterwafer
DE10147929C1 (de) 2001-09-28 2003-04-17 Infineon Technologies Ag Verfahren zum Herstellen einer Halbleiterstruktur und Verwendung des Verfahrens
KR100615600B1 (ko) * 2004-08-09 2006-08-25 삼성전자주식회사 고집적 자기램 소자 및 그 제조방법
US6952364B2 (en) * 2003-03-03 2005-10-04 Samsung Electronics Co., Ltd. Magnetic tunnel junction structures and methods of fabrication
US7067016B1 (en) * 2003-03-31 2006-06-27 Lam Research Corporation Chemically assisted mechanical cleaning of MRAM structures
KR100831572B1 (ko) * 2005-12-29 2008-05-21 동부일렉트로닉스 주식회사 반도체 소자의 배선 형성방법
US20090115060A1 (en) * 2007-11-01 2009-05-07 Infineon Technologies Ag Integrated circuit device and method
DE102007061485A1 (de) * 2007-12-20 2009-06-25 Altis Semiconductor Snc Verfahren zum Herstellen einer integrierten Schaltung
US7799696B2 (en) 2007-12-20 2010-09-21 Qimonda Ag Method of manufacturing an integrated circuit
DE102008032509A1 (de) * 2008-07-10 2010-01-14 Epcos Ag Heizungsvorrichtung und Verfahren zur Herstellung der Heizungsvorrichtung

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5616676A (en) 1979-07-21 1981-02-17 Hokuriku Denki Kogyo Kk Preparation of minute pattern
NL8703039A (nl) * 1987-12-16 1989-07-17 Philips Nv Werkwijze voor het patroonmatig vervaardigen van een dunne laag uit een oxidisch supergeleidend materiaal.
EP0425787A3 (en) * 1989-10-31 1993-04-14 International Business Machines Corporation Method for fabricating high circuit density, self-aligned metal lines to contact windows
US5981454A (en) * 1993-06-21 1999-11-09 Ekc Technology, Inc. Post clean treatment composition comprising an organic acid and hydroxylamine
US5244538A (en) 1991-07-26 1993-09-14 Microelectronics And Computer Technology Corporation Method of patterning metal on a substrate using direct-write deposition of a mask
DE69333877T2 (de) * 1992-07-09 2006-06-14 Ekc Technology Inc Reinigungsmittelzusammensetzung, das einem Redox Aminverbindung enthält
US5275974A (en) 1992-07-30 1994-01-04 Northern Telecom Limited Method of forming electrodes for trench capacitors
DE59402986D1 (de) 1993-07-27 1997-07-10 Siemens Ag Verfahren zur Herstellung eines Halbleiterschichtaufbaus mit planarisierter Oberfläche und dessen Verwendung bei der Herstellung eines Bipolartransistors sowie eines DRAM
US5585661A (en) 1993-08-18 1996-12-17 Harris Corporation Sub-micron bonded SOI by trench planarization
JPH07130702A (ja) * 1993-11-08 1995-05-19 Fujitsu Ltd 白金又はパラジウムよりなる金属膜のパターニング方法
US5545289A (en) * 1994-02-03 1996-08-13 Applied Materials, Inc. Passivating, stripping and corrosion inhibition of semiconductor substrates
JP3438446B2 (ja) * 1995-05-15 2003-08-18 ソニー株式会社 半導体装置の製造方法
JP2953369B2 (ja) * 1996-01-17 1999-09-27 日本電気株式会社 半導体装置の構造およびその製造方法
US6004839A (en) * 1996-01-17 1999-12-21 Nec Corporation Semiconductor device with conductive plugs
EP0865079A3 (en) * 1997-03-13 1999-10-20 Applied Materials, Inc. A method for removing redeposited veils from etched platinum surfaces
US5976928A (en) * 1997-11-20 1999-11-02 Advanced Technology Materials, Inc. Chemical mechanical polishing of FeRAM capacitors

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106803486A (zh) * 2012-11-06 2017-06-06 华邦电子股份有限公司 非易失性存储器的制造方法

Also Published As

Publication number Publication date
DE19733391C2 (de) 2001-08-16
DE19733391A1 (de) 1999-04-15
KR19990023265A (ko) 1999-03-25
US6454956B1 (en) 2002-09-24
DE59813289D1 (de) 2006-01-26
EP0901157A2 (de) 1999-03-10
EP0901157B1 (de) 2005-12-21
KR100538910B1 (ko) 2006-03-07
EP0901157A3 (de) 2000-09-13
JPH11126778A (ja) 1999-05-11
TW574424B (en) 2004-02-01

Similar Documents

Publication Publication Date Title
CN1207578A (zh) 结构化方法
CN1146023C (zh) 结构形成方法
US20030059720A1 (en) Masking methods and etching sequences for patterning electrodes of high density RAM capacitors
JP2003318371A (ja) 強誘電体メモリセルに関連するキャパシタスタックのエッチング方法
JP2002537645A (ja) 異方性白金形状のための改良されたエッチング法
KR20010102192A (ko) 유전체 물질의 부식을 방지하는 방법
CN1148789C (zh) 腐蚀半导体晶片的方法和装置
US6315913B1 (en) Structuring method
US6127277A (en) Method and apparatus for etching a semiconductor wafer with features having vertical sidewalls
US6670233B2 (en) Methods of patterning a multi-layer film stack and forming a lower electrode of a capacitor
KR19990013561A (ko) 구조화 방법
US7045070B1 (en) Method of producing an electrode configuration and method of electrically contacting the electrode configuration
KR100224730B1 (ko) 반도체장치의 패턴 형성방법 및 이를 이용한 커패시터 제조방법
JP4399195B2 (ja) 強誘電体メモリ素子のキャパシタ形成方法
EP1372187A1 (en) Method for manufacturing semiconductor device
JP2000195846A (ja) ドライエッチング方法およびドライエッチング装置
US6825116B2 (en) Method for removing structures
KR100537231B1 (ko) 반도체웨이퍼식각방법및장치
KR20020010574A (ko) 고밀도 ram 커패시터의 전극을 패턴화하기 위한 개선된마스킹 방법 및 에칭 공정
KR20010018060A (ko) 강유전체 커패시터의 상부 전극을 노출하는 콘택홀 형성방법
KR20000042490A (ko) 반도체소자의 저장전극 제조방법
KR20020009696A (ko) 포토레지스트 패턴 측벽에 증착되는 폴리머를 제거할 수있는 패턴 형성 방법 및 그를 이용한 강유전체 캐패시터형성 방법

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C12 Rejection of a patent application after its publication
RJ01 Rejection of invention patent application after publication