CN1183706A - 制备电路的方法及设备、使焊料均匀和传送焊膏的夹具板 - Google Patents
制备电路的方法及设备、使焊料均匀和传送焊膏的夹具板 Download PDFInfo
- Publication number
- CN1183706A CN1183706A CN97126212A CN97126212A CN1183706A CN 1183706 A CN1183706 A CN 1183706A CN 97126212 A CN97126212 A CN 97126212A CN 97126212 A CN97126212 A CN 97126212A CN 1183706 A CN1183706 A CN 1183706A
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- Prior art keywords
- semiconductor device
- brazing metal
- salient point
- circuit device
- substrate
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- 229910000679 solder Inorganic materials 0.000 title claims description 100
- 238000000034 method Methods 0.000 title claims description 52
- 239000004065 semiconductor Substances 0.000 claims abstract description 236
- 239000002184 metal Substances 0.000 claims abstract description 100
- 229910052751 metal Inorganic materials 0.000 claims abstract description 100
- 238000005219 brazing Methods 0.000 claims abstract description 95
- 230000002950 deficient Effects 0.000 claims abstract description 70
- 238000010438 heat treatment Methods 0.000 claims abstract description 31
- 238000005476 soldering Methods 0.000 claims description 72
- 239000000758 substrate Substances 0.000 claims description 51
- 238000003466 welding Methods 0.000 claims description 50
- 230000008878 coupling Effects 0.000 claims description 34
- 238000010168 coupling process Methods 0.000 claims description 34
- 238000005859 coupling reaction Methods 0.000 claims description 34
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 claims description 25
- 238000002360 preparation method Methods 0.000 claims description 16
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 9
- 229910052710 silicon Inorganic materials 0.000 description 9
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- 230000007246 mechanism Effects 0.000 description 5
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- 238000007796 conventional method Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000011156 evaluation Methods 0.000 description 3
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 description 3
- 230000003287 optical effect Effects 0.000 description 3
- 230000005855 radiation Effects 0.000 description 3
- 238000002474 experimental method Methods 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
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- 230000005496 eutectics Effects 0.000 description 1
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- 238000009434 installation Methods 0.000 description 1
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- 229910052759 nickel Inorganic materials 0.000 description 1
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- 230000000630 rising effect Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
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Abstract
一种包括修补步骤的制备电子电路装置的方法及设备、使焊料均匀和传送焊膏的夹具板,当发现布线板上的半导体器件有缺陷时,就用新的半导体器件来代之。该修补步骤包括:清除保留在已清除有缺陷的半导体器件的布线板焊接区上的多余的残余钎焊金属,并在焊接区留下一等量均匀的残余钎焊金属;使新半导体器件与布线板对准;通过加热熔化所留下的残余钎焊金属和新半导体器件的电极凸点,以使新的半导体器件连接到布线板上。
Description
本发明涉及包括修补步骤的制备电子电路装置的方法,其中,在一旦发现安装在基板上的半导体器件有缺陷的情况下,就要清除有缺陷的半导体器件,并在其上安装新的半导体器件;本发明还涉及在制备方法中制作使残留焊料均匀的夹具板(jig)和传送在制备方法中用的钎焊金属焊膏的夹具板,以及用于实现该制备方法的制备电子电路装置的设备。
在上述提到的修补步骤期间,当把有缺陷的半导体器件(电子元件)从布线板(比如装有半导体器件的基板)拆下时,比如钎焊金属焊膏的残留焊料则保持在布线板的连接部分上(比如焊接区)。由于残留焊料的高度不均匀,所以在这种情况下把新的半导体器件装在布线板上时,就会出现连接故障,引起电路开路等。
按照传统的修补方法,为防止连接故障,采取下面的步骤(1)和(2)。
(1)首先,将可浸润焊料的金属板(比如在其上能够均匀分布焊料的金属板)压在残留焊料上,并在这种状态下加热,以便残留焊料与金属板粘接,从而使布线板上的残留焊料完全清除。
(2)为防止焊接区氧化,把助焊剂涂敷在布线板的焊接区上。通过在大气炉内或空气炉中加热使要重新安装半导体器件的焊接电极凸点熔化,从而使半导体器件连接到布线板上。
例如,在日本特许公开1-209736和8-46351中披露了如上所述的传统实例。
在把半导体器件焊接在布线板上的情况下,通过倒装焊接法使用焊接电极凸点,当半导体器件和布线板的温度膨胀系数存在差别时,会产生下列问题。在通过加热熔化焊接电极凸点时的温度与室温之间的差别,或在半导体器件工作期间的温度与半导体器件不工作时的温度之间的差别,都会造成半导体器件与布线板之间在膨胀和收缩方面的差异(比如热应力)。这可能使焊接电极凸点的连接部分产生应变,导致连接缺陷。因此,由各部件部分的热膨胀系数差引起的焊接电极凸点连接部分的应变降低了产品的可靠性。
在半导体器件与布线板之间没有进行填充的情况下,焊接电极凸点连接部分的应变与按照下面的公式(1)和(2)表示的Coffin·Manson连接疲劳寿命的计算值很好地吻合。为降低连接部分中的最大应变γmax,根据公式(2),应该增加连接部分的高度Hj。为此,应增加焊料量。
Nf=C·f1/3·1/γmax 2·exp(ΔE/KTmax) …(1)
γmax=1/(Dmin/2)2/β·(Vj/π·Hj (1+β))1/β·ΔT·Δα·d …(2)
其中Nf:连接缺陷出现前的循环数
C:比例系数
β:焊料材料常数
K:Boltzmann(波兹曼)常数
f:温度循环频率
Tmax:温度循环的最高温度
Dmin:连接部分的最小直径(比如,图13连接部分的上直径DB1和下直径DB2的较小值)
Δα:布线板与半导体器件之间的温度膨胀系数差
d:聚集的焊料接点与热应力为零的点之间的距离
ΔE:引起疲劳的有效能量
作为参考,图13表示与上述有关的元件。
如上所述,按照传统的修补方法,要完全清除残留焊料,并用仅在焊接电极凸点上的焊料把半导体器件与布线板连接。因此,焊料量较小。这使得要尽量增加连接部分的高度Hj,以便改善产品的可靠性。
本发明的制备电子电路装置的方法包括在进行制备电子电路装置的工艺期间的修补步骤,修补方法是,使由钎焊金属构成并形成在半导体器件的一个主表面的电极凸点,与具有与相应的电极凸点连接的焊接区的用于安装半导体器件的基板对准,并且通过加热熔化电极凸点,从而把半导体器件装在基板上。修补步骤包括:在一旦发现安装的半导体器件有缺陷的情况下,就从基板上清除有缺陷的半导体器件,并把新的半导体器件装在基板上;该修补步骤包括下列步骤:清除保留在已清除有缺陷的半导体器件的基板焊接区上的多余的残余钎焊金属,并在焊接区留下等量均匀的残余钎焊金属;使新半导体器件与基板对准;通过加热熔化已均匀地保留在焊接区和新半导体器件的电极凸点上的残余钎焊金属,从而使新的半导体器件连接到基板。
再有,本发明的制备电子电路装置的方法包括在进行制备电子电路装置的工艺期间的修补步骤,修补方法是,使由钎焊金属构成并形成在半导体器件的一个主表面的电极凸点,与具有与相应的电极凸点连接的焊接区的用于安装半导体器件的基板对准,用加热熔化电极凸点,从而把半导体器件装在基板上,修补步骤包括:在一旦发现安装的半导体器件有缺陷的情况下,就从基板上清除有缺陷的半导体器件,并把新的半导体器件装在基板上;该修补步骤包括下列步骤:清除保留在已清除有缺陷的半导体器件的基板焊接区上的多余的残余钎焊金属,并在焊接区留下一些均匀的残余钎焊金属;把钎焊金属焊膏提供给新的半导体器件电极凸点的顶端;使新半导体器件与基板对准;通过加热熔化已均匀地保留在焊接区的钎焊金属和新半导体器件的电极凸点从而使新的半导体器件连接到基板。
本发明的一个实施例中,保留在焊接区上一等量均匀的残余钎焊金属的高度与残余钎焊金属的表面张力有关。
本发明的另一个实施例中,用灯发射的光加热已均匀保留在焊接区上的残余钎焊金属和新半导体器件的电极凸点。
本发明的另一个实施例中,使用近红外辐射灯作为加热灯。
本发明的另一个实施例中,按预定的间隙将由可浸润焊料的金属构成的板放置于残余钎焊金属之上,加热该板,从而进行清除在已清除了有缺陷的半导体器件的基板焊接区上的残余钎焊金属物并在焊接区上保留一等量均匀的残余钎焊金属的步骤。
本发明的另一个实施例中,预定间隙约为焊接区直径的1/4至1/10。
本发明的另一个实施例中,通过加热按预定速度移动同时保持与残余钎焊金属接触的烙铁,进行清除在已清除有缺陷的半导体器件并在其上保留了一些均匀的残余钎焊金属的基板焊接区上的多余残余钎焊金属物的步骤。
本发明的另一实施例中,在焊接区直径约为150μmφ至800μmφ的情况下,人工移动加热烙铁。
本发明的另一个实施例中,在焊接区直径约为150μmφ至550μmφ的情况下,人工移动加热烙铁。
本发明的另一个实施例中,钎焊金属是易熔焊料(eutectic solder)或把少许添加剂加入易熔焊料而增强其强度的焊料。
本发明的另一个实施例中,半导体器件是带有以区域排布的焊接电极凸点的半导体管壳。
本发明的另一个实施例中,用传送方法完成把钎焊金属焊膏提供给电极凸点顶端的步骤。
本发明的另一个实施例中,在粘合剂中放入与钎焊金属相同的细金属粉末来获得钎焊金属焊膏。
本发明的另一个实施例中,用灯发射的光加热熔化新半导体器件的电极凸点和钎焊金属焊膏。
按照本发明的另一方案,用于制备电子电路装置的使残留焊料均匀的夹具板(jig),包括在板的外周部分上的多个销钉。
再有,在按制备电子电路装置的方法把钎焊金属焊膏提供给电极凸点顶端的夹具板中,在夹具板的中心部分形成扩开的方形或圆形凹槽,槽的深度约为半导体器件电极凸点高度的1/3至1/2左右。
按照本发明的另一方案,在制备电子电路装置的设备中,使由钎焊金属构成并形成在半导体器件的一个主表面的电极凸点与具有用于安装半导体器件的并与相应的电极凸点连接的焊接区的基板对准,通过加热熔化电极凸点,从而把半导体器件装在基板上,其中,在一旦发现安装的半导体器件有缺陷的情况下,就从基板上清除有缺陷的半导体器件,并把新的半导体器件装在基板上;该设备包括:固定基板的托架;固定有缺陷的半导体器件或新的半导体器件的托架;使有缺陷的半导体器件或新的半导体器件与基板对准的对准单元;清除保留在已清除有缺陷的半导体器件的基板的连接部分上的多余钎焊金属残留物的单元,并按在连接部分上的残余钎焊金属的表面张力保留一等量均匀的残余钎焊金属;加热单元,利用加热熔化已对准的新半导体器件的电极凸点,从而把新半导体器件连接到基板上。
另一种制备电子电路装置的设备,使由焊接金属构成并形成在半导体器件的一个主表面的电极凸点与具有用于安装半导体器件并与相应的电极凸点连接的焊接区的基板对准,用加热熔化电极凸点,从而把半导体器件装在基板上,其中,在一旦发现安装的半导体器件有缺陷的情况下,就从基板上清除有缺陷的半导体器件,并把新的半导体器件装在基板上。该设备包括:固定基板的托架;固定有缺陷的半导体器件或新的半导体器件的托架;使有缺陷的半导体器件或新的半导体器件与基板对准的对准单元;清除保留在已清除有缺陷的半导体器件的基板的连接部分上的多余钎焊金属残留物的单元,并按在连接部分上的残余钎焊金属的表面张力保留一等量的残余钎焊金属;把钎焊金属焊膏传送到新半导体器件顶端的夹具板,在夹具板的中心部分形成扩开的方形或圆形凹槽,槽的深度约为半导体器件电极凸点高度的1/3至1/2左右;和加热单元,用加热熔化已对准的新半导体器件的电极凸点,从而把新半导体器件与基板连接。
本发明的另一实施例中,清除在已清除有缺陷的半导体器件的基板连接部分上多余的残余钎焊金属并在连接部分保留一等量的残余钎焊金属的单元是加热烙铁,按预定速度移动热烙铁,同时保持与残余钎焊金属或与使残留焊料均匀的在外周部分带有多个销钉的夹具板接触。
本发明的另一个实施例中,加热单元是近红外灯。
下面,叙述本发明的作用。
如上所述,只保留按照焊料表面张力的一等量的残留焊料,就能利用传送步骤用焊膏设置新的半导体器件。因此,能够保证足够的用于修补半导体器件的焊料。正如Coffin·Manson连接疲劳寿命公式所表示的,增加了连接部分的高度Hj,降低了连接部分中的最大应变γmax,所以不会出现连接错误(比如断路)。因此,能够改善半导体器件的可靠性。
按照半导体器件产品的种类(比如半导体器件和要连接的布线板种类),可省略上述的传送步骤。例如,按照本发明的发明者的实验结果,在把其焊接区节距LP约为0.6mm的半导体器件装在其节距LD约为200μmφ的布线板上的情况下,印制的焊料的高度(比如成形后的残留焊料高度)约为70μmφ。因此,可以确定,在不进行传送步骤的情况下,就可获得可靠的半导体器件。
按照本发明,在清除有缺陷的半导体器件的布线板上保留的残留焊料是有意留下的,而不是完全清除,从而确保足够量的焊料。这种情况下,在清除有缺陷的半导体器件的布线板上保留的残留焊料具有不等的量。可是,利用熔化焊料的表面张力,能够控制残留焊料成为等量和等高度。用加热残留焊料,使用上述使残留焊料均匀的夹具板,能够容易地实现这种控制。
按照传送方法,能够把等量的焊膏迅速提供给半导体器件,而且十分便利。具体地说,使用上述传送钎焊金属焊膏的夹具板有助于焊膏的传送。
按照Coffin·Manson连接疲劳寿命公式,为增加连接部分的高度,应该尽量多地传送焊膏。考虑到在布线板上保留的残留焊料量与其表面张力之间的关系,传送量最好为焊接电极凸点高度的约1/3或以上。如果传送的焊膏量过大,那么如图3A所示(后面将说明),焊膏12就可能与半导体器件20粘附,在焊接电极凸点21之间形成桥23。当形成这种桥23时,如图3B所示,在安装和加热半导体器件20时,桥23与焊接电极凸点21一起回流。然后,熔化的焊料由于其表面张力汇集,形成较大直径的焊接电极凸点24。为防止形成这种焊接电极凸点,应把传送量限定在焊接电极凸点21高度的约1/2,也就是不超过焊接电极凸点21的圆表面。
按照本发明,用于传送钎焊金属焊膏的夹具板的槽的深度规定为焊接电极凸点高度的约1/2至1/3,从而使传送量达到焊接电极凸点21高度的约1/2至1/3。用于把新半导体器件重新接在布线板的加热装置不应该包括过大的外力。具体地说,在没有外力的情况下,已经相互对准的半导体器件和布线板在其位置上不会移位。因此,可以快速和充分地完成修补步骤。由此,按照本发明,使用不包括外力的灯。对于灯,由于下列原因,最好使用近红外灯(IR灯)。在半导体器件中,以硅作为用于电路板的主要材料。硅透射在近红外辐射区域的光(波长约为1至5μm)。当采用波长约为1至5μm的光时,光穿过硅直接和充分地加热焊接电极凸点和焊膏。因此,最好使用能够发射约1至5μm波长发射光的IR灯。
使用易熔焊料或在易熔焊料中添加少量的钎焊金属,就能够改善焊料强度。
因此,本发明的优点在于:(1)提供了制备电子电路装置的方法,该方法能够确保足够的焊料量,以使半导体器件与布线板充分连接,从而增加连接部分的高度,改善产品的可靠性;(2)提供了使残留焊料量均匀的夹具板和在制备方法中使用的传送钎焊金属焊膏的夹具板;和(3)提供了用于实现制备方法的制备电子电路装置的设备。
对于本领域的技术人员来说,参照附图,通过阅读和理解下面的详细叙述,会更明白本发明的这些和其他优点。
图1是表示本发明的制备电子电路装置的方法中的修补步骤流程图。
图2A是表示实现本发明方法的传送焊膏的夹具板的透视图;图2B是表示用传送的焊膏填充夹具板的状态的透视图。
图3A和3B表示传送焊膏过量的情况下不利的情况。
图4A和4B表示传送焊膏的步骤。
图5A是表示实现本发明方法的另一传送焊膏夹具板的透视图;图5B是表示用传送的焊膏填充夹具板的状态的透视图。
图6是表示使残留焊料量均匀的夹具板的透视图。
图7A至图7C表示利用图6所示夹具板使布线板上残留焊料均匀的步骤。
图8A至8C使用另一使残留焊料均匀的夹具板来使残留焊料均匀的步骤。
图9A和9B分别表示本发明采用的半导体器件和布线板。
图10表示本发明采用的布线板的焊接区直径范围的曲线图。
图11是表示本发明制备电子电路装置的设备的透视图。
图12是表示本发明制备电子电路装置的另一设备的透视图。
图13展示Coffin·Manson连接疲劳寿命表达式。
下面,以通过参照附图,说明实施例的方式,来叙述本发明。
实施例1
图1至图7表示本发明的制备电子电路装置的方法。本发明方法的特征在于一修补步骤,下面,参照图1,概要说明该步骤。
首先,在步骤S1中,确定布线板上的半导体器件是否出现缺陷。在步骤S2中,用灯加热有缺陷的半导体器件,以便熔化焊接电极凸点,从而清除布线板上的该半导体器件。
在步骤S3中,在清除有缺陷的半导体器件后,清除布线板上残留的过多残留焊料,以便其上仅留下等量均匀的残留焊料。
在步骤S4中,准备一个新的半导体器件。在步骤S5中,按照传送方法,把焊膏送至器件的焊接电极凸点的顶端,由此准备安装器件。
在步骤S6中,把已传送焊膏的新的半导体器件与在其上保留了均匀的残留焊料的布线板对准。
在步骤S7中,用灯加热已装在布线板上的新的半导体器件,由此熔化焊接电极凸点和焊膏。从而,使半导体器件连接到布线板上。在步骤S8中,完成修补步骤。
在修补步骤期间,由于下列原因,最好使用近红外辐射灯(IR灯)。所选择的作为布线板的材料为硅(Si)。硅在近红外区透射光(波长:约1至5μm)。当使用波长约1至5μm的光时,光穿过硅直接加热焊接电极凸点和充分加热焊膏。因此,最好使用发射波长约1至5μm的IR灯。
例如,利用图2所示的焊膏传送夹具板10进行步骤S5中的传送焊膏的步骤。夹具板10是在其表面的中心部分有扩大的开口形状的槽11的矩形体。设置槽11的目的是使焊膏12具有相同厚度。由于下列理由,使槽11的深度为半导体器件20的焊接电板凸点21的高度的约1/2至1/3较合适(参照图3)。
按照上述Coffin·Manson连接疲劳寿命表达式,为增加连接部分的高度,应该尽量多地传送焊膏12。考虑到在布线板上保留的残留焊料量与其表面张力之间的关系,槽11的深度最好至少约为焊接电极凸点21高度的1/3。如果传送的焊膏量过大,焊膏12就可能与半导体器件20粘附,在焊接电极凸点21之间形成桥23,如图3A所示。当形成这种桥23时,如图3B所示,在安装和加热半导体器件20时,桥23与焊接电极凸点2I一起回流。然后,熔化的焊料由于表面张力而汇集,形成较大直径的焊接电极凸点24。为防止这种情况,应把传送量限定在焊接电极凸点21高度的约1/2,也就是不超过焊接电极凸点21的圆球形的平分面。
实施例1中,把夹具板10的槽11的深度设定为焊接电极凸点21高度的约1/2至1/3,从而把传送量设定为焊接电极凸点21高度的约1/2至1/3。
下面,参照图4A和4B,详细说明用夹具板10传送焊膏的步骤。
首先,把焊膏12放入夹具板10的槽11中,用橡皮滚子或类似物(未示出)压平焊膏12的表面,以便使焊膏12填充槽11。然后,把半导体器件20压在夹具板10上(参照图4A),从而使焊膏12能够粘接在焊接电极凸点21的顶端。接着,升高半导体器件20。于是,完成传送焊膏12的步骤(参照图4B)。
图5A和5B表示另一传送焊膏夹具板的实例。夹具板10′呈盘形,在其中心部分有圆形槽11′。在圆形槽11′的中心部分设置其表面与夹具板10′一样高的凸出部分13。与上述方式一样,把槽11′的深度设定为焊接电极凸点21高度的约1/2至1/3。
图6示出在步骤S3中使布线板上残留焊料量均匀的夹具板。夹具板40由在四角设有销钉42的长方体形状的可浸润焊料的金属板41构成。销钉42有保持与布线板30的恒定间隙的作用(参照图7)。
接着,参照图7A至7C,说明用夹具板40使布线板30上的残留焊料31均匀的步骤。如图7A所示,把夹具板40压在已清除了有缺陷的半导体器件的布线板30上,使销钉42朝下。在这种条件下,加热夹具板40,熔化布线板30上的残留焊料31,使其分散在整个金属板41上(参照图7B)。
图7B中,为简化起见,未示出分散在金属板41上的残留焊料。由于焊料的表面张力,焊料停止在夹具板40上的分散,在连接布线板30用的焊接区33上留下预定焊料量的焊料。此时,如果需要,可以把助焊剂或类似物涂敷在夹具板40或布线板30上。然后,去除夹具板40,均匀等量的焊料32就留在布线板30的焊接区33上(参照图7C)。
为利用焊料的表面张力使残留焊料31均匀,销钉42的高度很重要。已经证实,最好使销钉42的高度约为焊接区33直径的1/4至1/10。
由于本发明采用的是半导体器件,所以使用带有区域阵列的焊接电极凸点的半导体管壳。
实施例2
图8A至8C表示本发明实施例2的制备电子电路装置的方法。实施例2的特征在于在修补步骤期间使残留焊料均匀的方法。实施例2中,使用烙铁使残留焊料均匀。下面,详细说明使残留焊料均匀的步骤。
首先,如图8A所示,使烙铁50位于布线板30上。更具体地说,把烙铁50放置在这样的高度,使其顶端能够与残留焊料31接触。
接着,如图8B所示,加热的烙铁50按恒定速度在水平方向上移动。其中,最好用助焊剂涂敷烙铁50。
当烙铁50移动时,残留焊料31被烙铁50加热熔化,从而分布在烙铁50和焊接区33上。图8B中,为简明起见,未示出烙铁50上的残留焊料。可是,由于焊料的表面张力,焊料停止扩散,在布线板30的焊接区33上留下预定量的焊料(参见图8C)。已经确定,烙铁50最好以约1/10至1秒的时间经过焊接区33。
虽然在本实施例中人工移动烙铁50,但也可用本发明的设备(后面说明)自动地移动它。
如上所述,在利用人工移动烙铁50刮去残留焊料来定形的情况下,需要考虑焊接区直径LD。更具体地说,按照布线板30中焊接区直径LD的尺寸,这种定形方法会造成残留焊料31的变化,而导致出现不期望的状态。焊接区直径LD的优选范围如下所述。
参照图9A和9B,下面说明半导体器件20的焊接电极凸点尺寸HD,焊接电极凸点节距HP和布线板30的焊接区节距LP(类似于电极焊接凸点节距HP)。
电极焊接凸点尺寸HD约为0.2mmφ至0.8mmφ,电极焊接凸点节距Hp和布线板30的焊接区节距LP分别约为0.5mm至1.27mm。
按上述范围使用半导体器件20和布线板30进行实验。图10表示该结果。
在定形后残留焊料的优选高度随焊接区直径LD变化(例如,如图10所示,在焊接区直径LD约为150μmφ情况下,残留焊料的高度最好约为55μm至90μm;在焊接区直径LD约为250μmφ情况下,残留焊料的高度最好约为60μm至100μm)。按照实验结果,最好确定焊接区直径LD在约150μmφ至550μmφ的范围内。
对于布线板30的焊接区直径LD为大于φ800μm的情况,最好不用烙铁刮去焊料来定形残留焊料31。已经确定,在这种情况下分散的焊膏较好。当焊接区直径LD超过约φ1mm时,残留焊料31分布的最小值势必减小,其变化势必增大。于是,可以确定,不期望焊接区直径超过约1mmφ。
实施例3
实施例1采用将焊膏传送到新的半导体器件20的焊接电极凸点21的工艺方法,从而增加了连接部分的高度。可是,按照产品的种类(比如半导体器件20和要连接的布线板30的种类),可以不需要这种传送步骤。更具体地说,可以实现省略了实施例1中步骤S5(传送步骤)的修补步骤。
按照本发明发明者的实验结果,例如,在把焊接区节距LP约为0.6mm的半导体器件20装在焊接区直径LD约为200μmφ的布线板30上的情况下,印制的焊料的高度(即定形之后残留焊料的高度)约为70μm。因此,如图10所示,可以确定,即使在没有进行步骤S5的情况下,也能完成可靠的修补步骤。
下面的表1表示按照本发明方法修补的半导体器件的温度循环可靠性评价的实验结果和没有缺陷的半导体器件的温度循环可靠性评价。其中,半导体器件的焊接区节距为0.6mm。可以确定,修补的半导体器件的可靠性与没有缺陷的半导体器件的可靠性相同。
表1
温度循环可靠性评价 | |||
开始 | 100 | 200 | |
无缺陷的半导体器件的0.6mm节距已修补的半导体器件的0.6mm节距 | 良好 | 良好 | 差 |
良好 | 良好 | 差 |
下面的表2表示按照本发明修补的半导体器件出现断路与用常规修补方法(也就是说,在不传送焊膏的情况下,通过完全清除残留焊料来修补半导体器件)的半导体器件出现断路的情况的比较结果。其中,半导体器件的焊接区节距为0.8mm。
表2
温度循环 | 100 200 300 400 500 |
本发明的方法 | 良好 良好 良好 良好 良好 |
常规方法 | 4/5差 5/5差 |
正如表2所示,按照本发明的方法,能够完全避免按照常规方法会出现的连接缺陷。
按本发明的实验如下进行:
使用包括约0.3mmφ焊接区直径LD的布线板30。焊接区涂敷约2至3μm的化学镀镍(electroless Ni)和平镀金(flush Au plating)。
作为IR灯,使用由Phoenix Elect.公司制造的由钨丝形成的功率约225瓦的近红外灯。由IR灯发射的光用抛物面镜聚光,以便在布线板和半导体器件的表面附近有聚焦点。用IR灯在约1分钟内可把半导体器件加热到250℃。
实验中使用了粘度为300,000泊(cp)的焊膏(RMA 501-88-3-30,由Alphametals Co.,Ltd制造),利用把带有RMA型助焊剂的易熔焊料(Sn 63%和Pb37%)揉碎成细小的焊料粉末(平均尺寸:30μm)来获得该焊膏。
把焊膏放入图2A和2B所示的夹具板10中,该夹具板由在SUS 301板(厚度:约6mm)中铣成深度约为150μm的槽而制成。用厚度约为1.1mm的玻璃板(7027,Corning制造)刮平焊膏,以便把槽填平。
把半导体器件20连在真空夹子上(392,Hakko Kinzoku Co.,Ltd制造)。将半导体器件20人工压在厚度约50μm的扁平的焊膏上。使半导体器件20至少停留2分钟,以便与焊膏紧密接触。
用夹具板40清除残留焊料,在该夹具板中把四个内螺纹(ISO·M2螺纹)设在黄铜板上(厚度:约1.0mm),使其端部伸出黄铜板约0.1mm,以形成销钉42(参照图6)。用浸焊法薄焊黄铜板。进一步用刷子将助焊剂(RF-350-RAM,Nihon Alumit Co.,Ltd.制造)涂敷在焊接的黄铜板上。
把夹具板40放在残留焊料上,用IR灯按约1225瓦/分加热。残留焊料就呈现如图7C和8C所示的厚度约为50至70μm的小山包形状。
不用夹具板40,而用刷子把助焊剂(RF-350-RMA)涂敷在残留焊料上,用温度300℃至320℃的烙铁(926M,Hakko Kinzoku Co.,Ltd.制造)的铁尖端部(900M-TI-C)摩擦残留焊料。在此情况下,也可获得类似于上述的残留焊料。
把已被传送了焊膏的半导体器件20附在真空夹子上,在布线板30上放置视觉对准标记。
用IR灯加热放在布线板30上的半导体器件20,以便使残留焊料、焊接电极凸点21和传送的焊膏熔化。于是,半导体器件20连接到布线板30。当焊料熔化时,由于表面张力,即使焊料移动,焊料也会返回到正常位置(自对准作用)。因此,在焊接区直径约为0.3mm的情况下,焊接区可调整约±0.15mm。由此,可以确定,半导体器件20能够通过视觉对准安装在布线板30上。
实施例4
图11表示本发明实施例4的制备电子电路装置的设备。该设备包括:固定布线板30和能够精确移动以进行对准的基台130、焊膏传送夹具板10、用于拆除有缺陷的半导体器件20′并使残留焊料均匀和安装新半导体器件20的加热灯160(IR灯)、用于固定和移动半导体器件20的拾取器具170、用于对准的光学系统190和用于确认对准的监视器TV191。
拾取器具170、加热灯160和用于对准的光学系统190能够水平移动。比如,利用直线电机(1inear motor)(未示出),就能够移动它们。
上述设备中,在修补步骤期间,把灯160移在有缺陷的半导体器件20’上。将灯160点亮以加热有缺陷的半导体器件20′。结果,连接部分的焊料被加热熔化,从而能够清除有缺陷的半导体器件20′。
接着,移动拾取器具170使其位于有缺陷的半导体器件20′上,并与其连接,从而清除有缺陷的半导体器件20′。把上述夹具板40放在布线板30上所留下的残留焊料31上,并用灯160加热,从而使残留焊料均匀。
接着,使新的半导体器件20附着在拾取器具170上。此时,将焊膏12放入焊膏传送夹具板10的槽11中,并用刮板或类似物压平。附着在拾取器具170上的半导体器件20压向填充了焊膏12的焊膏传送夹具板10的槽11,从而把焊膏12传送到半导体器件20的焊接电极凸点21的端部。
然后,拾取器具170移到布线板30上,与半导体器件20连接。利用用于对准的光学系统190和用于确认对准的监视器TV191,移动基台130,使半导体器件20与布线板30对准,由此把半导体器件20装在布线板30上。此后,用灯160加热半导体器件20,从而加热和熔化焊料,把半导体器件20与布线板30连接起来。
实施例5
图12表示本发明实施例5的制备电子电路装置的设备。该设备与实施例4设备的差别仅在于设置了烙铁50和用于水平移动烙铁50的移动机构51。因此,用相同的参考标号表示相同的部分。这里,省略了在实施例4中已说明的部分的叙述。例如,用直线电机操作移动机构51。
本发明的设备中,在修补步骤期间,把灯160移到有缺陷的半导体器件20’上并加热它,由此加热并熔化连接部分的焊料。拾取器具170移到有缺陷的半导体器件20′上,并吸附它,从而清除有缺陷的半导体器件20′。然后,使烙铁50与布线板30接触。在这种条件下操作移动机构51,从而使布线板30上的残留焊料均匀。
接着,将新的半导体器件20吸附于拾取器具170。将半导体器件20压向填充了焊膏12的焊膏传送夹具板10的槽11。从而,把焊膏传送到半导体器件20的焊接电极凸点21的端部。
此后,按与上述同样的方式,使布线板30与半导体器件20对准,从而把半导体器件20装在布线板30上。然后用灯160加热半导体器件20,以便与布线板30连接。
实施例5的设备中,关键是烙铁50的移动机构51与烙铁50相连。可是,由于移动速度的裕度较大,所以在不使用移动机构51的情况下可以人工移动烙铁50。这种情况下,设备有与实施例4相同的结构。
按照本发明,由于其表面张力,不仅在布线板上留下等量均匀的残留焊料,还使新的半导体器件带有焊膏。因此,能够确保用于修补的半导体器件有足够量的焊料。按照Coffin·Manson连接疲劳寿命表达式,这样就增加了连接部分的高度Hj和降低了连接部分中的最大应变γmax,于是不会出现连接缺陷(比如断路)。因此,能够改善半导体器件的可靠性。
根据产品的种类(比如半导体器件和要连接的布线板的种类),可以省略上述传送步骤。
按照本发明,在已清除了有缺陷的半导体器件的布线板上有意地保留了残留焊料,取代了完全的清除,由此确保了足够量的焊料。这种情况下,在已清除有缺陷的半导体器件的布线板上的残留焊料是不均匀的。可是,利用熔化焊料的表面张力,可以控制残留焊料,达到均匀的量和均匀的高度。通过加热残留焊料,使用本发明的使残留焊料均匀的夹具板,可以容易地进行这种控制。
按照传送方法,可以容易地把等量的焊膏提供给半导体器件,这种方法十分便利。具体地说,使用上述用于传送钎焊金属焊膏的夹具板有助于焊膏的传送。
按照Coffin·Manson连接疲劳寿命表达式,为增加连接部分的高度,应该尽可能多的传送焊膏。考虑到在布线板上保留的残留焊料量和其表面张力的关系,传送量最好为焊接电极凸点高度的约1/3以上。如果焊膏量传送得过多,在焊接电极凸点之间就会形成桥。当形成这种桥时,熔化的焊料因其表面张力而汇集,形成有较大直径的焊接电极凸点。为防止形成这种焊接电极凸点,应该把传送量限定在焊接电极凸点高度的约1/2内,即不超过焊接电极凸点圆球形的平分面的值。
按照本发明,传送钎焊金属焊膏夹具板的槽深度最好为焊接电极凸点高度的约1/2至1/3,从而使传送量约为焊接电极凸点高度的约1/2至1/3。
把新的半导体器件与布线板重接的加热装置不应该产生任何过大的外力。具体地说,在没有过大外力的情况下,已经相互调整的半导体器件和布线板不会在其位置上移动。因此,能够更容易和有效地完成修补步骤。由此,按照本发明,使用不产生外力的灯。作为灯,由于下列原因,最好使用近红外灯(IR灯)。在半导体器件中,把硅作为选择电路板的材料。硅透射近红外区(波长:约1至5μm)的光。当使用波长约1至5μm的光时,光穿过硅直接有效地加热焊接电极凸点和焊膏。因此,最好使用能够发射波长约1至5μm光的IR灯。
使用易熔焊料或在其内添加少许钎焊金属的易熔焊料,能够改善焊料强度。
对于本领域的技术人员来说,在不脱离本发明的范围和精神的情况下,显然可以进行各种变化。因此,后面权利要求的范围并不意味着受限于前面的叙述,而是如权利要求所广泛解释的范围。
Claims (32)
1.一种包括修补步骤的制备电子电路装置的方法,在进行制备电子电路装置的工艺期间,使由钎焊金属构成并形成在半导体器件的一个主表面的电极凸点与具有与相应的电极凸点连接的焊接区的用于安装半导体器件的基板对准,通过加热熔化电极凸点,从而把半导体器件装在基板上,修补步骤包括:在一旦发现安装的半导体器件有缺陷的情况下,就从基板上清除有缺陷的半导体器件,并把新的半导体器件装在基板上;
该修补步骤包括下列步骤:
清除保留在已清除了有缺陷的半导体器件的基板焊接区上的多余的残余钎焊金属,并在焊接区留下等量均匀的残余钎焊金属;
使新半导体器件与基板对准;
通过加热熔化已均匀地保留在焊接区上的残余钎焊金属和新半导体器件的电极凸点,从而使新的半导体器件连接到基板。
2.如权利要求1所述的制备电子电路装置的方法,其中,在焊接区上等量均匀的残余钎焊金属具有与残余钎焊金属的表面张力一致的高度。
3.如权利要求1所述的制备电子电路装置的方法,其中,用灯发射的光加热熔化已均匀地保留在焊接区上的残余钎焊金属和新半导体器件电极凸点。
4.如权利要求3所述的制备电子电路装置的方法,其中,使用近红外灯作为加热用灯。
5.如权利要求1所述的制备电子电路装置的方法,其中,按预定的间隙将由可浸润焊料的金属构成的板放置于残余钎焊金属上,并加热该板,从而进行清除已清除了有缺陷的半导体器件的基板焊接区上的多余的残余钎焊金属物并在其上保留等量均匀的残余钎焊金属的步骤。
6.如权利要求5所述的制备电子电路装置的方法,其中,所述预定间隙约为焊接区直径的1/4至1/10。
7.如权利要求1所述的制备电子电路装置的方法,其中,用加热按预定速度移动同时保持与残余钎焊金属接触的烙铁,来进行清除在已清除了有缺陷的半导体器件的基板焊接区上的多余的残余钎焊金属物并在其上保留等量均匀的残余钎焊金属的步骤。
8.如权利要求7所述的制备电子电路装置的方法,其中,在焊接区直径约为150μmφ至800μmφ的情况下,人工移动热烙铁。
9.如权利要求7所述的制备电子电路装置的方法,其中,在焊接区直径约为150μmφ至550μmφ的情况下,人工移动热烙铁。
10.如权利要求1所述的制备电子电路装置的方法,其中,所述钎焊金属是易熔焊料或把少许添加剂加入易熔焊料而增强其强度的焊料。
11.如权利要求1所述的制备电子电路装置的方法,其中,所述半导体器件是带有区域阵列的焊接电极凸点的半导体管壳。
12.一种包括修补步骤的制备电子电路装置的方法,在制备电子电路装置的工艺期间,使由钎焊金属构成并形成在半导体器件的一个主表面的电极凸点与具有与相应的电极凸点连接的焊接区的用于安装半导体器件的基板对准,通过加热熔化电极凸点,从而把半导体器件装在基板上,修补步骤包括:在一旦发现安装的半导体器件有缺陷的情况下,就从基板上清除有缺陷的半导体器件,并把新的半导体器件装在基板上;
该修补步骤包括下列步骤:
清除保留在已清除有缺陷的半导体器件的基板焊接区上的多余的残余钎焊金属,并在焊接区留下等量均匀的残余钎焊金属;
把钎焊金属焊膏提供给新半导体器件电极凸点的顶端;
使新半导体器件与基板对准;和
通过加热熔化已均匀地保留在焊接区上的残余钎焊金属和新半导体器件的电极凸点,从而使新的半导体器件连接到基板上。
13.如权利要求12所述的制备电子电路装置的方法,其中,焊接区上等量均匀保留的钎焊金属焊膏高度与钎焊金属焊膏表面张力有关。
14.如权利要求12所述的制备电子电路装置的方法,其中,用传送方法完成把钎焊金属焊膏提供给电极凸点端部的步骤。
15.如权利要求12所述的制备电子电路装置的方法,其中,通过将与钎焊金属相同种类的细金属粉分散在粘合剂中来获得钎焊金属焊膏。
16.如权利要求12所述的制备电子电路装置的方法,其中,用灯发射的光加热熔化新半导体器件电极凸点和钎焊金属焊膏。
17.如权利要求16所述的制备电子电路装置的方法,其中,使用近红外灯作为加热用灯。
18.如权利要求12所述的制备电子电路装置的方法,其中,按预定的间隙将由可浸润焊料的金属构成的板放置于残余钎焊金属之上,并加热该板,从而进行清除在已清除了有缺陷的半导体器件的基板焊接区上的多余的残余钎焊金属物并在其上保留等量均匀的残余钎焊金属的步骤。
19.如权利要求18所述的制备电子电路装置的方法,其中,预定间隙约为焊接区直径的1/4至1/10。
20.如权利要求12所述的制备电子电路装置的方法,其中,加热按预定速度移动同时保持与残余钎焊金属接触的烙铁,从而进行清除在已清除有缺陷的半导体器件的基板焊接区上的多余的残余钎焊金属物并在其上保留等量均匀的残余钎焊金属的步骤。
21.如权利要求20所述的制备电子电路装置的方法,其中,在焊接区直径约为150μmφ至800μmφ的情况下,人工移动热烙铁。
22.如权利要求20所述的制备电子电路装置的方法,其中,在焊接区直径约为150μmφ至550μmφ的情况下,人工移动热烙铁。
23.如权利要求12所述的制备电子电路装置的方法,其中,所述钎焊金属是易熔焊料或把少许添加剂加入易熔焊料而增强其强度的焊料。
24.如权利要求12所述的制备电子电路装置的方法,其中,所述半导体器件是带有区域阵列的焊接电极凸点的半导体管壳。
25.一种用于制备电子电路装置的使残留焊料均匀的夹具板,包括在其板的外周部分上的多个销钉。
26.一种在制备电子电路装置的方法中把钎焊金属焊膏提供给半导体器件的电极凸点端部的夹具板,
其中,在夹具板的中心部分形成扩开的方形或圆形凹槽,槽的深度约为半导体器件电极凸点高度的1/3至1/2左右。
27.一种制备电子电路装置的设备,使由钎焊金属构成并形成在半导体器件的一个主表面的电极凸点与具有用于安装半导体器件的与相应的电极凸点连接的焊接区的基板对准,并用加热熔化电极凸点,从而把半导体器件装在基板上,其中,在一旦发现安装的半导体器件有缺陷的情况下,就从基板上清除有缺陷的半导体器件,并把新的半导体器件装在基板上;
该设备包括:
固定基板的托架;
固定有缺陷的半导体器件或新的半导体器件的托架;
使有缺陷的半导体器件或新的半导体器件与基板对准的对准单元;
清除保留在已清除有缺陷的半导体器件的基板的连接部分上的多余的钎焊金属残留物的单元,按在连接部分上的残余钎焊金属的表面张力来保留等量均匀的残余钎焊金属;和
加热单元,利用加热熔化已对准的新半导体器件的电极凸点,从而把新半导体器件连接到基板上。
28.如权利要求27所述的制备电子电路装置的设备,其中,清除在已清除有缺陷的半导体器件的基板连接部分上的多余的残余钎焊金属并把一等量均匀的残余钎焊金属留在连接部分上的单元是热烙铁,该热烙铁按预定速度移动,同时保持与残余钎焊金属接触;或是用于使残留焊料均匀的并在外周部分上包括多个销钉的夹具板。
29.如权利要求27所述的制备电子电路装置的设备,其中,加热单元是近红外灯。
30.一种制备电子电路装置的设备,使由钎焊金属构成并形成在半导体器件的一个主表面的电极凸点与具有用于安装半导体器件并与相应的电极凸点连接的焊接区的基板对准,通过加热熔化电极凸点,从而把半导体器件装在基板上,其中,在一旦发现安装的半导体器件有缺陷的情况下,就从基板上清除有缺陷的半导体器件,并把新的半导体器件装在基板上;
该设备包括:
固定基板的托架;
固定有缺陷的半导体器件或新的半导体器件的托架;
使有缺陷的半导体器件或新的半导体器件与基板对准的对准单元;
清除保留在已清除有缺陷的半导体器件的基板的连接部分上的多余的钎焊金属残留物的单元,按在连接部分上的残余钎焊金属的表面张力来保留等量均匀的残余钎焊金属;
把钎焊金属焊膏传送到新半导体器件顶端的夹具板,在夹具板的中心部分形成扩开的方形或圆形凹槽,槽的深度约为半导体器件电极凸点高度的1/3至1/2左右;和
加热单元,用加热熔化已对准的新半导体器件的电极凸点,从而把新半导体器件与基板连接。
31.如权利要求30所述的制备电子电路装置的设备,其中,清除在已清除有缺陷的半导体器件的基板连接部分上多余的残余钎焊金属并在连接部分保留等量均匀的残余钎焊金属的单元是热烙铁,其按预定速度移动,同时保持与残余钎焊金属接触;或是使残留焊料均匀的在外周部分带有多个销钉的夹具板。
32.如权利要求30所述的制备电子电路装置的设备,其中,加热单元是近红外灯。
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JP316555/1996 | 1996-11-27 | ||
JP31655596A JP3279940B2 (ja) | 1996-11-27 | 1996-11-27 | 電子回路装置の製造方法、半田残渣均一化治具、金属ロウペースト転写用治具及び電子回路装置の製造装置 |
JP316555/96 | 1996-11-27 |
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CN1183706A true CN1183706A (zh) | 1998-06-03 |
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Application Number | Title | Priority Date | Filing Date |
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CN97126212A Expired - Fee Related CN1101642C (zh) | 1996-11-27 | 1997-11-27 | 制备电路装置的方法及设备 |
Country Status (7)
Country | Link |
---|---|
US (1) | US6062460A (zh) |
EP (1) | EP0845807B1 (zh) |
JP (1) | JP3279940B2 (zh) |
KR (1) | KR100279133B1 (zh) |
CN (1) | CN1101642C (zh) |
DE (1) | DE69718755T2 (zh) |
TW (1) | TW422752B (zh) |
Cited By (2)
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CN101609793B (zh) * | 2009-06-30 | 2011-07-27 | 中国航空工业集团公司洛阳电光设备研究所 | Bga器件漏印工装及印制板bga器件的更新焊接方法 |
CN109904086A (zh) * | 2017-12-11 | 2019-06-18 | 台湾爱司帝科技股份有限公司 | 半导体晶片修补方法以及半导体晶片修补装置 |
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JP3239335B2 (ja) | 1999-08-18 | 2001-12-17 | インターナショナル・ビジネス・マシーンズ・コーポレーション | 電気的接続用構造体の形成方法およびはんだ転写用基板 |
JP3334693B2 (ja) * | 1999-10-08 | 2002-10-15 | 日本電気株式会社 | 半導体装置の製造方法 |
KR100528084B1 (ko) * | 2000-05-17 | 2005-11-15 | 히다치 가세고교 가부시끼가이샤 | 회로접속부의 보수방법 및 그 방법으로 회로를 보수한 회로단자의 접속구조 및 접속방법 |
US6509318B1 (en) | 2000-09-29 | 2003-01-21 | The Regents Of The University Of California | TGF-B inhibitors and methods |
US20030019576A1 (en) * | 2001-06-27 | 2003-01-30 | Loctite Corporation | Electronic component removal method through application of infrared radiation |
US6637641B1 (en) * | 2002-05-06 | 2003-10-28 | Emc Corporation | Systems and methods for manufacturing a circuit board |
US6910615B2 (en) * | 2003-03-27 | 2005-06-28 | International Business Machines Corporation | Solder reflow type electrical apparatus packaging having integrated circuit and discrete components |
KR100542552B1 (ko) | 2003-08-21 | 2006-01-11 | 삼성전자주식회사 | 인쇄회로기판, 및 이 인쇄회로기판을 갖는 화상기록장치 |
JP2007059652A (ja) * | 2005-08-25 | 2007-03-08 | Matsushita Electric Ind Co Ltd | 電子部品実装方法 |
JP4799997B2 (ja) * | 2005-10-25 | 2011-10-26 | 富士通株式会社 | 電子機器用プリント板の製造方法およびこれを用いた電子機器 |
KR100807478B1 (ko) | 2007-03-06 | 2008-02-25 | 삼성전기주식회사 | 솔더 형성 방법 및 솔더 형성용 캡 |
US8371497B2 (en) * | 2009-06-11 | 2013-02-12 | Qualcomm Incorporated | Method for manufacturing tight pitch, flip chip integrated circuit packages |
JP5726581B2 (ja) * | 2011-03-16 | 2015-06-03 | 富士機械製造株式会社 | 電子部品リペア機および生産ライン |
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JP2015220353A (ja) * | 2014-05-19 | 2015-12-07 | 富士通株式会社 | 電子部品の取り付け方法及びハンダペーストの転写方法並びに電子部品の取り付け装置 |
US10362720B2 (en) | 2014-08-06 | 2019-07-23 | Greene Lyon Group, Inc. | Rotational removal of electronic chips and other components from printed wire boards using liquid heat media |
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-
1996
- 1996-11-27 JP JP31655596A patent/JP3279940B2/ja not_active Expired - Fee Related
-
1997
- 1997-11-14 TW TW086116999A patent/TW422752B/zh not_active IP Right Cessation
- 1997-11-17 EP EP97120112A patent/EP0845807B1/en not_active Expired - Lifetime
- 1997-11-17 DE DE69718755T patent/DE69718755T2/de not_active Expired - Fee Related
- 1997-11-17 US US08/971,985 patent/US6062460A/en not_active Expired - Fee Related
- 1997-11-26 KR KR1019970062990A patent/KR100279133B1/ko not_active IP Right Cessation
- 1997-11-27 CN CN97126212A patent/CN1101642C/zh not_active Expired - Fee Related
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101609793B (zh) * | 2009-06-30 | 2011-07-27 | 中国航空工业集团公司洛阳电光设备研究所 | Bga器件漏印工装及印制板bga器件的更新焊接方法 |
CN109904086A (zh) * | 2017-12-11 | 2019-06-18 | 台湾爱司帝科技股份有限公司 | 半导体晶片修补方法以及半导体晶片修补装置 |
Also Published As
Publication number | Publication date |
---|---|
DE69718755T2 (de) | 2004-01-08 |
JP3279940B2 (ja) | 2002-04-30 |
KR100279133B1 (ko) | 2001-02-01 |
JPH10163624A (ja) | 1998-06-19 |
KR19980042767A (ko) | 1998-08-17 |
EP0845807B1 (en) | 2003-01-29 |
US6062460A (en) | 2000-05-16 |
EP0845807A2 (en) | 1998-06-03 |
EP0845807A3 (en) | 1999-04-07 |
TW422752B (en) | 2001-02-21 |
CN1101642C (zh) | 2003-02-12 |
DE69718755D1 (de) | 2003-03-06 |
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