CN117747422B - Low-stress deep trench polycrystalline gate and preparation method thereof - Google Patents
Low-stress deep trench polycrystalline gate and preparation method thereof Download PDFInfo
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- CN117747422B CN117747422B CN202410193083.4A CN202410193083A CN117747422B CN 117747422 B CN117747422 B CN 117747422B CN 202410193083 A CN202410193083 A CN 202410193083A CN 117747422 B CN117747422 B CN 117747422B
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- 238000002360 preparation method Methods 0.000 title claims abstract description 16
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 84
- 229920005591 polysilicon Polymers 0.000 claims abstract description 75
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 23
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 23
- 239000010703 silicon Substances 0.000 claims abstract description 23
- 238000000137 annealing Methods 0.000 claims abstract description 20
- 238000000034 method Methods 0.000 claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 238000005530 etching Methods 0.000 claims abstract description 4
- 239000000463 material Substances 0.000 claims abstract description 4
- 238000007254 oxidation reaction Methods 0.000 claims description 10
- 230000003647 oxidation Effects 0.000 claims description 5
- 230000001590 oxidative effect Effects 0.000 claims 2
- 238000011049 filling Methods 0.000 abstract description 7
- 235000012431 wafers Nutrition 0.000 abstract description 6
- 238000004519 manufacturing process Methods 0.000 abstract description 3
- 239000010408 film Substances 0.000 description 30
- 238000010586 diagram Methods 0.000 description 7
- 239000011265 semifinished product Substances 0.000 description 7
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 4
- 238000000151 deposition Methods 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 230000004927 fusion Effects 0.000 description 3
- 230000006978 adaptation Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000009347 mechanical transmission Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000010992 reflux Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
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- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention relates to the technical field of integrated circuit manufacturing, in particular to a low-stress deep trench polycrystalline gate and a preparation method thereof, which solve the problem that silicon wafers are seriously warped when the deep and wide trench polycrystalline gate is prepared by the existing method, and the preparation method comprises the following steps: etching a groove on a silicon substrate, and growing a gate oxide layer in the groove; preparing a doped polysilicon film in the groove and on the gate oxide layer; preparing an undoped polysilicon film in the groove and on the doped polysilicon layer; forming a first oxide layer at the groove opening, and annealing the doped polycrystalline silicon film and the undoped polycrystalline silicon film; removing the first oxide layer; preparing an upper doped polysilicon layer in the groove to form a grid, wherein the doped polysilicon layer can be filled with doped polysilicon material; and forming a second oxide layer on the doped polysilicon layer, and annealing the polysilicon. The invention is suitable for filling the polycrystalline gate of the deep and wide grooves, reduces the stress of the silicon substrate, improves the warpage of the silicon substrate, and improves the consistency of the center and the edge of the silicon substrate.
Description
Technical Field
The invention relates to the technical field of integrated circuit manufacturing, in particular to a low-stress deep trench polycrystalline gate and a preparation method thereof.
Background
In various device structures of semiconductors, the trench structure is widely applied due to the unique characteristics of performance and electrical parameters, and for various high-power devices such as IGBT, shielded gate MOS and the like, the gate filling of a large-size deep trench is widely applied in the devices, and the current gate manufacturing method for the devices is to deposit polysilicon as a gate in one step after the growth of a gate oxide layer. The polycrystalline silicon has great positive stress, so that the warping of the silicon wafer is great, particularly under the conditions of deeper grooves and larger widths, the problem of stress is more remarkable, the larger the stress is, the larger the warping degree of the silicon wafer is, the processing of subsequent wafers such as the vacuum mechanical transmission of various devices and the processing consistency of the center and the edge are greatly influenced, the cracking is seriously caused to be scrapped, and even the chamber components of the processing devices are damaged. Therefore, a new preparation method is needed to prepare a poly gate of a low stress deep trench.
Disclosure of Invention
The invention provides a low-stress deep trench polycrystalline gate and a preparation method thereof, aiming at solving the problem that the silicon wafer is seriously warped when the existing preparation method is used for preparing the deep and wide trench polycrystalline gate.
The technical scheme adopted by the invention for solving the technical problems is as follows:
a preparation method of a low-stress deep trench polycrystalline gate comprises the following steps:
s1, etching a groove on a silicon substrate, and growing a gate oxide layer in the groove;
s2, preparing a doped polysilicon film in the groove and on the gate oxide layer;
s3, preparing an undoped polysilicon film in the groove and on the doped polysilicon layer;
s4, forming a first oxide layer at the groove opening, and annealing the doped polycrystalline silicon film and the undoped polycrystalline silicon film;
s5, removing the first oxide layer;
s6, preparing an upper doped polysilicon layer in the groove to form a grid, wherein the doped polysilicon layer can be filled with doped polysilicon materials;
and S7, forming a second oxide layer on the doped polysilicon layer, and annealing the polysilicon.
The low-stress deep trench polycrystalline gate is prepared by adopting the preparation method of the low-stress deep trench polycrystalline gate.
The beneficial effects of the invention are as follows:
the low-stress deep trench polycrystalline gate and the preparation method thereof are suitable for filling the polycrystalline gate of the deep and wide trenches, reduce the stress of the silicon substrate, improve the warpage of the silicon substrate, have small warpage degree and improve the consistency of the center and the edge of the silicon substrate.
Drawings
Fig. 1 is a flow chart of a method for preparing a low stress deep trench poly gate according to the present invention.
Fig. 2 is a block diagram of a semi-finished product obtained by S1 of the method for preparing a low stress deep trench poly gate according to the present invention.
Fig. 3 is a block diagram of a semi-finished product obtained in S2 of the method for preparing a low stress deep trench poly gate according to the present invention.
Fig. 4 is a block diagram of a semi-finished product obtained in S3 of the method for preparing a low stress deep trench poly gate according to the present invention.
Fig. 5 is a block diagram of a semi-finished product obtained in S4 of the method for preparing a low stress deep trench poly gate according to the present invention.
Fig. 6 is a block diagram of a semi-finished product obtained in S5 of the method for preparing a low stress deep trench poly gate according to the present invention.
Fig. 7 is a block diagram of a semi-finished product obtained in S6 of the method for preparing a low stress deep trench poly gate according to the present invention.
Fig. 8 is a block diagram of a semi-finished product obtained in S7 of the method for preparing a low stress deep trench poly gate according to the present invention.
Detailed Description
In order that the above-recited objects, features and advantages of the present invention will be more clearly understood, a more particular description of the invention will be rendered by reference to the appended drawings and appended detailed description.
A preparation method of a low-stress deep trench polycrystalline gate, the preparation flow is as shown in figure 1, comprises the following steps:
s1, etching a groove on a silicon substrate, and growing a gate oxide layer in the groove;
the trench is etched using conventional techniques and a gate oxide layer is grown in the trench as shown in fig. 2.
S2, forming a doped polysilicon film in the groove and on the gate oxide layer;
a doped polysilicon film is obtained by means of deposition, as in fig. 3. As an embodiment, a doped polysilicon film with a certain thickness is formed on the gate oxide layer by using an LPCVD (low pressure chemical vapor deposition) process, and the thickness of the doped polysilicon film can be set according to the width of the trench, and as a preferred embodiment, it is ensured that only 10% of the width of the trench is filled, that is, the thickness of the doped polysilicon film is 10% of the width of the trench, then the sum of the doped polysilicon films on both sides of the trench is 20% of the width of the trench, a gap is left in the trench, and a thin film with high doping concentration is used for the polysilicon deposition.
S3, forming an undoped polysilicon film in the groove and on the doped polysilicon layer;
undoped polysilicon films are obtained by deposition, as an example, using an LPCVD (low pressure chemical vapor deposition) process.
As an example, the thickness of the undoped polysilicon film deposited is the same as the thickness of the doped polysilicon film, which is also set to 10% of the trench width, as shown in fig. 4.
S4, forming a first oxide layer at the groove opening, and annealing the doped polycrystalline silicon film and the undoped polycrystalline silicon film, as shown in FIG. 5;
the low-temperature oxyhydrogen diffusion and annealing process is adopted, specifically, a silicon substrate is placed in a furnace tube for oxidization and annealing, the oxidization temperature is 750-850 ℃, the oxidization time is 30-60 minutes, a first oxidization layer is formed on an undoped polysilicon film positioned at a groove opening part through oxidization, meanwhile, the annealing is also carried out on polycrystal (doped polysilicon film and undoped polysilicon film), so that the concentration of polycrystal in the groove is consistent, the reflux collapse effect is achieved, the width difference between the bottom of the groove and the groove opening is reduced, and the stress of polycrystal is also reduced. And (3) annealing the doped polysilicon film in the step (S4) to obtain a doped polysilicon film I with fused concentration, and annealing the undoped polysilicon film in the step (S4) to obtain an undoped polysilicon film I with fused concentration.
S5, as shown in FIG. 6, removing the first oxide layer; the polycrystalline filling morphology of the groove opening is improved;
s6, preparing an upper doped polysilicon layer in the groove to form a grid, wherein the doped polysilicon layer can be filled with doped polysilicon material, as shown in FIG. 7;
and (5) filling doped polycrystal in the groove on the silicon substrate obtained in the step (S5), and completely filling the whole groove to form gate polycrystal. As an embodiment, the doping type of the doped polysilicon layer is the same as the doping type of the doped polysilicon film in S2, and the doping concentration of the doped polysilicon layer is different from the doping concentration of the doped polysilicon film in S2. As another embodiment, the doping type and doping concentration of the doped polysilicon layer are the same as those of the doped polysilicon film in S2.
S7, forming a second oxide layer on the doped polysilicon layer, and annealing the polysilicon;
that is, the process is again performed at S4, the polycrystalline stress at S6 is improved, and the stress of the third layer of the polycrystalline is released, and the resulting structure is shown in fig. 8.
And (3) annealing the doped polysilicon film in S7 to obtain a doped polysilicon film II after concentration fusion, annealing the undoped polysilicon film in S7 to obtain an undoped polysilicon film II after concentration fusion, and annealing the doped polysilicon layer in S7 to obtain a doped polysilicon layer I after concentration fusion. The stress of the polycrystalline layer is released under the low-temperature oxidation atmosphere, so that the warping degree of the silicon wafer is greatly improved.
The low-stress deep trench polycrystalline gate prepared by the preparation method of the low-stress deep trench polycrystalline gate has small warping degree of the silicon substrate.
The preparation method is suitable for filling the polycrystalline grid of the deep groove wide groove, reduces the stress of the silicon substrate, improves the warpage of the silicon substrate, and improves the consistency of the center and the edge of the silicon substrate.
The description as it relates to "first", "second", etc. in the present invention is for descriptive purposes only and is not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated.
The foregoing is merely a preferred embodiment of the present invention and it should be noted that modifications and adaptations to those skilled in the art may be made without departing from the principles of the present invention, which are intended to be comprehended within the scope of the present invention.
Claims (7)
1. The preparation method of the low-stress deep trench polycrystalline gate is characterized by comprising the following steps of:
s1: etching a groove on a silicon substrate, and growing a gate oxide layer in the groove;
s2: preparing a doped polysilicon film in the groove and on the gate oxide layer;
s3: preparing an undoped polysilicon film in the groove and on the doped polysilicon layer;
s4: forming a first oxide layer at the groove opening, and annealing the doped polycrystalline silicon film and the undoped polycrystalline silicon film;
s5: removing the first oxide layer;
s6: preparing an upper doped polysilicon layer in the groove to form a grid electrode, wherein the doped polysilicon layer can be filled with doped polysilicon material;
s7: and forming a second oxide layer on the doped polysilicon layer, and annealing the polysilicon.
2. The method of claim 1, wherein the doped polysilicon film has a thickness of 10% of the trench width.
3. The method of claim 1, wherein the undoped polysilicon film has a thickness of 10% of the trench width.
4. The method for preparing a low stress deep trench poly gate according to claim 1, wherein S4 is specifically: and (3) oxidizing and annealing the silicon substrate in a furnace tube, forming a first oxide layer on the undoped polysilicon film positioned at the groove opening part through oxidation, and simultaneously annealing the doped polysilicon film and the undoped polysilicon film to ensure that the polycrystalline concentration of the doped polysilicon film and the undoped polysilicon film is consistent.
5. The method for preparing a low stress deep trench poly gate according to claim 1, wherein S7 specifically comprises: and (3) oxidizing and annealing the silicon substrate in a furnace tube, forming a second oxide layer on the undoped polysilicon film positioned at the groove opening part through oxidation, and annealing the doped polysilicon film, the undoped polysilicon film and the doped polysilicon layer at the same time to ensure that the polycrystalline concentrations of the doped polysilicon film, the undoped polysilicon film and the doped polysilicon layer are consistent.
6. The method for preparing a low stress deep trench poly gate according to claim 4 or 5, wherein the oxidation temperature is 750-850 ℃ and the oxidation time is 30-60 minutes.
7. A low stress deep trench poly gate prepared by a method of preparing a low stress deep trench poly gate as claimed in any one of claims 1 to 6.
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| CN202410193083.4A CN117747422B (en) | 2024-02-21 | 2024-02-21 | Low-stress deep trench polycrystalline gate and preparation method thereof |
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| CN117747422B true CN117747422B (en) | 2024-04-16 |
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| KR20110024513A (en) * | 2009-09-02 | 2011-03-09 | 주식회사 하이닉스반도체 | Method for fabricating semiconductor device |
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| CN103035502A (en) * | 2012-08-01 | 2013-04-10 | 上海华虹Nec电子有限公司 | Polycrystalline silicon filling method for insulated gate bipolar transistor (IGBT) grid groove |
| CN103050389A (en) * | 2012-12-14 | 2013-04-17 | 上海华虹Nec电子有限公司 | Growing method of low-stress IGBT (Insulated Gate Bipolar Transistor) groove type grid electrode |
| CN103903983A (en) * | 2012-12-24 | 2014-07-02 | 上海华虹宏力半导体制造有限公司 | Process method for forming embedded sink |
| CN113517193A (en) * | 2021-04-06 | 2021-10-19 | 江苏新顺微电子股份有限公司 | Process method for improving performance of trench MOS structure Schottky diode |
| CN115863250A (en) * | 2014-11-26 | 2023-03-28 | 德克萨斯仪器股份有限公司 | Multi-sandwich structure for deep trench filling |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9257557B2 (en) * | 2014-05-20 | 2016-02-09 | Globalfoundries Inc. | Semiconductor structure with self-aligned wells and multiple channel materials |
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Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20110024513A (en) * | 2009-09-02 | 2011-03-09 | 주식회사 하이닉스반도체 | Method for fabricating semiconductor device |
| CN102646603A (en) * | 2012-04-24 | 2012-08-22 | 上海宏力半导体制造有限公司 | Grooved MOS (metal oxide semiconductor) forming method |
| CN103035502A (en) * | 2012-08-01 | 2013-04-10 | 上海华虹Nec电子有限公司 | Polycrystalline silicon filling method for insulated gate bipolar transistor (IGBT) grid groove |
| CN103050389A (en) * | 2012-12-14 | 2013-04-17 | 上海华虹Nec电子有限公司 | Growing method of low-stress IGBT (Insulated Gate Bipolar Transistor) groove type grid electrode |
| CN103903983A (en) * | 2012-12-24 | 2014-07-02 | 上海华虹宏力半导体制造有限公司 | Process method for forming embedded sink |
| CN115863250A (en) * | 2014-11-26 | 2023-03-28 | 德克萨斯仪器股份有限公司 | Multi-sandwich structure for deep trench filling |
| CN113517193A (en) * | 2021-04-06 | 2021-10-19 | 江苏新顺微电子股份有限公司 | Process method for improving performance of trench MOS structure Schottky diode |
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