CN117832067A - Injection mask etching method of SiC power device - Google Patents
Injection mask etching method of SiC power device Download PDFInfo
- Publication number
- CN117832067A CN117832067A CN202311867251.5A CN202311867251A CN117832067A CN 117832067 A CN117832067 A CN 117832067A CN 202311867251 A CN202311867251 A CN 202311867251A CN 117832067 A CN117832067 A CN 117832067A
- Authority
- CN
- China
- Prior art keywords
- layer
- mask
- etching
- sub
- implantation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000005530 etching Methods 0.000 title claims abstract description 125
- 238000000034 method Methods 0.000 title claims abstract description 62
- 238000002347 injection Methods 0.000 title abstract description 7
- 239000007924 injection Substances 0.000 title abstract description 7
- 238000005468 ion implantation Methods 0.000 claims abstract description 40
- 238000002513 implantation Methods 0.000 claims abstract description 34
- 238000001039 wet etching Methods 0.000 claims abstract description 18
- 150000002500 ions Chemical class 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 238000001312 dry etching Methods 0.000 claims abstract description 5
- 229920002120 photoresistant polymer Polymers 0.000 claims description 24
- 239000000463 material Substances 0.000 claims description 15
- 230000004888 barrier function Effects 0.000 claims description 10
- 229910004613 CdTe Inorganic materials 0.000 claims description 8
- 238000010438 heat treatment Methods 0.000 claims description 8
- 239000011259 mixed solution Substances 0.000 claims description 7
- 239000000243 solution Substances 0.000 claims description 6
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 3
- 238000005229 chemical vapour deposition Methods 0.000 claims description 3
- 230000007423 decrease Effects 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 3
- 238000004528 spin coating Methods 0.000 claims description 3
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 abstract description 55
- 229910010271 silicon carbide Inorganic materials 0.000 abstract description 55
- 238000012545 processing Methods 0.000 abstract description 6
- 238000001259 photo etching Methods 0.000 abstract description 3
- 230000000873 masking effect Effects 0.000 abstract description 2
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000000903 blocking effect Effects 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000005280 amorphization Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0332—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their composition, e.g. multilayer masks, materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
- H01L21/0455—Making n or p doped regions or layers, e.g. using diffusion
- H01L21/046—Making n or p doped regions or layers, e.g. using diffusion using ion implantation
- H01L21/0465—Making n or p doped regions or layers, e.g. using diffusion using ion implantation using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
- H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Chemical & Material Sciences (AREA)
- Computer Hardware Design (AREA)
- Crystallography & Structural Chemistry (AREA)
- Inorganic Chemistry (AREA)
- Ceramic Engineering (AREA)
- Drying Of Semiconductors (AREA)
Abstract
The invention relates to an injection mask etching method of a SiC power device, which comprises the steps of providing a SiC substrate; forming an epitaxial layer on the SiC substrate, and preparing a dielectric layer with a sandwich structure on the front surface of the epitaxial layer; selectively masking, dry etching and wet etching the implantation mask layer to obtain a plurality of required ion implantation first windows; and carrying out transverse etching on the side wall of the ion implantation first window by utilizing wet etching to form implantation masks with different step thicknesses, carrying out ion implantation on the epitaxial layer through the mask steps with various thicknesses to form a structure with various ion depths, avoiding the damage of the ion implantation on the surface of silicon carbide, eliminating the low-concentration implantation area with uncontrollable surface, being compatible with the prior art, simplifying the device processing technology, and reducing the photoetching times and implantation mask processing times.
Description
Technical Field
The invention belongs to the technical field of semiconductors, and particularly relates to an implantation mask etching method of a SiC power device.
Background
The SiC material has large forbidden bandwidth, high breakdown electric field, high saturation drift speed and high thermal conductivity, and the excellent properties of the material make the material an ideal material for manufacturing high-power, high-frequency, high-temperature-resistant and radiation-resistant devices.
SiC DMOSFETs are of great value in high power applications, both due to their higher blocking voltages and similar drive circuit designs as Si DMOSFETs. In order to obtain control over surface charge in silicon carbide power device fabrication, a gradual development has been made from single implanted region technology to multi-implanted region technology.
However, this technique adds implantation and mask preparation steps, which are disadvantageous for mass production of semiconductor devices.
Disclosure of Invention
In order to solve the problems in the prior art, the invention provides an etching method of a SiC multistage groove structure. The technical problems to be solved by the invention are realized by the following technical scheme:
the embodiment of the invention provides an implantation mask etching method of a SiC power device, which comprises the following steps:
preparing a SiC substrate layer, a SiC epitaxial layer and a mask group layer which are sequentially stacked from bottom to top, wherein the mask group layer comprises a first mask layer, a second mask layer and a third mask layer which are sequentially stacked from bottom to top;
spin-coating photoresist on the third mask layer, and removing photoresist in the etching area to obtain photoresist at two sides of the etching area;
using photoresist at two sides of the etching region as an etching barrier layer, etching the third mask layer and the second mask layer by using a first etching process until the upper surface of the first mask layer is exposed, and etching the first mask layer in the etching region by using a second etching process until the upper surface of the SiC epitaxial layer is exposed;
a first layer of mask layer and a second layer of mask layer on two sides of the etching area are etched transversely, so that two parts of the first layer of mask layer are etched into a first layer of mask layer and a second layer of mask layer, two parts of the second layer of mask layer are etched into a third layer of mask layer and a fourth layer of mask layer, the distance between the first layer of mask layer and the second layer of mask layer is larger than the distance between the third layer of mask layer and the fourth layer of mask layer, and the distance between the third layer of mask layer and the fourth layer of mask layer is larger than the distance between the third layer of mask layer on two sides of the etching area;
and removing the photoresist on the third mask layer, and performing ion implantation on the SiC epitaxial layer through a mask step structure formed by the first mask sub-layer, the second mask sub-layer, the third mask sub-layer, the fourth mask sub-layer and the third mask layer so as to form an ion implantation region with ion implantation concentration sequentially reduced from the center to two ends in the SiC epitaxial layer.
In one embodiment of the present invention, preparing a SiC substrate layer, a SiC epitaxial layer, and a mask set layer stacked in this order from bottom to top, includes:
preparing an SiC epitaxial layer on the SiC substrate layer;
and sequentially depositing a first mask layer, a second mask layer and a third mask layer on the SiC epitaxial layer by utilizing an ion-enhanced chemical vapor deposition method.
In one embodiment of the present invention, using the photoresist on two sides of the etching area as an etching barrier layer, etching the third mask layer and the second mask layer by using a first etching process until the upper surface of the first mask layer is exposed, includes:
and etching the third mask layer and the second mask layer by using the photoresist at the two sides of the etching area as an etching barrier layer and using a dry etching process until the upper surfaces of the first mask layer are exposed.
In one embodiment of the inventionIn an embodiment, the first mask layer comprises a CdTe mask layer, the second mask layer comprises a SiN mask layer, and the third mask layer comprises SiO 2 And (5) a mask layer.
In one embodiment of the present invention, etching the first mask layer in the etched region to expose the upper surface of the SiC epitaxial layer using a second etching process includes:
and etching the first mask layer in the etching area by using a first wet etching process until the upper surface of the SiC epitaxial layer is exposed.
In one embodiment of the present invention, etching the first mask layer in the etched region to expose the upper surface of the SiC epitaxial layer using a first wet etching process includes:
etching the first mask layer in the etching region by using a first wet etching process until the upper surface of the SiC epitaxial layer is exposed, wherein the etching solution of the first wet etching process comprises HNO 3 And H 3 PO 4 The temperature of the mixed solution is normal temperature.
In one embodiment of the present invention, the etching of the first mask layer and the second mask layer on both sides of the etching region in a lateral direction to etch two portions of the first mask layer into a first mask sub-layer and a second mask sub-layer and two portions of the second mask layer into a third mask sub-layer and a fourth mask sub-layer includes:
and heating an etching solution, and transversely etching the first mask layer of CdTe material and the second mask layer of SiN material on two sides of the etching region by using a second wet etching process so as to etch two parts of the first mask layer into a first mask sub-layer and a second mask sub-layer respectively, and etch two parts of the second mask layer into a third mask sub-layer and a fourth mask sub-layer respectively.
In one embodiment of the invention, the HNO of the second wet etching process 3 And H 3 PO 4 The heating temperature of the mixed solution of (C) is 150-165 ℃.
In one embodiment of the present invention, ion implantation is performed on the SiC epitaxial layer to form an ion implantation region in which ion implantation concentration decreases from the center to both ends in sequence in the SiC epitaxial layer, including:
and performing vertical implantation or inclined implantation of ions on the SiC epitaxial layer to form ion implantation regions with ion implantation concentration sequentially reduced from the center to the two ends in the SiC epitaxial layer, wherein the ion implantation regions are stepped regions symmetrical along a vertical center line.
In one embodiment of the present invention, the ions implanted in the ion implantation region include Al ions.
Compared with the prior art, the invention has the beneficial effects that:
according to the method, the SiC epitaxial layer is formed on the SiC substrate layer, the first layer mask layer, the second layer mask layer and the third layer mask layer with the sandwich structure are prepared on the front surface of the epitaxial layer, then the first layer mask layer, the second layer mask layer and the third layer mask layer in the etching area are removed by selectively masking and etching the implantation mask layer, the etching areas with the first layer mask layer, the second layer mask layer and the third layer mask layer removed are transversely etched to form a mask step structure, and ion implantation is carried out on the SiC epitaxial layer through the mask step structure, so that a structure with various ion depths can be formed, the damage of the ion implantation to the surface of silicon carbide can be avoided, the surface uncontrollable low-concentration implantation area is eliminated, the method is compatible with the prior art, the device processing technology is simplified, the photoetching times and implantation mask processing times are reduced, the batch preparation of devices is facilitated, and the reliability and the stability of the device structure are improved.
The present invention will be described in further detail with reference to the accompanying drawings and examples.
Drawings
Fig. 1 is a schematic flow chart of an implantation mask etching method of a SiC power device according to an embodiment of the present invention;
fig. 2 is a schematic process diagram of an implantation mask etching method for a SiC power device according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to specific examples, but embodiments of the present invention are not limited thereto.
Example 1
Referring to fig. 1 and fig. 2, fig. 1 is a schematic flow chart of an implantation mask etching method of a SiC power device according to an embodiment of the present invention, and fig. 2 is a schematic flow chart of an implantation mask etching method of a SiC power device according to an embodiment of the present invention. The implantation mask etching method of the SiC power device comprises the following steps:
s1, preparing a SiC substrate layer 1, a SiC epitaxial layer 2 and a mask group layer which are sequentially stacked from bottom to top, wherein the mask group layer comprises a first mask layer 3, a second mask layer 4 and a third mask layer 5 which are sequentially stacked from bottom to top.
S1.1, preparing a SiC epitaxial layer 2 on the SiC substrate layer 1.
S1.2, sequentially depositing a first mask layer 3, a second mask layer 4 and a third mask layer 5 on the SiC epitaxial layer 2 by utilizing an ion-body enhanced chemical vapor deposition method.
Preferably, the first mask layer 3 comprises a CdTe mask layer, the second mask layer 4 comprises a SiN mask layer, and the third mask layer 5 comprises SiO 2 And (5) a mask layer.
S2, spin-coating the photoresist 6 on the third mask layer 5, and removing the photoresist 6 in the etching area to obtain the photoresist 6 at two sides of the etching area.
Specifically, the photoresist 6 is subjected to a patterning photolithography and development process to remove the photoresist 6 in the etched region.
And S3, taking the photoresist 6 at two sides of the etching area as an etching barrier layer, etching the third mask layer 5 and the second mask layer 4 by using a first etching process until the upper surface of the first mask layer 3 is exposed, and etching the first mask layer 3 in the etching area by using a second etching process until the upper surface of the SiC epitaxial layer 2 is exposed.
In a specific embodiment, the photoresist 6 at two sides of the etching area is used as an etching barrier layer, and the etching of the third mask layer 5 and the second mask layer 4 by using the first etching process until the upper surface of the first mask layer 3 is exposed includes:
and taking the photoresist 6 at the two sides of the etching area as an etching barrier layer, and etching the third mask layer 5 and the second mask layer 4 by using a dry etching process until the upper surfaces of the first mask layer 3 are exposed.
Preferably, the dry etching gas is CHF 3 And AR.
In a specific embodiment, etching the first mask layer 3 in the etching region to expose the upper surface of the SiC epitaxial layer 2 by using the second etching process includes:
the first mask layer 3 in the etched region is etched by a first wet etching process until the upper surface of the SiC epitaxial layer 2 is exposed.
Further, the first mask layer 3 in the etching region is etched by a first wet etching process until the upper surface of the SiC epitaxial layer 2 is exposed, wherein the etching solution of the first wet etching process includes HNO 3 And H 3 PO 4 The temperature of the mixed solution is normal temperature.
When the first mask layer 3 in the etched region needs to be removed, HNO is removed 3 And H 3 PO 4 Is injected into the etching area, and only the CdTe material is corroded at normal temperature.
S4, etching the first mask layer 3 and the second mask layer 4 on two sides of the etching area transversely to etch two parts of the first mask layer 3 into a first mask sub-layer 31 and a second mask sub-layer 32, and etching two parts of the second mask layer 4 into a third mask sub-layer 41 and a fourth mask sub-layer 42, wherein the distance between the first mask sub-layer 31 and the second mask sub-layer 32 is larger than the distance between the third mask sub-layer 41 and the fourth mask sub-layer 42, and the distance between the third mask sub-layer 41 and the fourth mask sub-layer 42 is larger than the distance between the third mask sub-layer 5 on two sides of the etching area.
In a specific embodiment, the etching solution is heated, and the first mask layer 3 of CdTe material and the second mask layer 4 of SiN material on both sides of the etching region are etched laterally by using a second wet etching process, so that two portions of the first mask layer 3 are etched into a first mask sub-layer 31 and a second mask sub-layer 32, respectively, and two portions of the second mask layer 4 are etched into a third mask sub-layer 41 and a fourth mask sub-layer 42, respectively.
HNO of the second wet etching process 3 And H 3 PO 4 The heating temperature of the mixed solution of (C) is 150-165 ℃.
After removing the first mask layer 3 in the etched area, HNO continues to be heated by heating the entire device 3 And H 3 PO 4 The mixed solution is continuously etched in the heating process to the CdTe material, and after the heating is carried out to 150-165 ℃, the SiN material starts to be etched, so that finally, two parts of the first mask layer 3 are etched into a first mask sub-layer 31 and a second mask sub-layer 32 through transverse etching, two parts of the second mask layer 4 are etched into a third mask sub-layer 41 and a fourth mask sub-layer 42, and a mask step structure formed by the first mask sub-layer 31, the second mask sub-layer 32, the third mask sub-layer 41, the fourth mask sub-layer 42 and the third mask layer 5 is used as a mask for subsequent ion implantation.
S5, removing the photoresist 6 on the third mask layer 5, and performing ion implantation on the SiC epitaxial layer 2 through a mask step structure formed by the first mask sub-layer 31, the second mask sub-layer 32, the third mask sub-layer 41, the fourth mask sub-layer 42 and the third mask layer 5 to form ion implantation regions 7 with ion implantation concentrations sequentially decreasing from the center to the two ends in the SiC epitaxial layer 2.
Specifically, the SiC epitaxial layer 2 is subjected to vertical implantation or tilt implantation of ions to form ion implantation regions 6 in the SiC epitaxial layer 2 in which the ion implantation concentration decreases from the center to both ends in order, and the ion implantation regions 7 are stepped regions symmetrical along the vertical center line. The vertical implantation is performed along the direction perpendicular to the device, and the inclined implantation is performed at an included angle smaller than 90 degrees and larger than 0 degrees with the horizontal direction of the device.
Preferably, the ions implanted in the ion implantation region include Al ions.
The invention provides an injection mask etching method of a SiC power device, which comprises the steps of firstly growing a first mask layer, a second mask layer and a third mask layer which are sequentially stacked from bottom to top, taking photoresist 6 at two sides of an etching area as an etching barrier layer, etching the third mask layer and the second mask layer in the etching area, then etching the first mask layer and the second mask layer at two sides of the etching area through transverse etching, so that two parts of the first mask layer are etched into a first mask sub-layer and a second mask sub-layer, and two parts of the second mask layer are etched into a third mask sub-layer and a fourth mask sub-layer, thereby forming mask step structures with various thicknesses; and then, carrying out ion implantation on the SiC epitaxial layer through mask steps with various thicknesses to form ion implantation areas with various ion depths, thereby improving the implantation depth and the reliability and stability of the device structure.
According to the invention, the mask steps with various thicknesses are used as the blocking layer for ion implantation, so that amorphization damage of the ion implantation to the silicon carbide surface can be avoided, the channel effect of the ion implantation is avoided, the low implantation concentration area on the silicon carbide surface is eliminated, and the control of the ion implantation peak value depth can be realized through the mask step film etching depth with various thicknesses.
The invention can realize the structure with different injection depths in multiple regions by one injection, effectively reduces the local electric field on the surface of the device, is compatible with the prior art, simplifies the processing technology of the device, and reduces the photoetching times and the injection mask processing times.
In the description of the present invention, the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present invention, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Further, one skilled in the art can engage and combine the different embodiments or examples described in this specification.
The foregoing is a further detailed description of the invention in connection with the preferred embodiments, and it is not intended that the invention be limited to the specific embodiments described. Modifications made by those skilled in the art without departing from the spirit of the invention should be considered as falling within the scope of the invention.
Claims (10)
1. An implantation mask etching method of a SiC power device is characterized by comprising the following steps:
preparing a SiC substrate layer (1), a SiC epitaxial layer (2) and a mask group layer which are sequentially stacked from bottom to top, wherein the mask group layer comprises a first mask layer (3), a second mask layer (4) and a third mask layer (5) which are sequentially stacked from bottom to top;
spin-coating photoresist (6) on the third mask layer (5), and removing the photoresist (6) in the etching area to obtain the photoresist (6) at two sides of the etching area;
using photoresist (6) at two sides of the etching area as an etching barrier layer, etching the third mask layer (5) and the second mask layer (4) by using a first etching process until the upper surface of the first mask layer (3) is exposed, and etching the first mask layer (3) in the etching area by using a second etching process until the upper surface of the SiC epitaxial layer (2) is exposed;
a first layer mask layer (3) and a second layer mask layer (4) on two sides of the etching area are transversely etched, so that two parts of the first layer mask layer (3) are etched to form a first layer mask sub-layer (31) and a second layer mask sub-layer (32), two parts of the second layer mask layer (4) are etched to form a third layer mask sub-layer (41) and a fourth layer mask sub-layer (42), wherein the distance between the first layer mask sub-layer (31) and the second layer mask sub-layer (32) is larger than the distance between the third layer mask sub-layer (41) and the fourth layer mask sub-layer (42), and the distance between the third layer mask sub-layer (41) and the fourth layer mask sub-layer (42) is larger than the distance between the third layer mask layer (5) on two sides of the etching area;
and removing the photoresist (6) on the third mask layer (5), and performing ion implantation on the SiC epitaxial layer (2) through a mask step structure formed by the first mask sub-layer (31), the second mask sub-layer (32), the third mask sub-layer (41), the fourth mask sub-layer (42) and the third mask layer (5) so as to form an ion implantation region with ion implantation concentration sequentially reduced from the center to two ends in the SiC epitaxial layer (2).
2. The implantation mask etching method according to claim 1, wherein preparing the SiC substrate layer (1), the SiC epitaxial layer (2) and the mask set layer stacked in this order from bottom to top comprises:
preparing an SiC epitaxial layer (2) on the SiC substrate layer (1);
and sequentially depositing a first mask layer (3), a second mask layer (4) and a third mask layer (5) on the SiC epitaxial layer (2) by utilizing an ion-enhanced chemical vapor deposition method.
3. The implantation mask etching method according to claim 1, wherein the etching the third mask layer (5) and the second mask layer (4) by using the photoresist (6) at two sides of the etching region as an etching barrier layer by using a first etching process until the upper surface of the first mask layer (3) is exposed comprises:
and etching the third mask layer (5) and the second mask layer (4) by using the photoresist (6) at two sides of the etching area as etching barrier layers and using a dry etching process until the upper surfaces of the first mask layer (3) are exposed.
4. The implantation mask etching method according to claim 1, wherein the first mask layer (3) comprises a CdTe mask layer, the second mask layer (4) comprises a SiN mask layer, and the third mask layer (5) comprises SiO 2 And (5) a mask layer.
5. The implantation mask etching method according to claim 4, wherein etching the first mask layer (3) in the etching region to expose the upper surface of the SiC epitaxial layer (2) using the second etching process comprises:
and etching the first mask layer (3) in the etching area by using a first wet etching process until the upper surface of the SiC epitaxial layer (2) is exposed.
6. The implantation mask etching method according to claim 5, wherein etching the first mask layer (3) in the etching region to expose the upper surface of the SiC epitaxial layer (2) using a first wet etching process comprises:
etching the first mask layer (3) in the etching region by using a first wet etching process until the upper surface of the SiC epitaxial layer (2) is exposed, wherein the etching solution of the first wet etching process comprises HNO 3 And H 3 PO 4 The temperature of the mixed solution is normal temperature.
7. The implantation mask etching method according to claim 6, wherein the first mask layer (3) and the second mask layer (4) on both sides of the etching region are laterally etched to etch two parts of the first mask layer (3) into a first mask sub-layer (31) and a second mask sub-layer (32), and two parts of the second mask layer (4) into a third mask sub-layer (41) and a fourth mask sub-layer (42), comprising:
and heating an etching solution, and transversely etching the first mask layer (3) of CdTe material and the second mask layer (4) of SiN material on two sides of the etching region by using a second wet etching process so as to etch two parts of the first mask layer (3) into a first mask sub-layer (31) and a second mask sub-layer (32) respectively and etch two parts of the second mask layer (4) into a third mask sub-layer (41) and a fourth mask sub-layer (42) respectively.
8. The method of claim 7, wherein the HNO of the second wet etch process 3 And H 3 PO 4 The heating temperature of the mixed solution of (C) is 150-165 ℃.
9. The implantation mask etching method according to claim 1, wherein ion implantation is performed on the SiC epitaxial layer (2) to form an ion implantation region in which ion implantation concentration decreases sequentially from the center toward both ends in the SiC epitaxial layer (2), comprising:
and performing vertical implantation or inclined implantation of ions on the SiC epitaxial layer (2) to form ion implantation regions with ion implantation concentration sequentially reduced from the center to two ends in the SiC epitaxial layer (2), wherein the ion implantation regions are stepped regions symmetrical along a vertical center line.
10. The implantation mask etching method of claim 9, wherein the ions implanted in the ion implantation region comprise Al ions.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311867251.5A CN117832067A (en) | 2023-12-28 | 2023-12-28 | Injection mask etching method of SiC power device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311867251.5A CN117832067A (en) | 2023-12-28 | 2023-12-28 | Injection mask etching method of SiC power device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN117832067A true CN117832067A (en) | 2024-04-05 |
Family
ID=90514985
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202311867251.5A Pending CN117832067A (en) | 2023-12-28 | 2023-12-28 | Injection mask etching method of SiC power device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN117832067A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN118039432A (en) * | 2024-04-11 | 2024-05-14 | 南京航空航天大学 | Method for producing semiconductor mask plate by single mask technology |
-
2023
- 2023-12-28 CN CN202311867251.5A patent/CN117832067A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN118039432A (en) * | 2024-04-11 | 2024-05-14 | 南京航空航天大学 | Method for producing semiconductor mask plate by single mask technology |
| CN118039432B (en) * | 2024-04-11 | 2024-06-07 | 南京航空航天大学 | Method for producing semiconductor mask plate by single mask technology |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2670563B2 (en) | Method for manufacturing semiconductor device | |
| JPS6220696B2 (en) | ||
| JPH0744272B2 (en) | Transistor manufacturing method | |
| JPS62219943A (en) | Formation of insulated isolation region | |
| CN117832067A (en) | Injection mask etching method of SiC power device | |
| CN108336152A (en) | Groove-shaped silicon carbide SBD device with floating junction and its manufacturing method | |
| CN105070663B (en) | Silicon carbide MOSFET channel self-alignment process implementation method | |
| CN102522335B (en) | Power device terminal ring production method and structure of terminal ring | |
| CN117747422B (en) | Low-stress deep trench polycrystalline gate and preparation method thereof | |
| CN116994956A (en) | Silicon carbide power device, preparation method thereof and chip | |
| JP5087834B2 (en) | Manufacturing method of semiconductor device | |
| US4477963A (en) | Method of fabrication of a low capacitance self-aligned semiconductor electrode structure | |
| JPS62570B2 (en) | ||
| US20230038280A1 (en) | Silicon carbide mosfet device and manufacturing method thereof | |
| US4587709A (en) | Method of making short channel IGFET | |
| JPS62232142A (en) | Manufacture of semi-oxide isolation device | |
| CN104022153B (en) | Dual gate FET with tensile strain thin film strain source and preparation method thereof | |
| CN104241128A (en) | Method for manufacturing vertical SiGe FinFET | |
| KR100430258B1 (en) | Fabrication method of laser diode using of plasma reactive etching | |
| KR100877878B1 (en) | Method for manufacturing semiconductor device | |
| JPS5968950A (en) | Manufacture of semiconductor device | |
| KR100628624B1 (en) | Method for fabricating a self-aligned bipolar transistor and related structure | |
| CN117832076A (en) | Self-alignment method of groove type SiC device | |
| RU867224C (en) | Method of manufacturing hf transistor structures | |
| CN109755130A (en) | A kind of method, semi-conductor device manufacturing method reducing input capacitance |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |