CN118156136A - Method for improving reverse withstand voltage of trench MOSFET device IGSSR - Google Patents
Method for improving reverse withstand voltage of trench MOSFET device IGSSR Download PDFInfo
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- CN118156136A CN118156136A CN202410078670.9A CN202410078670A CN118156136A CN 118156136 A CN118156136 A CN 118156136A CN 202410078670 A CN202410078670 A CN 202410078670A CN 118156136 A CN118156136 A CN 118156136A
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- 238000000034 method Methods 0.000 title claims abstract description 63
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 68
- 229920005591 polysilicon Polymers 0.000 claims abstract description 65
- 230000008569 process Effects 0.000 claims abstract description 40
- 239000000758 substrate Substances 0.000 claims abstract description 39
- 238000005530 etching Methods 0.000 claims abstract description 36
- 239000004065 semiconductor Substances 0.000 claims abstract description 20
- 238000000137 annealing Methods 0.000 claims abstract description 6
- 210000000746 body region Anatomy 0.000 claims abstract description 6
- 238000005468 ion implantation Methods 0.000 claims abstract description 5
- 238000002513 implantation Methods 0.000 claims abstract description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 8
- 229910052710 silicon Inorganic materials 0.000 claims description 8
- 239000010703 silicon Substances 0.000 claims description 8
- 238000000151 deposition Methods 0.000 claims description 5
- 238000001312 dry etching Methods 0.000 claims description 5
- 230000003647 oxidation Effects 0.000 claims description 5
- 238000007254 oxidation reaction Methods 0.000 claims description 5
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 claims description 3
- 229910002601 GaN Inorganic materials 0.000 claims description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 3
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims description 3
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 3
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 3
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 3
- 230000007547 defect Effects 0.000 description 4
- 238000001039 wet etching Methods 0.000 description 4
- 230000008021 deposition Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000012360 testing method Methods 0.000 description 3
- 238000005137 deposition process Methods 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
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Abstract
The invention discloses a method for improving reverse withstand voltage of a groove type MOSFET product IGSSR, which comprises the steps of etching a semiconductor substrate to form a groove, forming a gate dielectric layer, and filling the groove with polysilicon; etching back the polysilicon, etching back the gate dielectric layer, removing the gate dielectric layer on the surface of the semiconductor substrate, and removing the gate dielectric layer on the side wall of the groove on the upper top surface of the polysilicon in the groove opening; growing an oxide layer again, wherein the oxide layer is formed on the surface of the whole semiconductor substrate and covers the upper top surface of the polysilicon in the groove; performing a polysilicon annealing process; and (5) completing the implantation and thermal promotion of the P-type body region and the ion implantation of the source region. The invention optimizes the process sequence, precisely controls the thickness of the oxide layer, eliminates the problem of reduced pressure resistance of the device caused by the hole formed at the sharp angle position of the gate dielectric layer at the top of the groove, and improves the reverse pressure resistance of the gate source of the groove product.
Description
Technical Field
The invention relates to the field of semiconductor device manufacturing, in particular to a method for improving reverse withstand voltage of a groove type MOSFET device IGSSR.
Background
The trench MOSFET is another power device different from the planar gate MOSFET, and has stronger current passing capability and higher power. The equivalent circuit structure is shown in figure 1, the grid electrode is a groove type, and the groove is filled with a layer of grid dielectric layer deposited in the groove to form the grid electrode structure.
IGSS, the leakage current between Gate and Source, i.e., the leakage current of Gate oxide, is typically in the nA level.
The existing manufacturing process of the trench MOSFET comprises the following steps: polysilicon deposition and annealing, polysilicon back etching, oxide film wet etching, P-type body region injection and thermal promotion, oxide layer wet etching, source region injection and the like.
The main process affecting IGSS is at several main nodes:
1. The polysilicon is etched back, and direct short circuit between the contact hole and the polysilicon is possibly caused by incomplete etching back;
2. Metal short circuit between gate sources possibly caused in a metal back etching process;
3. Defects or contamination of the gate oxide itself formed.
In the product manufacturing process, the annealing of the polysilicon is completed after deposition, and the thickness of the shielding oxide layer of the ion implantation of the body region and the source region is controlled by a wet etching process, but the process can form a cavity at the sharp corner position of the gate oxide layer, which can lead to lower reverse withstand voltage of the device.
Disclosure of Invention
The technical problem to be solved by the invention is to provide a method for improving the reverse voltage resistance of a trench MOSFET device IGSSR, which is used for improving the problems of gate-source leakage and device voltage resistance reduction caused by a cavity formed at the sharp angle position between the top of polysilicon in a trench and a gate dielectric layer.
In order to solve the above-mentioned problems, the present invention provides a method for improving reverse withstand voltage of a trench MOSFET device IGSSR, comprising:
Providing a semiconductor substrate, and etching a groove on the semiconductor substrate, wherein the groove is used for forming a grid electrode;
Forming a gate dielectric layer in the groove, and filling the groove with polysilicon;
etching the polysilicon back until the upper top surface of the polysilicon in the groove is lower than the opening of the groove by a certain distance;
Etching the gate dielectric layer back to remove the gate dielectric layer on the surface of the semiconductor substrate, and removing the gate dielectric layer on the side wall of the groove on the upper top surface of the polysilicon in the groove opening;
Growing an oxide layer again, wherein the oxide layer is formed on the surface of the whole semiconductor substrate, covers the upper top surface of the polysilicon in the groove, and wraps and isolates the polysilicon together with the gate dielectric layer;
Performing a polysilicon annealing process;
and (5) completing the implantation and thermal promotion of the P-type body region and the ion implantation of the source region.
Further, the semiconductor substrate comprises a silicon substrate, a gallium arsenide substrate, a germanium-silicon substrate, a gallium nitride substrate and a silicon carbide substrate.
Further, the back etching of the polysilicon is to etch the filled polysilicon in the trench downwards by adopting an etching process, so that the upper top surface of the polysilicon and the opening plane of the trench have enough fall to ensure sufficient etching, and the bonding plane of the upper top surface of the polysilicon and the gate dielectric layer is smooth and has no recess.
Further, the etching process is a dry etching process.
Further, the gate dielectric layer is etched back, and the gate dielectric layer on the side wall of the trench above the upper top surface of the polysilicon in the trench can be completely removed or incompletely removed.
Further, the oxide layer grows again, so that an oxide layer is formed on the upper top surface of the polysilicon in the groove and combined with the gate dielectric layer, and the polysilicon, the gate dielectric layer and the newly grown oxide layer are tightly combined without forming a cavity; the process for growing the oxide layer adopts a thermal oxidation method to oxidize the polysilicon and the semiconductor substrate to form the oxide layer, or a deposition method to deposit an oxide layer.
The method for improving the reverse voltage resistance of the trench MOSFET device IGSSR optimizes the process sequence, precisely controls the thickness of the oxide layer, firstly carries out the back etching process of the polysilicon and then anneals the polysilicon, eliminates the problem of reduced voltage resistance of the device caused by the hole formed at the sharp angle position of the gate dielectric layer at the top of the trench, and improves the gate-source reverse voltage resistance of the trench product.
Drawings
Fig. 1 is an equivalent circuit diagram of a trench MOSFET device.
Fig. 2 is a schematic illustration of the invention after polysilicon deposition and back etching.
Fig. 3 is a schematic diagram of the gate dielectric layer of the present invention after etching back.
Fig. 4 is a schematic diagram of the present invention where an oxide layer is again formed to encapsulate a polysilicon gate.
Fig. 5 is a graph of reverse withstand voltage test of a device formed by the process of the present invention.
Fig. 6 is a flow chart of the method steps of the present invention.
Description of the reference numerals
1 Is a semiconductor substrate, 2 is a gate dielectric layer (oxide layer), and 3 is polysilicon.
Detailed Description
The following description of the embodiments of the present invention will be given with reference to the accompanying drawings, in which the technical solutions of the present invention are clearly and completely described, but the present invention is not limited to the following embodiments. It will be apparent that the described embodiments are some, but not all, embodiments of the invention. Advantages and features of the invention will become more apparent from the following description and from the claims. It is noted that the drawings are in a very simplified form and use non-precise ratios for convenience and clarity in assisting in illustrating embodiments of the invention. All other embodiments obtained by those skilled in the art without making any inventive effort are within the scope of the present invention.
This application may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the application to those skilled in the art. In the drawings, the size of layers and regions, as well as the relative sizes, may be exaggerated for the same elements throughout. In the description of the present application, it should be noted that the directions or positional relationships indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. are based on the directions or positional relationships shown in the drawings, are merely for convenience of describing the present application and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
The invention provides a method for improving reverse voltage withstand of a groove type MOSFET device IGSSR, which solves the problem of insufficient IGSSR reverse voltage withstand capability of the groove type MOSFET device caused by the technical problem. The process method comprises the following steps:
a semiconductor substrate is provided including, but not limited to, a silicon substrate, a gallium arsenide substrate, a silicon germanium substrate, a gallium nitride substrate, a silicon carbide substrate. Taking the most common silicon substrate as an example, etching a groove on the silicon substrate, wherein the groove is used for forming a gate structure of the groove type MOSFET device.
And forming a gate dielectric layer, generally an oxide layer, in the trench, wherein the oxide layer serving as the gate dielectric layer is generally formed by a thermal oxidation method, and the formed gate dielectric layer has good compactness and high quality. The gate dielectric layer covers the surface of the silicon substrate and the inner wall of the groove, and an attached gate dielectric layer is formed on the inner wall of the groove. And then, a deposition process of polysilicon is carried out, and the space of the groove is filled with polysilicon.
And carrying out back etching on the polycrystalline silicon, and carrying out downward etching on the filled polycrystalline silicon in the groove by adopting a dry etching process, so that the upper top surface of the polycrystalline silicon and the opening plane of the groove have enough fall to ensure sufficient etching. As shown in FIG. 2, the drop height shown by the broken line in the figure is larger than that after the back etching of the conventional process, namely, the back etching quantity of the polysilicon is basically larger than that of the conventional process, so that the two sides of the upper top surface of the polysilicon and the gate oxide are ensured to have no excessive gap as much as possible. Because, as introduced in the background art, after the back etching of the polysilicon in the conventional process, the wet etching process is adopted for the back etching of the gate dielectric layer, the etching amount is not easy to precisely control, so that a larger downward recess appears between the polysilicon and the gate dielectric layer, and gaps can be caused by incomplete filling of the recess when the oxide layer is formed in the follow-up process, thereby reducing the reverse pressure-resistant capability of the device.
As shown in fig. 3, the gate dielectric layer is etched back by a dry etching process, the thickness of the etched oxide layer is precisely controlled by the dry etching process, the gate dielectric layer on the surface of the semiconductor substrate is removed, and the gate dielectric layer on the side wall of the trench on the upper top surface of the polysilicon in the trench opening is also partially removed or completely removed. The combination plane of the upper top surface of the polysilicon and the gate dielectric layer is smooth and has no recess.
And growing an oxide layer again, wherein the oxide layer is formed on the surface of the whole semiconductor substrate and covers the upper top surface of the polysilicon in the groove, and the polysilicon, the gate dielectric layer and the newly grown oxide layer are tightly combined to form no cavity, as shown in fig. 4. And the newly formed oxide layer and the gate dielectric layer are used for wrapping and isolating the polysilicon. The formation process of the oxide layer can be a thermal oxidation method, and oxygen is introduced into a high-temperature process cavity to oxidize the silicon substrate material and the polysilicon at a high temperature. The silicon material of the silicon substrate and the polysilicon in the groove are subjected to thermal oxidation, so that an oxide layer can be directly produced, or a deposition process can be adopted, and an oxide layer is directly and additionally grown on the oxide layer and combined with the original gate oxide layer. Under the conventional process, due to the incompleteness of etching between the upper top surface of the polysilicon and the oxide layer, a cavity is easy to form between the upper top surface of the polysilicon and the gate oxide layer on the side wall of the groove to cause defects, and after the process, the sharp corner cavity defects of the conventional process are eliminated.
Then, carrying out subsequent processes including an annealing process of the polysilicon;
and (5) completing the implantation and thermal promotion of the P-type body region and the ion implantation of the source region.
The device formed by the process has the advantages that the cavity defects on the two sides of the top of the polysilicon are basically eliminated, and the ideal process morphology can be formed.
The graph shown in fig. 5 is a graph for testing a device formed by the method of the present invention, and shows the reverse withstand voltage capability between gate and source, and it can be seen that the reverse withstand voltage of the device in the prior art is about 20V, and the test graph of the device of the present invention shows that the reverse withstand voltage is raised to 50-60V.
According to the method for improving the reverse voltage resistance of the trench MOSFET product IGSSR, the process sequence is optimized, the thickness of the oxide layer is accurately controlled, the back etching process of the polysilicon is performed first, then the polysilicon is annealed, the problem of reduced device voltage resistance caused by holes formed at the sharp corner positions of the gate dielectric layer at the top of the trench is solved, and the gate-source reverse voltage resistance of the trench product is improved.
The above are only preferred embodiments of the present invention, and are not intended to limit the present invention. Various modifications and variations of the present invention will be apparent to those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (7)
1. A method for improving reverse withstand voltage of a trench MOSFET device IGSSR, comprising:
Providing a semiconductor substrate, and etching the semiconductor substrate by adopting an etching process to form a groove, wherein the groove is used for forming a groove type grid electrode of the groove type MOSFET device;
Forming a gate dielectric layer in the groove, and filling the groove with polysilicon;
etching the polysilicon back until the upper top surface of the polysilicon in the groove is lower than the opening of the groove by a certain distance;
Etching the gate dielectric layer back to remove the gate dielectric layer on the surface of the semiconductor substrate, and removing the gate dielectric layer on the side wall of the groove on the upper top surface of the polysilicon in the groove opening;
Growing an oxide layer again, wherein the oxide layer is formed on the surface of the whole semiconductor substrate, covers the upper top surface of the polysilicon in the groove, and wraps and isolates the polysilicon together with the gate dielectric layer;
Performing a polysilicon annealing process;
and (5) completing the implantation and thermal promotion of the P-type body region and the ion implantation of the source region.
2. The method for improving the reverse withstand voltage of a trench MOSFET device IGSSR as defined in claim 1, wherein: the semiconductor substrate comprises a silicon substrate, a gallium arsenide substrate, a germanium-silicon substrate, a gallium nitride substrate and a silicon carbide substrate.
3. The method for improving the reverse withstand voltage of a trench MOSFET device IGSSR as defined in claim 1, wherein: and the step of back etching the polysilicon is to etch the filled polysilicon in the groove downwards by adopting an etching process, so that the upper top surface of the polysilicon and the opening plane of the groove have enough fall to ensure sufficient etching, and the bonding plane of the upper top surface of the polysilicon and the gate dielectric layer is smooth and has no recess.
4. The method for improving the reverse withstand voltage of the trench MOSFET device IGSSR as recited in claim 3, wherein: the etching process is a dry etching process.
5. The method for improving the reverse withstand voltage of a trench MOSFET device IGSSR as defined in claim 1, wherein: and etching the gate dielectric layer back, wherein the gate dielectric layer on the side wall of the groove above the upper top surface of the polysilicon in the groove can be completely removed or incompletely removed.
6. The method for improving the reverse withstand voltage of a trench MOSFET device IGSSR as defined in claim 1, wherein: growing an oxide layer again, so that an oxide layer is formed on the upper top surface of the polysilicon in the groove and combined with the gate dielectric layer, and the polysilicon, the gate dielectric layer and the newly grown oxide layer are tightly combined without forming a cavity; the process for growing the oxide layer adopts a thermal oxidation method to oxidize the polysilicon and the semiconductor substrate to form the oxide layer, or a deposition method to deposit an oxide layer.
7. The method for improving the reverse withstand voltage of a trench MOSFET device IGSSR as defined in any one of claims 1 to 6, wherein: the gate dielectric layer is an oxide layer.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410078670.9A CN118156136A (en) | 2024-01-19 | 2024-01-19 | Method for improving reverse withstand voltage of trench MOSFET device IGSSR |
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| CN202410078670.9A CN118156136A (en) | 2024-01-19 | 2024-01-19 | Method for improving reverse withstand voltage of trench MOSFET device IGSSR |
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