CN113192839B - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor device Download PDFInfo
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- CN113192839B CN113192839B CN202110461229.5A CN202110461229A CN113192839B CN 113192839 B CN113192839 B CN 113192839B CN 202110461229 A CN202110461229 A CN 202110461229A CN 113192839 B CN113192839 B CN 113192839B
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- 238000000034 method Methods 0.000 title claims abstract description 57
- 239000004065 semiconductor Substances 0.000 title claims abstract description 24
- 238000004519 manufacturing process Methods 0.000 title claims description 19
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 51
- 229920005591 polysilicon Polymers 0.000 claims abstract description 48
- 239000000758 substrate Substances 0.000 claims abstract description 46
- 230000008569 process Effects 0.000 claims abstract description 42
- 238000001039 wet etching Methods 0.000 claims abstract description 31
- 238000000137 annealing Methods 0.000 claims abstract description 23
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 12
- 229910052757 nitrogen Inorganic materials 0.000 claims description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 5
- 239000007789 gas Substances 0.000 claims description 5
- 239000001257 hydrogen Substances 0.000 claims description 5
- 229910052739 hydrogen Inorganic materials 0.000 claims description 5
- 230000003647 oxidation Effects 0.000 claims description 5
- 238000007254 oxidation reaction Methods 0.000 claims description 5
- 239000001301 oxygen Substances 0.000 claims description 5
- 229910052760 oxygen Inorganic materials 0.000 claims description 5
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 4
- 238000005530 etching Methods 0.000 claims description 4
- 238000002360 preparation method Methods 0.000 abstract description 5
- 230000007547 defect Effects 0.000 description 8
- 230000015556 catabolic process Effects 0.000 description 6
- 230000008901 benefit Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- -1 for example Substances 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 150000002431 hydrogen Chemical class 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000008439 repair process Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000009279 wet oxidation reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
- H01L29/66621—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The invention provides a preparation method of a semiconductor device, which comprises the following steps: providing a substrate, and forming a plurality of grid grooves in the substrate; forming a first oxide layer on the inner wall of the gate trench; performing an annealing process on the first oxide layer; filling a polysilicon layer in the gate trench; wet etching is carried out on the first oxide layer so that the top of the first oxide layer is lower than the surface of the substrate; the invention improves the electric performance of the device by improving the uniformity of the top of the first oxide layer.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a preparation method of a semiconductor device.
Background
The shielded gate trench type MOSFET is a typical trench type MOSFET and has the advantage of low conduction loss of the traditional trench type MOSFET, so the shielded gate trench type MOSFET has wide application. In the manufacturing process of the shielded gate trench MOSFET, after a first oxide layer is formed in a gate trench, the first oxide layer covers the inner wall of the gate trench, then a polysilicon layer is formed in the gate trench, the polysilicon layer is filled in the gate trench, the polysilicon layer covers the surface of a substrate when the polysilicon layer is formed, and after the polysilicon layer is etched, the polysilicon layer on the surface of the substrate is removed and the polysilicon layer in the gate trench is reserved; the first oxide layer is then etched to form openings in which a gate polysilicon layer is formed by a subsequent process to fabricate a gate. However, after the first oxide layer is etched, a relatively obvious unevenness may occur on the top of the first oxide layer, which affects the formation of the subsequent second oxide layer and ultimately affects the electrical performance of the device.
Disclosure of Invention
The invention aims to provide a preparation method of a semiconductor device, which reduces the influence on the subsequent process caused by poor top uniformity of a first oxide layer by improving the top uniformity of the first oxide layer so as to improve the electrical performance of the device.
In order to achieve the above object, the present invention provides a method for manufacturing a semiconductor device, comprising:
providing a substrate, and forming a plurality of grid grooves in the substrate;
forming a first oxide layer on the inner wall of the gate trench;
performing an annealing process on the first oxide layer;
Filling a polysilicon layer in the gate trench; and
And carrying out wet etching on the first oxide layer so that the top of the first oxide layer is lower than the surface of the substrate.
Optionally, the temperature of the annealing process is 950-1150 ℃.
Optionally, the time of the annealing process is 1-4 hours.
Optionally, the process gas of the annealing process is hydrogen and/or nitrogen.
Optionally, a wet oxygen oxidation process is used to form the first oxide layer on the inner wall of the gate trench.
Optionally, when the first oxide layer is formed on the inner wall of the gate trench, the first oxide layer also extends to cover the surface of the substrate.
Optionally, when the polysilicon layer is filled in the gate trench, the polysilicon layer also extends to cover the surface of the first oxide layer.
Optionally, before wet etching the first oxide layer, the method further includes:
And etching the polysilicon layer to remove the polysilicon layer on the surface of the substrate and the polysilicon layer with partial thickness in the gate trench, so that the top of the polysilicon layer in the gate trench is lower than the surface of the substrate.
Optionally, after the first oxide layer is wet etched, an opening is formed between the surface of the substrate and the top of the first oxide layer.
Optionally, after wet etching the first oxide layer, a second oxide layer is further formed on the inner wall of the opening.
In the preparation method of the semiconductor device, a plurality of gate trenches are formed in the substrate, a first oxide layer is formed on the inner wall of each gate trench, and then an annealing process is carried out on the first oxide layer so as to change the compactness of the first oxide layer and enhance the breakdown resistance of the device; furthermore, filling a polysilicon layer in the gate trench, and performing wet etching on the first oxide layer so that the top of the first oxide layer is lower than the surface of the substrate; because the compactness of the first oxide layer is changed and the defect of the surface of the first oxide layer is repaired after the first oxide layer is subjected to an annealing process, the wet etching rate can be reduced when wet etching is performed, so that the uniformity of the top of the first oxide layer is improved after wet etching, and the influence on the subsequent process due to poor uniformity of the top of the first oxide layer is reduced, so that the electrical performance of a device is improved.
Drawings
Fig. 1 is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention;
FIGS. 2A-2E are schematic cross-sectional views illustrating steps corresponding to a method for fabricating a semiconductor device according to an embodiment of the present invention;
wherein, the reference numerals are as follows:
10-substrate; 20-gate trenches; 30-a first oxide layer; a 40-polysilicon layer; 50-a second oxide layer.
Detailed Description
In the manufacturing process of the shielded gate trench type MOSFET, a first oxide layer is formed in a gate trench by adopting a wet oxygen oxidation process, the first oxide layer covers the inner wall of the gate trench, although the wet oxygen oxidation process is faster in forming the first oxide layer, the compactness of the first oxide layer is poor, the fixed charge density of the first oxide layer is high, the surface defect charges of the first oxide layer are more, and the breakdown resistance of a device is poor. And filling the grid groove to form a polysilicon layer, wherein the polysilicon layer also covers the surface of the substrate when the polysilicon layer is formed, and carrying out wet etching on the first oxide layer so that the top of the first oxide layer is lower than the surface of the substrate to form an opening. After wet etching is carried out on the polycrystalline silicon layer, removing the polycrystalline silicon layer on the surface of the substrate and reserving the polycrystalline silicon layer in the grid electrode groove; however, one side of the first oxide layer, which is close to the polysilicon layer, will be contacted with the etchant in wet etching, and is etched earlier than the other side of the first oxide layer, which is far away from the polysilicon layer, and the compactness of the first oxide layer is worse, when wet etching is performed, the etching rate is faster, and after wet etching, the morphology difference between one side of the first oxide layer, which is close to the polysilicon layer, and the other side of the first oxide layer, which is far away from the polysilicon layer, is larger, namely the top uniformity of the first oxide layer is worse. And the uniformity of the top of the first oxide layer is poor, when the second oxide layer is formed in the opening by the subsequent process, the uniformity of the top of the first oxide layer is poor, which affects the morphology of the second oxide layer after formation, resulting in poor uniformity of the second oxide layer, such as uneven thickness of the second oxide layer, and the second oxide layer is used as a gate oxide layer, and the uniformity of the second oxide layer is poor, which affects the electrical performance of the device.
Therefore, in the preparation method of the semiconductor device provided by the invention, a plurality of gate trenches are formed in the substrate, a first oxide layer is formed on the inner wall of the gate trench, and then an annealing process is performed on the first oxide layer, so that the compactness of the first oxide layer is changed, and the breakdown resistance of the device is enhanced; furthermore, filling a polysilicon layer in the gate trench, and performing wet etching on the first oxide layer so that the top of the first oxide layer is lower than the surface of the substrate; because the compactness of the first oxide layer is changed and the defect of the surface of the first oxide layer is repaired after the first oxide layer is subjected to an annealing process, the wet etching rate can be reduced when wet etching is performed, so that the uniformity of the top of the first oxide layer is improved after wet etching, and the influence on the subsequent process due to poor uniformity of the top of the first oxide layer is reduced, so that the electrical performance of a device is improved.
Specific embodiments of the present invention will be described in more detail below with reference to the drawings. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.
Fig. 1 is a flowchart of a method for manufacturing a semiconductor device according to this embodiment. The embodiment provides a method for manufacturing a semiconductor device, which reduces the influence on the subsequent process caused by poor top uniformity of a first oxide layer by improving the top uniformity of the first oxide layer, so as to improve the electrical performance of the device.
Referring to fig. 1, the method for manufacturing the semiconductor device includes:
step S1: providing a substrate, and forming a plurality of grid grooves in the substrate;
step S2: forming a first oxide layer on the inner wall of the gate trench;
step S3: performing an annealing process on the first oxide layer;
step S4: filling a polysilicon layer in the gate trench; and
Step S5: and carrying out wet etching on the first oxide layer so that the top of the first oxide layer is lower than the surface of the substrate.
Fig. 2A to 2E are schematic cross-sectional views illustrating corresponding steps of a method for manufacturing a semiconductor device according to this embodiment, and the method for manufacturing a semiconductor device according to this embodiment is described in detail below with reference to fig. 2A to 2D.
Referring to fig. 2A, step S1 is performed: a substrate 10 is provided, and a number of gate trenches 20 are formed within the substrate 10.
Specifically, the substrate 10 is provided, the material of the substrate 10 includes one or more of silicon, germanium, gallium, nitrogen or carbon, a plurality of gate trenches 20 are formed in the substrate 10, and a gate structure is formed in each gate trench 20 in a subsequent process to manufacture a semiconductor device. In this embodiment, the substrate 10 may include an epitaxial layer and a substrate, and the epitaxial layer is formed on the substrate, and has the same crystal structure as the substrate, higher purity, fewer lattice defects, and controllable impurity type and concentration, and several gate trenches 20 are formed in the epitaxial layer.
Referring to fig. 2A, step S2 is performed: a first oxide layer 30 is formed on the inner walls of the gate trench 20.
Specifically, a first oxide layer 30 is formed on the inner wall of the gate trench 20, and the first oxide layer 30 extends to cover the surface of the substrate 10. In the present embodiment, the first oxide layer 30 is formed by a wet oxygen oxidation process, but is not limited to this process.
Referring to fig. 2A, step S3 is performed: an annealing process is performed on the first oxide layer 30.
Specifically, although the wet oxidation process forms the first oxide layer 30 at a relatively high speed, the compactness of the first oxide layer 30 may be poor, the fixed charge density of the first oxide layer 30 is high, and the surface defect charges of the first oxide layer 30 are more, so that the breakdown resistance of the device is poor. Therefore, an annealing process is performed on the first oxide layer 30, which can improve the compactness of the first oxide layer 30, and a long-time high-temperature annealing process can repair defects on the surface of the first oxide layer 30, improve the quality of the first oxide layer 30, and improve the breakdown resistance of the device. In this embodiment, the temperature of the annealing process may be 950-1150 ℃, such as 950 ℃, 1000 ℃, 1150 ℃, but is not limited to this temperature range; the time of the annealing process may be 1 to 4 hours, such as 1 hour, 2 hours, 4 hours, but is not limited to this temperature; the process gas of the annealing process may be hydrogen and/or nitrogen, for example, hydrogen, nitrogen, a mixed gas of hydrogen and nitrogen, but is not limited to this process gas, and may be other inert gases.
Referring to fig. 2B and 2C, step S4 is performed: a polysilicon layer 40 is filled in the gate trench 20.
Specifically, the polysilicon layer 40 is filled in the gate trench 20, and the polysilicon layer 40 extends to cover the surface of the first oxide layer 30. Further, the polysilicon layer 40 is etched to remove the polysilicon layer 40 on the surface of the substrate 10 and a portion of the thickness of the polysilicon layer in the gate trench 20, so that the top of the polysilicon layer 40 in the gate trench 20 is lower than the surface of the substrate 10.
Referring to fig. 2D, step S5 is performed: the first oxide layer 30 is wet etched such that the top of the first oxide layer 30 is lower than the surface of the substrate 10.
Specifically, the first oxide layer 30 is wet etched, and the side of the first oxide layer 30 close to the polysilicon layer 40 will be contacted with the etchant in the wet etching, so that the side of the first oxide layer 30 close to the polysilicon layer 40 is etched earlier than the other side of the first oxide layer 30 away from the polysilicon layer 40. Since the annealing process is performed on the first oxide layer 30 in step S3, the compactness of the first oxide layer 30 is improved, the etching rate is slowed down when the wet etching is performed, and after the wet etching, the difference between the height of one side of the first oxide layer 30 close to the polysilicon layer 40 and the height of the other side of the first oxide layer 30 away from the polysilicon layer 40 (shown in the dashed box of fig. 2D) is reduced, i.e., the top uniformity of the first oxide layer 30 is improved. After wet etching the first oxide layer 30, the top of the first oxide layer 30 is lower than the top of the polysilicon layer 40, so that an opening is formed between the surface of the substrate 10 and the top of the first oxide layer 30.
Referring to fig. 2E, further, after the wet etching is performed on the first oxide layer 30, a second oxide layer 50 is further formed on the inner wall of the opening, since the uniformity of the top of the first oxide layer 30 is improved after step S5, after the second oxide layer 50 is formed, the uniformity of the second oxide layer 50 is improved, specifically, the thickness of the second oxide layer 50 near the top end of the first oxide layer 30 is increased, the sharp corner defect is avoided at the end of the second oxide layer 50 near the top of the first oxide layer 30, the uniformity of the thickness of the second oxide layer 50 is improved, the uniformity of the second oxide layer 50 is improved, the reliability of the gate oxide layer is increased, and finally, the electrical performance of the device is improved.
In summary, in the method for manufacturing a semiconductor device provided by the present invention, a plurality of gate trenches are formed in the substrate, a first oxide layer is formed on an inner wall of the gate trench, and then an annealing process is performed on the first oxide layer, so as to change the compactness of the first oxide layer and enhance the breakdown resistance of the device; furthermore, filling a polysilicon layer in the gate trench, and performing wet etching on the first oxide layer so that the top of the first oxide layer is lower than the surface of the substrate; because the compactness of the first oxide layer is changed and the defect of the surface of the first oxide layer is repaired after the first oxide layer is subjected to an annealing process, the wet etching rate can be reduced when wet etching is performed, so that the uniformity of the top of the first oxide layer is improved after wet etching, and the influence on the subsequent process due to poor uniformity of the top of the first oxide layer is reduced, so that the electrical performance of a device is improved.
The foregoing is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Any person skilled in the art will make any equivalent substitution or modification to the technical solution and technical content disclosed in the invention without departing from the scope of the technical solution of the invention, and the technical solution of the invention is not departing from the scope of the invention.
Claims (6)
1. A method of manufacturing a semiconductor device, comprising:
providing a substrate, and forming a plurality of grid grooves in the substrate;
Forming a first oxide layer on the inner wall of the grid electrode groove by adopting a wet oxygen oxidation process;
An annealing process is carried out on the first oxide layer, wherein the temperature of the annealing process is 950-1150 ℃, the time of the annealing process is 1-4 hours, and the process gas of the annealing process is hydrogen and/or nitrogen;
Filling a polysilicon layer in the gate trench; and
And carrying out wet etching on the first oxide layer so that the top of the first oxide layer is lower than the surface of the substrate.
2. The method for manufacturing a semiconductor device according to claim 1, wherein the first oxide layer is further extended to cover a surface of the substrate when the first oxide layer is formed on an inner wall of the gate trench.
3. The method of manufacturing a semiconductor device according to claim 2, wherein the polysilicon layer further extends to cover a surface of the first oxide layer when the polysilicon layer is filled in the gate trench.
4. The method for manufacturing a semiconductor device according to claim 3, further comprising, before wet etching the first oxide layer:
And etching the polysilicon layer to remove the polysilicon layer on the surface of the substrate and the polysilicon layer with partial thickness in the gate trench, so that the top of the polysilicon layer in the gate trench is lower than the surface of the substrate.
5. The method of manufacturing a semiconductor device according to claim 1, wherein after wet etching the first oxide layer, an opening is formed between a surface of the substrate and a top of the first oxide layer.
6. The method for manufacturing a semiconductor device according to claim 5, wherein a second oxide layer is further formed on an inner wall of the opening after wet etching the first oxide layer.
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| CN202110461229.5A CN113192839B (en) | 2021-04-27 | 2021-04-27 | Method for manufacturing semiconductor device |
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| CN202110461229.5A CN113192839B (en) | 2021-04-27 | 2021-04-27 | Method for manufacturing semiconductor device |
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| CN113192839B true CN113192839B (en) | 2024-05-10 |
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| CN101207154A (en) * | 2006-12-22 | 2008-06-25 | 万国半导体股份有限公司 | Split gate formation with high density plasma (HDP) oxide layer as inter-polysilicon insulation layer |
| CN101635271A (en) * | 2009-06-09 | 2010-01-27 | 上海宏力半导体制造有限公司 | Fabricating method of shallow trench isolation structure |
| CN110034182A (en) * | 2019-03-13 | 2019-07-19 | 上海华虹宏力半导体制造有限公司 | The manufacturing method of trench-gate device with shield grid |
| CN110400841A (en) * | 2018-04-24 | 2019-11-01 | 世界先进积体电路股份有限公司 | Semiconductor device and its manufacturing method |
| CN112133637A (en) * | 2020-11-30 | 2020-12-25 | 中芯集成电路制造(绍兴)有限公司 | Method for manufacturing semiconductor device with shielded gate trench |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101207154A (en) * | 2006-12-22 | 2008-06-25 | 万国半导体股份有限公司 | Split gate formation with high density plasma (HDP) oxide layer as inter-polysilicon insulation layer |
| CN101635271A (en) * | 2009-06-09 | 2010-01-27 | 上海宏力半导体制造有限公司 | Fabricating method of shallow trench isolation structure |
| CN110400841A (en) * | 2018-04-24 | 2019-11-01 | 世界先进积体电路股份有限公司 | Semiconductor device and its manufacturing method |
| CN110034182A (en) * | 2019-03-13 | 2019-07-19 | 上海华虹宏力半导体制造有限公司 | The manufacturing method of trench-gate device with shield grid |
| CN112133637A (en) * | 2020-11-30 | 2020-12-25 | 中芯集成电路制造(绍兴)有限公司 | Method for manufacturing semiconductor device with shielded gate trench |
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