CN113192839B - Method for preparing semiconductor device - Google Patents

Abstract

The invention provides a preparation method of a semiconductor device, which comprises the following steps: providing a substrate, and forming a plurality of grid grooves in the substrate; forming a first oxide layer on the inner wall of the gate trench; performing an annealing process on the first oxide layer; filling a polysilicon layer in the gate trench; wet etching is carried out on the first oxide layer so that the top of the first oxide layer is lower than the surface of the substrate; the invention improves the electric performance of the device by improving the uniformity of the top of the first oxide layer.

Description

Method for preparing semiconductor device

Technical Field

The present invention relates to the field of semiconductor technology, and in particular to a method for preparing a semiconductor device.

Background technique

The shielded gate trench MOSFET is a typical trench MOSFET tube, which has the advantage of low conduction loss of the traditional trench MOSFET tube, so the shielded gate trench MOSFET tube is widely used. In the manufacturing process of the shielded gate trench MOSFET tube, the first oxide layer is first formed in the gate trench, and the first oxide layer covers the inner wall of the gate trench, and then a polysilicon layer is formed in the gate trench, and the polysilicon layer is filled in the gate trench. When the polysilicon layer is formed, the polysilicon layer will cover the surface of the substrate. After etching the polysilicon layer, the polysilicon layer on the surface of the substrate is removed and the polysilicon layer in the gate trench is retained; then the first oxide layer is etched to form an opening, and the subsequent process forms a gate polysilicon layer in the opening to manufacture the gate. However, after etching the first oxide layer, the top of the first oxide layer may appear more obviously uneven, which affects the formation of the subsequent second oxide layer and ultimately affects the electrical performance of the device.

Summary of the invention

The object of the present invention is to provide a method for preparing a semiconductor device, by improving the uniformity of the top of the first oxide layer, reducing the influence of the poor uniformity of the top of the first oxide layer on subsequent processes, so as to improve the electrical performance of the device.

In order to achieve the above object, the present invention provides a method for preparing a semiconductor device, comprising:

Providing a substrate, forming a plurality of gate trenches in the substrate;

forming a first oxide layer on an inner wall of the gate trench;

performing an annealing process on the first oxide layer;

filling a polysilicon layer in the gate trench; and,

The first oxide layer is wet-etched so that a top of the first oxide layer is lower than a surface of the substrate.

Optionally, the temperature of the annealing process is 950°C to 1150°C.

Optionally, the annealing process lasts for 1 hour to 4 hours.

Optionally, the process gas of the annealing process is hydrogen and/or nitrogen.

Optionally, the first oxide layer is formed on the inner wall of the gate trench by a wet oxygen oxidation process.

Optionally, when the first oxide layer is formed on the inner wall of the gate trench, the first oxide layer also extends to cover the surface of the substrate.

Optionally, when the polysilicon layer is filled in the gate trench, the polysilicon layer also extends to cover the surface of the first oxide layer.

Optionally, before wet etching the first oxide layer, the method further includes:

The polysilicon layer is etched to remove the polysilicon layer on the surface of the substrate and a portion of the polysilicon layer in the gate trench, so that the top of the polysilicon layer in the gate trench is lower than the surface of the substrate.

Optionally, after the first oxide layer is wet-etched, an opening is formed between the surface of the substrate and the top of the first oxide layer.

Optionally, after the first oxide layer is wet-etched, a second oxide layer is further formed on the inner wall of the opening.

In a method for preparing a semiconductor device provided by the present invention, a plurality of gate trenches are formed in the substrate, a first oxide layer is formed on the inner wall of the gate trench, and then an annealing process is performed on the first oxide layer to change the compactness of the first oxide layer and enhance the device's anti-breakdown capability; further, a polysilicon layer is filled in the gate trench, and the first oxide layer is wet-etched so that the top of the first oxide layer is lower than the surface of the substrate; since the compactness of the first oxide layer is changed and the surface defects of the first oxide layer are repaired after the annealing process, the wet etching rate can be reduced during wet etching, so that after wet etching, the uniformity of the top of the first oxide layer is improved, and the influence of the poor uniformity of the top of the first oxide layer on subsequent processes is reduced, so as to improve the electrical performance of the device.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

2A to 2E are cross-sectional schematic diagrams of corresponding steps of a method for preparing a semiconductor device provided in one embodiment of the present invention;

Wherein, the accompanying drawings are marked as follows:

10 - substrate; 20 - gate trench; 30 - first oxide layer; 40 - polysilicon layer; 50 - second oxide layer.

Detailed ways

In the manufacturing process of shielded gate trench MOSFET tube, a first oxide layer is formed in the gate trench by a wet oxygen oxidation process, and the first oxide layer covers the inner wall of the gate trench. Although the wet oxygen oxidation process forms the first oxide layer at a faster speed, the first oxide layer has poor compactness, a large fixed charge density, and a large number of surface defect charges of the first oxide layer, resulting in poor anti-breakdown capability of the device. A polysilicon layer is filled in the gate trench. When the polysilicon layer is formed, the polysilicon layer also covers the surface of the substrate. The first oxide layer is wet-etched so that the top of the first oxide layer is lower than the surface of the substrate to form an opening. After the polysilicon layer is wet-etched, the polysilicon layer on the surface of the substrate is removed and the polysilicon layer in the gate trench is retained; however, the side of the first oxide layer close to the polysilicon layer will first contact the etchant in the wet etching, and will be etched earlier than the other side of the first oxide layer away from the polysilicon layer, and the first oxide layer has poor compactness, and the etching rate is fast during wet etching. After wet etching, the morphology of the side of the first oxide layer close to the polysilicon layer and the other side of the first oxide layer away from the polysilicon layer are greatly different, that is, the top uniformity of the first oxide layer is poor. The top uniformity of the first oxide layer is poor. When the second oxide layer is formed in the opening in the subsequent process, the top uniformity of the first oxide layer is poor, which will affect the morphology of the second oxide layer after formation, resulting in poor uniformity of the second oxide layer, such as uneven thickness of the second oxide layer, and the second oxide layer is used as a gate oxide layer, and the second oxide layer has poor uniformity, which will affect the electrical performance of the device.

Therefore, in a method for preparing a semiconductor device provided by the present invention, a plurality of gate trenches are formed in the substrate, a first oxide layer is formed on the inner wall of the gate trench, and then an annealing process is performed on the first oxide layer to change the compactness of the first oxide layer and enhance the device's anti-breakdown capability; further, a polysilicon layer is filled in the gate trench, and the first oxide layer is wet-etched so that the top of the first oxide layer is lower than the surface of the substrate; since the compactness of the first oxide layer is changed and the surface defects of the first oxide layer are repaired after the annealing process, the wet etching rate can be reduced during wet etching, so that after wet etching, the uniformity of the top of the first oxide layer is improved, and the influence of the poor uniformity of the top of the first oxide layer on subsequent processes is reduced, so as to improve the electrical performance of the device.

The specific implementation of the present invention will be described in more detail below in conjunction with the schematic diagram. The advantages and features of the present invention will become clearer based on the following description. It should be noted that the drawings are all in a very simplified form and are not in exact proportions, and are only used to facilitate and clearly assist in explaining the purpose of the embodiments of the present invention.

Figure 1 is a flow chart of a method for preparing a semiconductor device provided in this embodiment. This embodiment provides a method for preparing a semiconductor device, which improves the uniformity of the top of the first oxide layer to reduce the impact of poor uniformity of the top of the first oxide layer on subsequent processes, so as to improve the electrical performance of the device.

Referring to FIG. 1 , the method for preparing the semiconductor device includes:

Step S1: providing a substrate, and forming a plurality of gate trenches in the substrate;

Step S2: forming a first oxide layer on the inner wall of the gate trench;

Step S3: performing an annealing process on the first oxide layer;

Step S4: filling a polysilicon layer in the gate trench; and,

Step S5: wet-etching the first oxide layer so that the top of the first oxide layer is lower than the surface of the substrate.

2A to 2E are cross-sectional schematic diagrams of corresponding steps of the method for preparing a semiconductor device provided in this embodiment. The method for preparing a semiconductor device provided in this embodiment will be described in detail below in conjunction with FIGS. 2A to 2D .

Please refer to FIG. 2A , and perform step S1 : providing a substrate 10 , and forming a plurality of gate trenches 20 in the substrate 10 .

Specifically, the substrate 10 is provided, and the material of the substrate 10 includes one or more of silicon, germanium, gallium, nitrogen or carbon. A plurality of gate trenches 20 are formed in the substrate 10, and a gate structure is formed in each gate trench 20 in a subsequent process to manufacture a semiconductor device. In this embodiment, the substrate 10 may include an epitaxial layer and a substrate, and the epitaxial layer is grown on the substrate. The epitaxial layer has the same crystal structure as the substrate, has a higher purity, has fewer lattice defects, and can also control the impurity type and concentration. The plurality of gate trenches 20 are formed in the epitaxial layer.

Please refer to FIG. 2A , and perform step S2 : forming a first oxide layer 30 on the inner wall of the gate trench 20 .

Specifically, a first oxide layer 30 is formed on the inner wall of the gate trench 20, and the first oxide layer 30 extends to cover the surface of the substrate 10. In this embodiment, the first oxide layer 30 is formed by a wet oxygen oxidation process, but is not limited to this process.

Please refer to FIG. 2A , and perform step S3 : performing an annealing process on the first oxide layer 30 .

Specifically, although the wet oxygen oxidation process forms the first oxide layer 30 at a faster speed, it will result in poor compactness of the first oxide layer 30, large fixed charge density of the first oxide layer 30, and more surface defect charges of the first oxide layer 30, resulting in poor anti-breakdown capability of the device. Therefore, an annealing process is performed on the first oxide layer 30, and the annealing process can improve the compactness of the first oxide layer 30, and the use of a long high temperature annealing can repair the surface defects of the first oxide layer 30, improve the quality of the first oxide layer 30, and improve the anti-breakdown capability of the device. In this embodiment, the temperature of the annealing process can be 950°C to 1150°C, such as 950°C, 1000°C, 1150°C, but not limited to this temperature range; the time of the annealing process can be 1 hour to 4 hours, such as 1 hour, 2 hours, 4 hours, but not limited to this temperature; the process gas of the annealing process can be hydrogen and/or nitrogen, such as hydrogen, nitrogen, a mixed gas of hydrogen and nitrogen, but not limited to this process gas, and can also be other inert gases.

Please refer to FIG. 2B and FIG. 2C , and perform step S4 : filling the gate trench 20 to form a polysilicon layer 40 .

Specifically, the polysilicon layer 40 is filled and formed in the gate trench 20, and the polysilicon layer 40 extends to cover the surface of the first oxide layer 30. Then, the polysilicon layer 40 is etched to remove the polysilicon layer 40 on the surface of the substrate 10 and a portion of the polysilicon layer in the gate trench 20, so that the top of the polysilicon layer 40 in the gate trench 20 is lower than the surface of the substrate 10.

Referring to FIG. 2D , step S5 is performed: wet etching is performed on the first oxide layer 30 so that the top of the first oxide layer 30 is lower than the surface of the substrate 10 .

Specifically, the first oxide layer 30 is wet-etched, and the side of the first oxide layer 30 close to the polysilicon layer 40 will first contact the etchant in the wet etching, resulting in the first oxide layer 30 The side close to the polysilicon layer 40 is etched earlier than the other side of the first oxide layer 30 away from the polysilicon layer 40. Since the first oxide layer 30 is subjected to an annealing process in step S3, the compactness of the first oxide layer 30 is improved, and the etching rate is slowed down during the wet etching. After the wet etching, the height difference between the side of the first oxide layer 30 close to the polysilicon layer 40 and the other side of the first oxide layer 30 away from the polysilicon layer 40 is reduced (as shown in the virtual box of FIG. 2D), that is, the uniformity of the top of the first oxide layer 30 is improved. After the first oxide layer 30 is wet-etched, the top of the first oxide layer 30 is lower than the top of the polysilicon layer 40, so that an opening is formed between the surface of the substrate 10 and the top of the first oxide layer 30.

Please refer to Figure 2E. Further, after the first oxide layer 30 is wet-etched, a second oxide layer 50 is formed on the inner wall of the opening. Since the uniformity of the top of the first oxide layer 30 is improved after step S5, after the second oxide layer 50 is formed, the uniformity of the second oxide layer 50 is improved. The specific improvement is that the thickness of the second oxide layer 50 at one end close to the top of the first oxide layer 30 is increased to avoid the formation of a sharp corner defect at one end of the second oxide layer 50 close to the top of the first oxide layer 30, so that the overall thickness uniformity of the second oxide layer 50 is improved. The second oxide layer 50 serves as a gate oxide layer, which improves the uniformity of the second oxide layer 50, increases the reliability of the gate oxide layer, and ultimately improves the electrical performance of the device.

In summary, in a method for preparing a semiconductor device provided by the present invention, a plurality of gate trenches are formed in the substrate, a first oxide layer is formed on the inner wall of the gate trench, and then an annealing process is performed on the first oxide layer to change the compactness of the first oxide layer and enhance the device's anti-breakdown capability; further, a polysilicon layer is filled in the gate trench, and the first oxide layer is wet-etched so that the top of the first oxide layer is lower than the surface of the substrate; since the first oxide layer has undergone the annealing process, the compactness of the first oxide layer is changed and the surface defects of the first oxide layer are repaired, the wet etching rate can be reduced during wet etching, so that after wet etching, the uniformity of the top of the first oxide layer is improved, and the influence of the poor uniformity of the top of the first oxide layer on subsequent processes is reduced, so as to improve the electrical performance of the device.

The above is only a preferred embodiment of the present invention and does not limit the present invention in any way. Any technician in the relevant technical field, without departing from the scope of the technical solution of the present invention, makes any form of equivalent replacement or modification to the technical solution and technical content disclosed in the present invention, which does not depart from the content of the technical solution of the present invention and still falls within the protection scope of the present invention.

Claims (6)

1. A method for preparing a semiconductor device, comprising: Providing a substrate, forming a plurality of gate trenches in the substrate; forming a first oxide layer on the inner wall of the gate trench by a wet oxygen oxidation process; Performing an annealing process on the first oxide layer, wherein the temperature of the annealing process is 950° C. to 1150° C., the time of the annealing process is 1 hour to 4 hours, and the process gas of the annealing process is hydrogen and/or nitrogen; filling a polysilicon layer in the gate trench; and, The first oxide layer is wet-etched so that a top of the first oxide layer is lower than a surface of the substrate. 2 . The method for preparing a semiconductor device according to claim 1 , wherein when the first oxide layer is formed on the inner wall of the gate trench, the first oxide layer also extends to cover the surface of the substrate. 3 . The method for preparing a semiconductor device according to claim 2 , wherein when the polysilicon layer is filled in the gate trench, the polysilicon layer also extends to cover the surface of the first oxide layer. 4. The method for preparing a semiconductor device according to claim 3, characterized in that before wet etching the first oxide layer, it further comprises: The polysilicon layer is etched to remove the polysilicon layer on the surface of the substrate and a portion of the polysilicon layer in the gate trench, so that the top of the polysilicon layer in the gate trench is lower than the surface of the substrate. 5 . The method for preparing a semiconductor device according to claim 1 , wherein after the first oxide layer is wet-etched, an opening is formed between the surface of the substrate and the top of the first oxide layer. 6 . The method for manufacturing a semiconductor device according to claim 5 , wherein after the first oxide layer is wet-etched, a second oxide layer is formed on an inner wall of the opening.