CN103681449A - Method for forming shallow trench isolation region - Google Patents

Method for forming shallow trench isolation region Download PDF

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Publication number
CN103681449A
CN103681449A CN201210338682.8A CN201210338682A CN103681449A CN 103681449 A CN103681449 A CN 103681449A CN 201210338682 A CN201210338682 A CN 201210338682A CN 103681449 A CN103681449 A CN 103681449A
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CN
China
Prior art keywords
silicon nitride
semiconductor substrate
nitride layer
liner oxidation
silicon
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Pending
Application number
CN201210338682.8A
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Chinese (zh)
Inventor
张飞
杨玲
夏雁宾
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Corp
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Semiconductor Manufacturing International Shanghai Corp
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Priority to CN201210338682.8A priority Critical patent/CN103681449A/en
Publication of CN103681449A publication Critical patent/CN103681449A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02321—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer
    • H01L21/02323—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer introduction of oxygen
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02359—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment to change the surface groups of the insulating layer

Abstract

The invention discloses a method for forming a shallow trench isolation region. The method comprises the following steps: sequentially forming an isolation oxidation layer and a silicon nitride layer on a semiconductor substrate; sequentially etching the silicon nitride layer, the isolation oxidation layer and the semiconductor substrate, and forming a trench inside the semiconductor substrate; growing a liner silicon nitride layer on the surface inside the trench; filling and polishing an oxide inside the trench, forming the shallow trench isolation region, and eliminating the silicon nitride layer. Through the adoption of the method, the quality of a liner silicon nitride film at an AA corner is improved.

Description

Form the method for shallow channel isolation area
Technical field
The present invention relates to the manufacturing technology of semiconductor device, particularly a kind of method that forms shallow channel isolation area.
Background technology
The concrete manufacture method of prior art shallow channel isolation area (STI) comprises the steps:
Step 11, in Semiconductor substrate 100 thermal oxide growth isolating oxide layer 101, with protection active area, in the follow-up process of removing silicon nitride layer, avoiding chemistry stains, and as the stress-buffer layer between silicon nitride layer and silicon substrate, described Semiconductor substrate is silicon substrate;
Step 12, at the surface deposition silicon nitride layer 102 of described isolating oxide layer 101; Wherein, the silicon nitride layer that in this step, deposition obtains is the mask material that one deck is firm;
The etching of step 13, shallow trench: etch silicon nitride layer 102, isolating oxide layer 101 and Semiconductor substrate 100 successively, at the interior formation groove of described Semiconductor substrate 100;
The growth of step 14, trench liner silica 103, at the inner superficial growth one deck of groove liner oxidation silicon 103, this liner oxidation silicon 103 is for improving the interfacial characteristics between Semiconductor substrate and the oxide of follow-up filling;
Step 15, described liner oxidation silicon 103 is carried out to annealing in process,
Step 16, trench oxide 104 are filled and polishing, adopt the method for high density plasma CVD (HDPCVD), and fill oxide in groove, then carries out the polishing of oxide; Wherein, the silicon nitride layer that deposition obtains in step 12 can be protected active area in the process of carrying out this step, serves as the barrier material of polishing, prevents the excessive polishing of oxide;
Concrete, HDPCVD adopts the method for deposition limit, limit etching to fill, and uses synchronous deposition and etching, and the speed of deposition is greater than the speed of etching, will reduce like this generation in cavity (via) in groove.
Step 17, remove described silicon nitride layer 102.
According to foregoing description, step 11 to the structural representation of 16 formation as shown in Figure 1a, the structural representation that step 17 forms is as shown in Figure 1 b.
It should be noted that, in forming the process of shallow channel isolation area, can in a plurality of steps, use and there is corrosive acid-base solution, for example, while carrying out the polishing of oxide in step 16, polishing acid solution may enter into semiconductor substrate surface from the gap between S TI and active area (AA) in the process of grinding, and not only corrodes the isolating oxide layer of AA corner, and the semiconductor substrate surface of corrosion AA corner, in Fig. 1 b, there is defect as shown in the figure.Again for example, step 17 is removed silicon nitride layer 102 also can use acid solution, at this moment, if the liner oxidation silicon fiml of AA corner is of low quality, is also easy to be subject to sour corrosion, and then erodes to semiconductor substrate surface.Follow-uply on the active area of both sides, shallow channel isolation area, form polysilicon gate, very possible because the existence of depression makes etch polysilicon grid incomplete, cause two polysilicon gates on active area to be electrical connected.Therefore how to improve the quality of AA corner liner oxidation silicon fiml, become the problem of paying close attention in the industry.
Summary of the invention
In view of this, the invention provides a kind of method that forms shallow channel isolation area, can improve the liner oxidation silicon fiml quality of AA corner.
Technical scheme of the present invention is achieved in that
A method that forms shallow channel isolation area, the method comprises:
In Semiconductor substrate, form successively isolating oxide layer and silicon nitride layer;
Etch silicon nitride layer, isolating oxide layer and Semiconductor substrate form groove in described Semiconductor substrate successively;
At the inner superficial growth one deck of described groove liner oxidation silicon;
Described liner oxidation silicon is carried out to annealing in process;
In groove, carry out filling and the polishing of oxide, form shallow channel isolation area, and remove described silicon nitride layer;
When described liner oxidation silicon is carried out to annealing in process, pass into oxygen to improve the formation quality of liner oxidation silicon.
Adopt high density plasma CVD HDPCVD method fill oxide in groove.
From such scheme, can find out, the present invention is forming shallow channel isolation area, when liner oxidation silicon is carried out to annealing in process, also pass into oxygen, further improve the formation quality of liner oxidation silicon, especially the liner oxidation silicon fiml quality of AA corner, can be connected closelyr with isolating oxide layer, make it more can resist the corrosion of acid-base solution, thereby avoid AA corner to occur depression.
Accompanying drawing explanation
Fig. 1 a to Fig. 1 b is the structural representation that prior art forms the detailed process of shallow channel isolation area.
Fig. 2 a to 2b is the structural representation that the present invention forms shallow channel isolation area detailed process.
Fig. 2 is the schematic flow sheet of shallow channel isolation area of the present invention manufacture method.
Embodiment
For making object of the present invention, technical scheme and advantage clearer, referring to the accompanying drawing embodiment that develops simultaneously, the present invention is described in further detail.
The concrete manufacturing process schematic diagram of shallow channel isolation area of the present invention refers to Fig. 2 a to Fig. 2 b, and the schematic flow sheet of concrete manufacture method as shown in Figure 2, comprises the steps:
Step 21, in Semiconductor substrate 100, form successively isolating oxide layer 101 and silicon nitride layer 102;
Particularly, thermal oxide growth isolating oxide layer 101 in Semiconductor substrate 100, stains to protect active area to avoid chemistry in the follow-up process of removing silicon nitride layer, and as the stress-buffer layer between silicon nitride layer and silicon substrate; Then at the surface deposition silicon nitride layer 102 of described isolating oxide layer 101; Wherein, the silicon nitride layer that in this step, deposition obtains is the mask material that one deck is firm;
The etching of step 22, shallow trench: etch silicon nitride layer 102, isolating oxide layer 101 and Semiconductor substrate 100 successively, at the interior formation groove of described Semiconductor substrate 100;
The growth of step 23, trench liner silica 103, at the inner superficial growth one deck of groove liner oxidation silicon 103, this liner oxidation silicon 103 is for improving the interfacial characteristics between Semiconductor substrate and the oxide of follow-up filling;
Step 24, described liner oxidation silicon 103 is carried out to annealing in process, and pass into oxygen to improve the formation quality of liner oxidation silicon 103;
This step is key of the present invention, and prior art is only carried out annealing in process to liner oxidation silicon, but the formation of liner oxidation silicon 103 in step 23 is by passing into oxygen, makes oxygen and trenched side-wall pasc reaction form liner oxidation silicon.When in step 23, oxygen passes into, reaction speed is fast, so the liner oxidation silicon 103 forming is of low quality, film is fine and close not, have a lot of defects, for example, have SiON key or the SiO key that complete reaction does not occur, the present invention passes into oxygen in the process of annealing, oxygen is under the high temperature action of annealing, and the reaction equation of generation is:
SiON+O 2→SiO 2+NO 2
SiO+O 2→SiO 2
From above-mentioned reaction, can find out, there is SiON key or the SiO key of defect, in annealing process, occur fully to react with oxygen, formed fine and close silicon oxide film, greatly improved the quality of liner oxidation silicon, especially the liner oxidation silicon fiml quality of AA corner, can be connected closelyr with isolating oxide layer, make it more can resist the corrosion of acid-base solution, thereby avoid AA corner to occur corrosion pitting.
Step 25, the filling of carrying out oxide in groove and polishing, form shallow channel isolation area;
Wherein, the filling that the embodiment of the present invention is carried out oxide in groove adopts HDPCVD method to form silicon oxide layer, can certainly adopt other chemical gaseous phase depositing process, such as the method for aumospheric pressure cvd (APCVD) etc.
Step 26, remove described silicon nitride layer 102.
So far, embodiment of the present invention shallow channel isolation area forms.The structural representation forming according to step 21 to step 25 as shown in Figure 2 a.The structural representation that step 26 forms as shown in Figure 2 b.
To sum up, by the present invention, form the method for shallow channel isolation area, improve the liner oxidation silicon fiml quality of LiaoAA corner, can effectively reduce AA corner and occur corrosion default, so just can effectively avoid the problem that polysilicon gate is electrically connected to occur, thereby improve the performance of semiconductor device.
The foregoing is only preferred embodiment of the present invention, in order to limit the present invention, within the spirit and principles in the present invention not all, any modification of making, be equal to replacement, improvement etc., within all should being included in the scope of protection of the invention.

Claims (2)

1. a method that forms shallow channel isolation area, the method comprises:
In Semiconductor substrate, form successively isolating oxide layer and silicon nitride layer;
Etch silicon nitride layer, isolating oxide layer and Semiconductor substrate form groove in described Semiconductor substrate successively;
At the inner superficial growth one deck of described groove liner oxidation silicon;
Described liner oxidation silicon is carried out to annealing in process;
In groove, carry out filling and the polishing of oxide, form shallow channel isolation area, and remove described silicon nitride layer;
It is characterized in that, when described liner oxidation silicon is carried out to annealing in process, pass into oxygen to improve the formation quality of liner oxidation silicon.
2. the method for claim 1, is characterized in that, adopts high density plasma CVD HDPCVD method fill oxide in groove.
CN201210338682.8A 2012-09-13 2012-09-13 Method for forming shallow trench isolation region Pending CN103681449A (en)

Priority Applications (1)

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Application Number Priority Date Filing Date Title
CN201210338682.8A CN103681449A (en) 2012-09-13 2012-09-13 Method for forming shallow trench isolation region

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9704872B1 (en) 2016-01-07 2017-07-11 Micron Technology, Inc. Memory device and fabricating method thereof
CN115472554A (en) * 2021-06-11 2022-12-13 和舰芯片制造(苏州)股份有限公司 Deep trench silicon dioxide filling method and wafer

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6817903B1 (en) * 2000-08-09 2004-11-16 Cypress Semiconductor Corporation Process for reducing leakage in an integrated circuit with shallow trench isolated active areas
CN101207063A (en) * 2006-12-18 2008-06-25 中芯国际集成电路制造(上海)有限公司 Method for forming shallow trench isolation
CN102122629A (en) * 2010-01-08 2011-07-13 中芯国际集成电路制造(上海)有限公司 Method for manufacturing lining oxide layer of shallow trench isolation (STI)

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6817903B1 (en) * 2000-08-09 2004-11-16 Cypress Semiconductor Corporation Process for reducing leakage in an integrated circuit with shallow trench isolated active areas
CN101207063A (en) * 2006-12-18 2008-06-25 中芯国际集成电路制造(上海)有限公司 Method for forming shallow trench isolation
CN102122629A (en) * 2010-01-08 2011-07-13 中芯国际集成电路制造(上海)有限公司 Method for manufacturing lining oxide layer of shallow trench isolation (STI)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9704872B1 (en) 2016-01-07 2017-07-11 Micron Technology, Inc. Memory device and fabricating method thereof
CN115472554A (en) * 2021-06-11 2022-12-13 和舰芯片制造(苏州)股份有限公司 Deep trench silicon dioxide filling method and wafer

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Application publication date: 20140326

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