CN116895523A - Method for forming polycrystalline silicon layer - Google Patents
Method for forming polycrystalline silicon layer Download PDFInfo
- Publication number
- CN116895523A CN116895523A CN202310889600.7A CN202310889600A CN116895523A CN 116895523 A CN116895523 A CN 116895523A CN 202310889600 A CN202310889600 A CN 202310889600A CN 116895523 A CN116895523 A CN 116895523A
- Authority
- CN
- China
- Prior art keywords
- film layer
- thin film
- temperature
- layer
- wafer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 42
- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 30
- 239000010409 thin film Substances 0.000 claims abstract description 57
- 229920005591 polysilicon Polymers 0.000 claims abstract description 28
- 239000010408 film Substances 0.000 claims abstract description 25
- 238000000151 deposition Methods 0.000 claims abstract description 22
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 230000008021 deposition Effects 0.000 claims abstract description 9
- 235000012431 wafers Nutrition 0.000 claims description 33
- 238000001556 precipitation Methods 0.000 abstract description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000001816 cooling Methods 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000013467 fragmentation Methods 0.000 description 1
- 238000006062 fragmentation reaction Methods 0.000 description 1
- 239000013307 optical fiber Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
Abstract
The application discloses a polysilicon layer forming method, which comprises the following steps: s1: providing a wafer, wherein the wafer comprises a substrate with a groove, a hard mask layer is formed on the substrate, and the wafer is placed in a process chamber of a deposition machine; s2: adjusting the temperature of the process chamber to a first temperature, and depositing a first film layer on the hard mask layer at the first temperature, wherein the first film layer fills the groove; s3: depositing a second thin film layer on the first thin film layer at a first temperature; s4: depositing a third thin film layer on the second thin film layer at the first temperature; s5: raising the temperature of the process chamber to a second temperature and depositing a fourth thin film layer on the third thin film layer at the second temperature; the first film layer, the second film layer and the third film layer are all doped polysilicon, and the fourth film layer is undoped polysilicon. According to the application, the undoped polysilicon layer is formed on the uppermost layer, so that the precipitation of the P element can be inhibited, and the pollution to a machine and a wafer is reduced.
Description
Technical Field
The application relates to the technical field of semiconductor manufacturing, in particular to a polysilicon layer forming method.
Background
The vertical furnace tube machine is one of important process equipment of the previous working procedure of a semiconductor production line, and is used for diffusion, oxidation, annealing, alloy and other processes in the industries of large-scale integrated circuits, discrete devices, power electronics, photoelectric devices, optical fibers and the like.
Deep trenches of SGT (Shielded Gate Transistor, shielded gate trenches) cause product stress problems, easily triggering alarms and causing wafer damage during gate layer operation. Currently, SGT gate (12 KA) filling typically employs a three-step distributed deposition, which reduces the risk of fragmentation but reduces the yield of FAB, and in addition, may result in P-contamination of the product due to the higher P-element doping concentration (> 2E 20) in D-POLY (doped polysilicon).
Disclosure of Invention
The application provides a polysilicon layer forming method which can solve the problems in the related art.
The application provides a polysilicon layer forming method, which comprises the following steps:
s1: providing a wafer, wherein the wafer comprises a substrate with a groove formed thereon, a hard mask layer is formed on the substrate, and the wafer is placed in a process chamber of a deposition machine;
s2: adjusting the temperature of the process chamber to a first temperature, and depositing a first thin film layer on the hard mask layer at the first temperature, wherein the first thin film layer fills the groove;
s3: depositing a second thin film layer on the first thin film layer at the first temperature;
s4: depositing a third thin film layer on the second thin film layer at the first temperature;
s5: raising the temperature of the process chamber to a second temperature and depositing a fourth thin film layer on the third thin film layer at the second temperature;
the first thin film layer, the second thin film layer and the third thin film layer are all doped polysilicon, and the fourth thin film layer is undoped polysilicon.
In some embodiments, the first temperature is 530 ℃.
In some embodiments, the second temperature is 580 ℃ -620 ℃.
In some embodiments, the first film layer has a thickness of 4000A.
In some embodiments, the second film layer has a thickness of 4000A.
In some embodiments, the third film layer and the fourth film layer have a total thickness of 4000A.
In some embodiments, the fourth film layer has a thickness greater than 500A and less than 4000A.
In some embodiments, between the S2 and S3, and between the S3S 4, the steps of: and removing the wafer boat carrying the wafers from the process chamber so as to cool the wafers.
The technical scheme of the application at least comprises the following advantages:
1. after multi-layer doped polysilicon is deposited step by step at the first temperature, a layer of undoped polysilicon is deposited on the topmost layer, and the undoped polysilicon can inhibit the precipitation of P element, so that the possibility of pollution to the wafer and the machine caused by the precipitation of P element in the wafer is reduced.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described, and it is obvious that the drawings in the description below are some embodiments of the present application, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.
Fig. 1 is a flowchart of a polysilicon layer forming method according to an exemplary embodiment of the present application;
fig. 2 to 5 are schematic views of a wafer structure during execution of a polysilicon layer forming method according to an exemplary embodiment of the present application;
fig. 6 is a graph showing the distribution of P elements with Poly depth in one case provided by an exemplary embodiment of the present application.
Reference numerals illustrate:
1. a substrate; 11. a groove; 2. a hard mask layer; 3. a first film layer; 4. a second film layer; 5. a third film layer; 6. and a fourth film layer.
Description of the embodiments
The following description of the embodiments of the present application will be made more apparent and fully hereinafter with reference to the accompanying drawings, in which some, but not all embodiments of the application are shown. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
In the description of the present application, it should be noted that the directions or positional relationships indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. are based on the directions or positional relationships shown in the drawings, are merely for convenience of describing the present application and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present application, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically or electrically connected; the two components can be directly connected or indirectly connected through an intermediate medium, or can be communicated inside the two components, or can be connected wirelessly or in a wired way. The specific meaning of the above terms in the present application will be understood in specific cases by those of ordinary skill in the art.
In addition, the technical features of the different embodiments of the present application described below may be combined with each other as long as they do not collide with each other.
Referring to fig. 1, a flowchart of a polysilicon layer forming method according to an exemplary embodiment of the present application is shown, including the steps of:
s1: a wafer is provided, the wafer including a substrate having a trench formed therein, the substrate having a hard mask layer formed thereon, the wafer being disposed in a process chamber of a deposition tool.
Illustratively, referring to fig. 2, the wafer includes a substrate 1 having a trench 11 formed therein, and a hard mask layer 2 is formed on the substrate 1. In this embodiment, the substrate 1 may be a silicon substrate, and the hard mask layer 2 may be a silicon dioxide layer. The wafers to be processed are placed in the wafer boat, and then the wafers enter the process chamber of the deposition machine along with the wafer boat, so that the subsequent deposition process is facilitated.
S2: the temperature of the process chamber is adjusted to a first temperature, and a first thin film layer is deposited on the hard mask layer at the first temperature, the first thin film layer filling the trench.
The temperature within the process chamber is illustratively adjusted to a first temperature, where the first temperature may be 530 ℃. Thereafter, referring to fig. 3, a first thin film layer 3 is deposited on the hard mask layer 2 under the condition of the first temperature, and the first thin film layer 3 fills the trench 11.
The first thin film layer 3 is doped polysilicon, and the first thin film layer 3 can be formed by chemical vapor deposition, and the thickness of the first thin film layer 3 is 4000A.
Illustratively, in some embodiments, after deposition to form the first thin film layer 3, the wafer boat loaded with wafers may be removed from the process chamber, thereby cooling the wafers with ambient temperature.
S3: a second thin film layer is deposited over the first thin film layer at a first temperature.
Illustratively, the wafer surface may be pre-cleaned to remove oxides from the wafer surface. Referring to fig. 4, a second thin film layer 4 is deposited on the first thin film layer 3 in a process chamber having a first temperature.
The second thin film layer 4 is also doped polysilicon, and the thickness thereof is 4000A.
Illustratively, in some embodiments, removal of the wafer-loaded boat from the process chamber may be performed after deposition to form the second thin film layer 4, thereby cooling the wafer with ambient temperature.
S4: a third thin film layer is deposited over the second thin film layer at the first temperature.
Illustratively, the wafer surface may be pre-cleaned to remove oxides from the wafer surface. Referring to fig. 5, a third thin film layer 5 is deposited on the second thin film layer 4 in a process chamber having a temperature of the first temperature.
Wherein the third thin film layer 5 is also doped polysilicon.
S5: the temperature of the process chamber is raised to a second temperature and a fourth thin film layer is deposited on the third thin film layer at the second temperature.
Illustratively, referring to fig. 5, after the deposition to form the third thin film layer 5, the temperature in the process chamber is raised to a second temperature and a fourth thin film layer 6 is further deposited on the third thin film layer 5. Wherein the fourth thin film layer 6 is undoped polysilicon. The stress around the groove is released due to the temperature rise, which is helpful for improving the warpage and improving the productivity.
In some embodiments, the second temperature is 580 ℃ -620 ℃, for example, the second temperature is 580 ℃, 590 ℃, 600 ℃, and so on.
In some embodiments, the total thickness of the third film layer 5 and the fourth film layer 6 is 4000A, and the thickness of the fourth film layer 6 is greater than 500A and less than 4000A, for example, the thickness of the third film layer 5 is 3000A, while the thickness of the fourth film layer 6 is 1000A. Referring to fig. 6, which shows a distribution diagram of P element with the depth of Poly under the condition of depositing the third thin film layer 5 of 3000A and the fourth thin film layer 6 of 1000A, it can be found that the surface is covered with a layer of undoped polysilicon to effectively inhibit the precipitation of P element.
According to the method for forming the polysilicon layer, disclosed by the embodiment of the application, after multiple layers of doped polysilicon are deposited in steps at the first temperature, a layer of undoped polysilicon is deposited on the topmost layer, and the undoped polysilicon can inhibit the precipitation of P element, so that the pollution to a wafer and a machine is reduced.
It is apparent that the above examples are given by way of illustration only and are not limiting of the embodiments. Other variations or modifications of the above teachings will be apparent to those of ordinary skill in the art. It is not necessary here nor is it exhaustive of all embodiments. While still being apparent from variations or modifications that may be made by those skilled in the art are within the scope of the application.
Claims (8)
1. A method of forming a polysilicon layer, comprising:
s1: providing a wafer comprising a substrate (1) with a trench (11) formed therein, the substrate (1) having a hard mask layer (2) formed thereon, the wafer being disposed in a process chamber of a deposition tool;
s2: adjusting the temperature of the process chamber to a first temperature and depositing a first thin film layer (3) on the hard mask layer (2) at the first temperature, the first thin film layer (3) filling the trench (11);
s3: -depositing a second thin film layer (4) on the first thin film layer (3) at the first temperature;
s4: -depositing a third thin film layer (5) on the second thin film layer (4) at the first temperature;
s5: raising the temperature of the process chamber to a second temperature and depositing a fourth thin film layer (6) on the third thin film layer (5) at the second temperature;
the first thin film layer (3), the second thin film layer (4) and the third thin film layer (5) are all doped polysilicon, and the fourth thin film layer (6) is undoped polysilicon.
2. The method of claim 1, wherein the first temperature is 530 ℃.
3. The method of claim 1, wherein the second temperature is 580-620 ℃.
4. The method according to claim 1, characterized in that the thickness of the first film layer (3) is 4000A.
5. The method according to claim 1, characterized in that the thickness of the second film layer (4) is 4000A.
6. The method according to claim 1, characterized in that the total thickness of the third film layer (5) and the fourth film layer (6) is 4000A.
7. The method according to claim 6, characterized in that the thickness of the fourth film layer (6) is greater than 500A and less than 4000A.
8. The method according to claim 1, characterized in that between said S2 and S3, and between said S3S 4, the steps of: and removing the wafer boat carrying the wafers from the process chamber so as to cool the wafers.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310889600.7A CN116895523A (en) | 2023-07-19 | 2023-07-19 | Method for forming polycrystalline silicon layer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310889600.7A CN116895523A (en) | 2023-07-19 | 2023-07-19 | Method for forming polycrystalline silicon layer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN116895523A true CN116895523A (en) | 2023-10-17 |
Family
ID=88313325
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310889600.7A Pending CN116895523A (en) | 2023-07-19 | 2023-07-19 | Method for forming polycrystalline silicon layer |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116895523A (en) |
-
2023
- 2023-07-19 CN CN202310889600.7A patent/CN116895523A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP0391562B1 (en) | Semiconductor devices incorporating a tungsten contact and fabrication thereof | |
| US9048300B2 (en) | Strained-induced mobility enhancement nano-device structure and integrated process architecture for CMOS technologies | |
| US20060156970A1 (en) | Methods for in-situ cleaning of semiconductor substrates and methods of semiconductor device fabrication employing the same | |
| WO2014064873A1 (en) | Semiconductor device manufacturing method | |
| CN113437023A (en) | Semiconductor device and method for manufacturing the same | |
| JP4016371B2 (en) | Manufacturing method of silicon epitaxial wafer | |
| KR20000006001A (en) | Semiconductors having defect denuded zones | |
| US8710626B2 (en) | Semiconductor device having trapezoidal shaped trenches | |
| JP4753075B2 (en) | Manufacturing method of silicon epitaxial wafer | |
| US20040164364A1 (en) | Semiconductor device and its manufacturing method | |
| CN116895523A (en) | Method for forming polycrystalline silicon layer | |
| CN113192839B (en) | Method for manufacturing semiconductor device | |
| CN112186041B (en) | SGT device for improving wafer warping and manufacturing method thereof | |
| US20130203229A1 (en) | Method of reducing surface doping concentration of doped diffusion region, method of manufacturing super junction using the same and method of manufacturing power transistor device | |
| TW201926572A (en) | Method for manufacturing semiconductor structure | |
| JP4743611B2 (en) | Manufacturing method of silicon epitaxial wafer | |
| CN114267730A (en) | Manufacturing method and structure of Trench MOS device | |
| JP2006190896A (en) | Epitaxial silicon wafer and its manufacturing method, and semiconductor device and its manufacturing method | |
| CN113205994A (en) | Method for forming metal silicide layer | |
| CN117747422B (en) | Low-stress deep trench polycrystalline gate and preparation method thereof | |
| CN113628959A (en) | Groove filling method applied to power device | |
| US5635752A (en) | Semiconductor device having source and drain regions which include horizontally extending secondary defect layers | |
| CN113284798A (en) | Method for manufacturing semiconductor device | |
| CN112635395A (en) | Preparation method of semiconductor device and semiconductor device | |
| KR100452311B1 (en) | Interlayer dielectric of semiconductor device and fabricating method thereof to stably use hto layer and bpsg layer without preventing silicide layer from being influenced by heat |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |