JP4743611B2 - Manufacturing method of silicon epitaxial wafer - Google Patents

Description

  The present invention relates to a method for manufacturing a silicon epitaxial wafer and an epitaxial wafer manufactured thereby. More particularly, the present invention relates to an epitaxial wafer manufacturing method in which a buried layer is formed by vapor-phase growth of a silicon epitaxial layer after ion implantation into the silicon epitaxial layer, and an epitaxial wafer manufactured thereby.

  In a silicon epitaxial wafer obtained by vapor phase epitaxial growth of a silicon single crystal thin film on a silicon single crystal substrate (hereinafter also simply referred to as “epitaxial wafer”), the silicon single crystal thin film (hereinafter referred to as “silicon epitaxial layer” or simply “epitaxial”). A technique for forming an ion-implanted layer of an impurity element by an ion implantation method and forming another epitaxial layer thereon as a buried layer is disclosed in, for example, Japanese Patent Laid-Open No. 1-105557. Already known. In this publication, as an example, a process of forming a CMOS circuit on an epitaxial wafer is disclosed.

  When an element such as a vertical MOSFET or a vertical bipolar transistor is formed on an epitaxial wafer, an impurity doped region that is long in the depth direction (hereinafter referred to as “vertical doped region” or “vertical doped region” in this specification). May have to be formed. For example, to an element isolation region for isolating elements from other regions (in the above publication, the element isolation regions 3 and 4 in FIG. 1 of the publication) or to a high-concentration impurity diffusion layer embedded in a wafer. The impurity doped region (in the above publication, drain regions 6 and 6a in FIG. 1 of the publication) corresponds to this “longitudinal addition region”.

  For example, when the epitaxial layer is formed as a single relatively thick layer, direct ion implantation may make it difficult to form a longitudinally added region that penetrates the epitaxial layer. In this case, an ion-implanted layer is formed in advance on the substrate surface, another ion-implanted layer is formed on the layer surface after the growth of the epitaxial layer, and the impurity-added regions based on both ion implantations are diffused into each other by subsequent diffusion heat treatment. To connect and integrate. However, this method also has a drawback that if the diffusion distance in the vertical direction is too long, a large number of diffusion regions in the horizontal direction are required, which causes inconvenience in reducing the element size. Therefore, in the above publication, a relatively thin epitaxial layer is grown a plurality of times instead of a single relatively thick epitaxial layer, and impurities are added to a required portion for each epitaxial layer forming step. A technique is disclosed in which an impurity-added portion is overlapped from the final epitaxial layer to a required depth by performing a diffusion heat treatment. Since an ion implantation layer is formed for each comparatively thin epitaxial layer, the longitudinal diffusion distance can be shortened. As a result, there is an advantage that the lateral diffusion is suppressed and the heat treatment time can be shortened.

  By the way, in the technique disclosed in the above publication, an oxide film formed on the epitaxial layer is used as a mask in order to selectively implant impurity ions into a specific region of the epitaxial layer (hereinafter referred to as “ion implantation”). "Oxide film for masks"). Since the oxide film for the ion implantation mask is formed by thermally oxidizing the surface of the epitaxial layer, when forming an ion implantation layer in each of the plurality of epitaxial layers, the heat for forming the oxide film is equal to the number of epitaxial layers. History is added (first heat history).

  In addition, crystal damage (defects) is caused by implanting ions with high energy in the ion implantation layer, and thus heat treatment for recovering the crystal damage after ion implantation (hereinafter referred to as “crystal recovery heat treatment”) is also necessary. The heat history associated with the heat treatment is also added by the number of times of ion implantation (second heat history). Further, as shown in FIG. 12A, ions are directly implanted into a pattern opening formed by etching away the oxide film for ion implantation mask, and further, crystal recovery heat treatment (generally in an inert atmosphere such as a nitrogen atmosphere). Is carried out), the surface of the region where the ion implantation is performed tends to be rough. Therefore, normally, as shown in FIG. 5B, a process of forming a thin oxide film for preventing surface roughness on the surface of the epitaxial layer exposed by etching is performed prior to the ion implantation process (so-called “before implantation”). Oxidation process "). Since this oxide film is also formed by thermal oxidation of the epitaxial layer, the thermal history associated therewith is further added by the number of times of ion implantation (third thermal history). Furthermore, when another epitaxial layer is vapor-grown on the ion-implanted layer to form a buried layer, the epitaxial wafer is heated to a high temperature, so the thermal history associated with the vapor-phase growth is added by the number of epitaxial layers. (Fourth heat history).

  Therefore, in the technique described in the above publication, such four kinds of thermal histories are repeatedly applied to the formed ion implantation layer every cycle of formation of each epitaxial layer and ion implantation. The longitudinally added region formed in this manner has a problem that the lateral diffusion is not necessarily suppressed. For example, as shown in FIG. 6A, when the ion implantation layers 101 and 102 are formed between the plurality of epitaxial layers 103a to 103c, the epitaxial layers 103a to 103c and the ion implantation layers 101 and 102 are formed. Since the thermal history has already been added many times, the diffusion regions 101a and 102a are considerably expanded. Then, as shown in FIG. 5B, when diffusion treatment is further performed to form the longitudinal addition region 105 in which the ion implantation layer is connected in the longitudinal direction, diffusion in the lateral direction further proceeds 105a and 105b. It becomes. In particular, the lower the ion implantation layer 101, the more heat history is repeatedly applied each time the epitaxial layer and the ion implantation layer are formed, so that the lateral spread becomes worse than the upper layer side.

  More specifically, as shown in FIG. 6C, the ion implantation layer 101 formed between the layers of the epitaxial layer 103 becomes non-uniform with a larger spread as it is positioned on the lower layer side. The structure diffuses in the vertical direction and is already connected to some extent (particularly, the ion implantation layer on the lower layer side). As a result, as shown in FIG. 6D, the longitudinal addition region 105 obtained by the subsequent diffusion heat treatment can be obtained only in a non-uniform size that becomes thicker at the lower side. When forming ion implantation layers having different conductivity types (for example, n-type and p-type) in the same epitaxial layer, cycles of forming an oxide film for ion implantation mask, pre-implantation oxidation treatment, and crystal recovery heat treatment are performed for each cycle. The above problem becomes more serious because it is necessary to repeat for each ion implantation layer pattern of the conductive type.

  On the other hand, in the technique disclosed in Japanese Patent Laid-Open No. 1-105557, the cycle of forming an oxide film for an ion implantation mask, pre-implantation oxidation treatment, and crystal recovery heat treatment is repeated many times. Low productivity is also a major problem. In this case, in addition to the above steps, the following derivation steps are inevitably included, so it goes without saying that the problem of low productivity is actually greater.

(1) When forming an oxide film for an ion implantation mask, pre-oxidation cleaning is required in order to remove contaminants and form a defect-free pattern.

(2) When forming an ion implantation mask, steps or recesses are three-dimensionally formed as marks (so-called alignment marks) for pattern alignment. Such a three-dimensional mark (hereinafter referred to as “three-dimensional mark”) is re-formed each time one epitaxial layer is formed.

(3) A back oxide film made of silicon dioxide is often formed on a substrate used for manufacturing a silicon epitaxial wafer by a CVD method or the like for the purpose of preventing autodoping from the main back side of the substrate. On the other hand, on the main surface of the substrate, formation and removal of the oxide film for ion implantation mask with respect to the epitaxial layer are repeated many times. In general, the removal of the oxide film is performed by so-called wet etching in which the oxide film is chemically dissolved by immersing the substrate in an etching solution such as hydrofluoric acid. Since the back oxide film is also removed, a resist film for protecting it from the etching solution is formed on the back oxide film. Since the resist film does not endure the heat treatment temperature at the time of forming the oxide film for the ion implantation mask, it is removed immediately after completion of the wet etching, and must be formed every time the oxide film for the ion implantation mask is removed. .

(4) Photolithography for forming a pattern on the oxide film is necessary. As is well known, photolithography includes as many as three steps: exposure of a photoresist, development, and wet etching.

  In addition, there is an autodoping problem to be solved in the vapor phase growth of the epitaxial layer forming the buried layer. That is, after forming an ion implantation layer, when an epitaxial layer is further grown in a vapor phase to be used as a buried layer, lateral autodoping (lateral autodoping) occurs from the ion implantation layer. There is a case. When such lateral auto-doping occurs, the dopant element liberated from the ion implantation layer into the gas phase is re-incorporated into the growing epitaxial layer around the ion implantation layer, resulting in a region where no ion implantation is performed. In some cases, the target device performance may not be obtained in the vicinity of the epitaxial layer interface due to doping. In particular, when an n-type buried layer is formed by ion implantation of, for example, phosphorus (P), phosphorus is an element that is particularly susceptible to autodoping, so care must be taken.

  Further, for example, consider a case where a phosphorus implantation layer which is an n-type ion implantation layer is formed first, and then a p-type ion implantation layer is formed by boron (B) implantation. When the aforementioned pre-implantation oxidation treatment is performed when forming the boron implantation layer, a thin oxide film is also formed on the surface of the previously formed phosphorous implantation layer. The main component of the oxide film is silicon dioxide. However, since phosphorus has a large segregation coefficient with respect to silicon dioxide, phosphorus tends to be unevenly distributed on the main surface side where the oxide film is formed in the phosphorus injection layer. When the epitaxial layer is grown in a vapor phase after removing the oxide film in this state, the lateral auto-doping from the phosphorus implantation layer becomes more severe due to the influence of phosphorus unevenly distributed on the main surface.

  A first object of the present invention is to provide an epitaxial wafer in which a plurality of epitaxial layers are laminated through a buried layer, and to produce a silicon epitaxial wafer with very low lateral diffusion of the formed ion implantation layer. And a silicon epitaxial wafer that can be manufactured thereby. In addition, the second problem is that when the epitaxial wafer is manufactured by repeating the ion implantation and the formation of the epitaxial layer, the number of formations of the three-dimensional mark for pattern alignment can be reduced, and the manufacturing process is simplified. An object of the present invention is to provide a method for producing a silicon epitaxial wafer that contributes to the formation of a silicon epitaxial wafer and a silicon epitaxial wafer obtained thereby. Furthermore, the third problem is to provide a method for manufacturing a silicon epitaxial wafer that can effectively suppress lateral autodoping from the ion-implanted layer, and a silicon epitaxial wafer obtained thereby.

Means for Solving the Problems and Effects of the Invention

(First aspect)
This is to solve the first problem. This is because an impurity element is ion-implanted into the first epitaxial layer to form an ion-implanted layer, and the second epitaxial layer is vapor-phase grown and stacked thereon to form the ion-implanted layer and the first epitaxial layer. In the method for manufacturing a silicon epitaxial wafer embedded between two epitaxial layers and forming an embedded layer,
A mask forming step of directly forming an ion implantation mask made of a photoresist film on the surface of the first epitaxial layer;
An ion implantation step of performing ion implantation on the first epitaxial layer on which the ion implantation mask is formed;
A hydrogen heat treatment step that is performed prior to vapor phase growth of the second epitaxial layer after the ion implantation step is completed;
A vapor phase growth step of vapor-phase-growing the second epitaxial layer after the hydrogen heat treatment step is completed.

  There are two important points in the manufacturing method of the first aspect. One is that a photoresist film is used instead of an oxide film as a mask for ion implantation, that is, from the photoresist film without positively forming an oxide film on the first epitaxial layer to be ion-implanted. The ion implantation mask is formed directly on the first epitaxial layer. However, a natural oxide film formed on the surface of the epitaxial layer near room temperature is allowed. The other is that heat treatment for crystallinity recovery after ion implantation and carrier activation is performed in a hydrogen atmosphere. Forming an ion implantation mask made of a photoresist film directly on the first epitaxial layer means that not only the formation of an oxide film for the ion implantation mask but also no pre-implantation oxidation treatment is performed. The heat treatment for crystallinity recovery and carrier activation after the implantation process (hereinafter sometimes simply referred to as “crystallinity recovery and activation heat treatment”) does not actively form an oxide film on the surface of the ion implantation layer. Done in state.

  If the crystallinity recovery and activation heat treatment is performed in a nitrogen atmosphere as in the past without forming an oxide film on the surface of the ion implantation layer, rough unevenness generated on the surface of the ion implantation layer due to the heat treatment becomes large. However, as a result of intensive studies by the present inventors, it has been found that the surface roughness can be extremely effectively suppressed if this crystallinity recovery and activation heat treatment is performed in a hydrogen atmosphere. As a result, in the method of manufacturing an epitaxial wafer having an embedded layer, it is possible to omit the pre-implantation oxidation process, and hence an ion implantation process using only the photoresist film as a mask. Then, as a result of the necessity of an active oxide film forming process on the epitaxial layer including the pre-implantation oxidation, as described below, the conventional oxide film generated when the oxide film is used as a mask during ion implantation is used. All the problems of the manufacturing method can be solved.

[1] Since an oxide film is not used as an ion implantation mask, the first thermal history related to the formation of an oxide film for an ion implantation mask and the pre-implantation oxidation among the three thermal histories inevitably generated in the conventional method. The third heat history related to the processing can be avoided. As a result, it is possible to extremely effectively suppress the lateral diffusion of the buried layer and, consequently, the impurity-added region formed based thereon.
[2] Two oxide film formation processing steps of mask oxide film formation and pre-implantation oxidation are omitted.
[3] Along with the omission of the mask oxide film forming step, the pre-oxidation cleaning step and the oxide film etching step can be omitted. Also, the formation of a resist film for protecting the backside oxide film can be omitted or the number of times can be reduced.

  Thereby, it is possible to dramatically simplify the manufacturing process of an epitaxial wafer having a buried layer, particularly an epitaxial wafer in which a plurality of epitaxial layers and an ion implantation layer are laminated.

The manufacturing method of the present invention described above can be applied in the form including the following steps even when different ion implantation layer patterns of different conductivity types are formed on the same epitaxial layer:
A first mask forming step of directly forming a first ion implantation mask for ion implantation of a first impurity into a first region of the surface of the first epitaxial layer on the surface of the first epitaxial layer by a photoresist film;
A first ion implantation step of forming a first ion implantation layer in the first region by implanting a first impurity into the first epitaxial layer on which the first ion implantation mask is formed;
A second ion implantation mask for ion-implanting a second impurity different from the first impurity in a second region different from the first region on the surface of the first epitaxial layer is formed by a photoresist film. Forming a second mask directly on the surface of one epitaxial layer;
A second ion implantation step of forming a second ion implantation layer at a position corresponding to the second region by ion implantation of a second impurity into the first epitaxial layer on which the second ion implantation mask is formed. ;
A hydrogen heat treatment step performed after the second ion implantation step is completed and before the second epitaxial layer is vapor-grown on the first epitaxial layer on which the first and second ion implantation layers are formed;
After the hydrogen heat treatment step is completed, the second epitaxial layer is vapor-grown to form the first ion-implanted layer and the second ion-implanted layer as the first buried layer and the second buried layer, respectively. Growth process.

  When the first ion implantation layer and the second ion implantation layer are formed in the same epitaxial layer using the oxide film as a mask as in the prior art, oxide film formation → photoresist corresponding to both types of ion implantation layers The process cycle of coating → pattern exposure / development → etching (pattern formation) → photoresist removal → ion implantation → oxide film removal must be repeated twice. As a result, the heat treatment is repeated twice with the formation of the oxide film, and the diffusion of the implanted impurities is increased accordingly (in particular, the ion implantation layer of the type formed earlier). In addition, since etching for pattern formation or oxide film removal is performed four times, each time, for convenience, the photoresist coating (back surface coating) for protecting the back surface oxide film must be performed four times correspondingly. .

  However, in the method of the present invention, not only the thermal history associated with oxide film formation is added, but also etching for pattern formation or oxide film removal, and further no back coating is required, and the entire process is applied with photoresist → pattern exposure.・ Development → Ion implantation → Removal of photoresist is dramatically shortened, and further, crystallinity recovery and activation heat treatment performed in a hydrogen atmosphere is performed on two types of ion implantation layers at the same time. Becomes even more prominent.

  Further, the manufacturing method of the present invention can be applied to the manufacture of an epitaxial wafer in which a plurality of epitaxial layers and buried layers are stacked as follows. That is, the processing cycle from the mask formation step to the vapor phase growth step through the ion implantation step and the hydrogen heat treatment step is repeated once or a plurality of times by using the formed second epitaxial layer as a new first epitaxial layer. As a result, a plurality of epitaxial layers are stacked and formed with the buried layer sandwiched between the layers.

  According to the above method, the thermal history applied to each epitaxial layer is limited to crystallinity recovery and activation heat treatment performed in a hydrogen atmosphere after ion implantation and heating during vapor phase growth. When the epitaxial layer is formed, the thermal history during the formation of the subsequent epitaxial layer or buried layer is less likely to be accumulated in the underlying buried layer. As a result, the spread of the buried layer due to thermal diffusion can be reduced between the lower layer and the upper layer, and the buried layer located on the lower layer side can be effectively suppressed from becoming uneven in the lateral direction. Can do.

  For example, when forming the above-described longitudinally added region, it is effective to form a plurality of buried layers into which the same impurity is ion-implanted so that they are all separated from each other in the stacking direction of the silicon epitaxial layer. . In this case, by performing a diffusion heat treatment, the plurality of buried layers can be diffused and integrated in the stacking direction of the epitaxial layer (hereinafter also referred to as the vertical direction) to form the above-described vertical addition region.

  The epitaxial wafer of the present invention obtained by the above method is a silicon epitaxial wafer for manufacturing an element having a structure in which a plurality of impurity-added regions are interconnected in the stacking direction of the epitaxial layer, and has the same conductivity type. In a silicon epitaxial wafer having a structure in which a plurality of epitaxial layers in which the buried layers are formed in the same region are stacked, the plurality of buried layers are all separated from each other in the stacking direction of the epitaxial layers. And That is, by adopting the method of the present invention in which the thermal history is less likely to accumulate, as a result of suppressing the spreading of the buried layers arranged in the vertical direction, all the buried layers are not connected in the vertical arrangement direction but separated from each other. A structure that maintains the specified state is realized. In such a structure, as a result, spreading of the buried layer in the lateral direction is appropriately suppressed, so that the longitudinal addition region obtained by diffusing and integrating these buried layers by diffusion heat treatment is A uniform product with a small difference in lateral spread (or size) between the lower layer side and the upper layer side can be obtained. As a result, it is extremely effective in reducing the size of a semiconductor element formed using such a longitudinally added region.

(Second aspect)
This is to solve the second problem. This is because an impurity element is ion-implanted into the first epitaxial layer to form an ion-implanted layer, and the second epitaxial layer is vapor-phase grown and stacked thereon to form the ion-implanted layer and the first epitaxial layer. In the method of manufacturing a silicon epitaxial wafer in which a plurality of epitaxial layers in which embedded layers are formed are stacked, by repeating the step of embedding between two epitaxial layers and forming a buried layer,
Form a positioning solid mark consisting of a recess or a step on the surface of the first epitaxial layer,
A mask pattern is transferred to the first epitaxial layer while positioning using a positioning solid mark to form an ion implantation mask for forming an ion implantation layer,
When the second epitaxial layer is formed on the first epitaxial layer, a transfer solid mark is generated on the surface of the second epitaxial layer in such a way that the shape of the positioning solid mark is raised, and the transfer solid mark is next ion-implanted. It is used as a positioning solid mark for forming a layer.

  In the above method, since the solid mark is transferred when forming the second epitaxial layer which is the upper layer based on the solid mark for positioning the first epitaxial layer which is the lower layer side, this is used as the three-dimensional mark for positioning the second epitaxial layer. To do. That is, since a new solid mark is not formed every time an epitaxial layer is formed, the number of formations of the solid mark can be greatly reduced, which is efficient. More specifically, the transfer source positioning solid mark that is not derived from the positioning epitaxial mark of the lower epitaxial layer and serves as a transfer source for forming the transfer solid mark on the subsequent layers is formed as an embedded layer. A method of forming only a part of the epitaxial layers including the lowermost layer is possible. That is, since the transfer source positioning solid mark is not formed on the epitaxial layers other than a part of the layers including the lowermost layer, the number of formation of the solid mark can be greatly reduced, which is efficient.

  The three-dimensional mark for positioning the transfer source can be formed by employing a wet etching method or a dry etching method such as ion etching.

  The structure of the silicon epitaxial wafer obtained by the above method is as follows from the viewpoint of the formation layer of the transfer source positioning solid mark. That is, in a silicon epitaxial wafer in which a plurality of epitaxial layers with embedded layers formed are stacked, a positioning solid mark consisting of a recess or a step, not derived from the positioning solid mark of the underlying epitaxial layer, and The transfer source positioning solid mark, which is the transfer source for forming the transfer solid mark on the subsequent layers, is formed only on a part of the epitaxial layer including the bottom layer among the epitaxial layers on which the buried layer is formed. The

  Further, from the viewpoint of the number of appearance of the transfer solid mark on the uppermost epitaxial layer, the structure of the silicon epitaxial wafer is as follows. In other words, in a silicon epitaxial wafer in which an epitaxial layer having a buried layer is stacked, a positioning solid mark consisting of a recess or a step is formed on the epitaxial layer having the buried layer. The number is less than the number of layers.

  Since any of these epitaxial wafers does not require the formation of the positioning solid mark by the wet etching method or the dry etching method in the epitaxial layer in which the transfer source positioning solid mark is not formed, an advantage that it can be manufactured at high efficiency and at low cost. There is.

  If the formation / removal of an oxide film is repeated on the surface of the same epitaxial layer for the purpose of forming an ion implantation mask or pre-implantation oxidation prior to ion implantation, the epitaxial layer surface layer portion on which the three-dimensional mark is formed is oxidized. The shape is easily lost due to conversion to and removal from the film. In some cases, when a new epitaxial layer is stacked, the original shape of the transferred solid mark may be damaged. In this case, the shape collapse of the three-dimensional mark can be effectively suppressed by combining the manufacturing method of the first aspect in which an ion implantation mask made of a photoresist film is directly formed on the surface of the epitaxial layer. In other words, by forming the ion implantation mask as a photoresist film instead of an oxide film, it is not necessary to repeat the formation of the oxide film and its etching removal, and the shape of the positioning solid mark formed on the epitaxial layer is almost destroyed. Disappear. As a result, the lower positioning solid mark transferred when a new epitaxial layer is laminated on the upper side can be used as the positioning solid mark for the upper epitaxial layer.

  Here, in the first aspect, the oxide film etching process is practically not included with respect to the pattern formation of the ion implantation layer, and there is no room for wet etching. Therefore, if the transfer source positioning solid mark is formed by dry etching such as ion etching, the wet etching process including the formation of the positioning solid mark can be abolished. It is not necessary to perform the resist film forming process at all. Further, since no acidic etching waste liquid is generated, the waste liquid processing cost can be reduced.

  By the way, in the following description, the Miller index is used to display the crystal plane as (hkl) and the crystal axis as [hkl]. In the Miller index display method, [1] and [ As in [2], a negative sign representing a negative index is generally added above the index.

However, in this specification, the above [1] and [2] are represented as [1] ′ and [2] ′ below for convenience.
(H-kl) ... [1] '
[H-kl] ... [2] '

  When the positioning solid mark is transferred onto the second epitaxial layer, the outer shape of the transferred solid mark may be deformed due to the vapor phase growth mechanism. Such deformation of the transfer solid mark increases as the thickness of the second epitaxial layer to be formed and the number of times of transfer (that is, the number of stacked epitaxial layers) increase. When the deformation of the transfer solid mark is increased, the accuracy of mask alignment performed for forming the ion implantation layer is reduced.

  As a result of intensive studies by the present inventors, when an epitaxial layer is formed on a silicon single crystal substrate having a plane orientation (100), the positioning solid mark is in the [011] direction or the [0-1-1] direction. It has been found that it is preferable to form it so that it has a straight portion that faces in a direction within 45 °. If the transfer source solid mark includes a straight line portion that satisfies the above conditions, the straight line portion with a clear boundary is unlikely to be deformed when the transfer solid mark is formed by vapor-phase growth of the second epitaxial layer. As this is taken over. Therefore, when pattern formation is performed using the transfer solid mark as a new solid mark, the accuracy of alignment for forming the ion implantation layer can be increased by using the inherited straight line portion for pattern positioning. . In addition, even when a considerable number of epitaxial layers are stacked on the epitaxial layer on which the transfer source positioning solid mark is formed, the shape of the transferred solid mark is not easily lost, and it is necessary to form the transfer source positioning solid mark. Since the number of epitaxial layers to be formed can be reduced, it is more effective in reducing the number of processes.

  In this case, in the obtained epitaxial wafer, an epitaxial layer is formed on a silicon single crystal substrate having a plane orientation (100), and a positioning solid mark including a recess or a step is formed on the uppermost epitaxial layer. In addition, the positioning solid mark has a linear portion that faces a direction within 45 ° with respect to the [011] direction or the [0-1-1] direction. By forming the positioning solid mark including such a straight line portion, it becomes difficult to cause the deformation of the transferred solid mark, and the number of formations of the transfer original positioning solid mark can be reduced. There is an advantage that can be manufactured.

  In addition, if the direction of the straight line portion of the positioning solid mark is out of the above angle range, the degree of deformation of the corresponding straight line portion in the transfer solid mark formed using this becomes large and the boundary becomes unclear. In some cases, accurate alignment may be hindered.

(Third embodiment)
This is to solve the third problem. This is because phosphorus is ion-implanted into the first epitaxial layer and a plurality of phosphorus-implanted layers are formed so as to be aligned in the width direction, and a second epitaxial layer is vapor-phase grown and stacked thereon to form a phosphorus-implanted layer. In the method of manufacturing a silicon epitaxial wafer embedded between the first epitaxial layer and the second epitaxial layer and forming a phosphorus embedded layer,
An ion implantation step of implanting phosphorus into the first epitaxial layer;
A heat treatment step of performing heat treatment at 950 ° C. or more and less than 1100 ° C. under atmospheric pressure before vapor-phase growth of the second epitaxial layer after the ion implantation step is completed;
After the heat treatment step is completed, a sealing growth step of introducing a source gas in a reduced pressure atmosphere and vapor-growing a sealing epitaxial layer at a pressure of 5 to 60 torr ;
And a main growth step of vapor-phase-growing a second epitaxial layer on the sealing epitaxial layer. The silicon source gas is, for example, dichlorosilane (SiH ₂ Cl ₂ ), trichlorosilane (SiHCl ₃ ), or silicon tetrachloride (SiCl ₄ ) diluted with hydrogen.

  According to the above method, after phosphorus is ion-implanted to form a phosphorus-implanted layer, heat treatment is performed at 950 ° C. or more and less than 1100 ° C. at normal pressure, and then silicon source gas is introduced in a reduced-pressure atmosphere. The auto-doping sealing epitaxial layer is vapor-phase grown, and then the second epitaxial layer is grown on the sealing epitaxial layer, thereby performing lateral auto-doping of phosphorus extremely effectively. Can be suppressed.

Conventionally, it has been thought that the autodoping phenomenon increases as the heat treatment temperature increases. However, as a result of the present inventors investigating the auto-doping phenomenon of phosphorus under normal pressure in the heat treatment temperature range of 850 to 1200 ° C., the amount of auto-dope becomes smaller in the temperature range of 950 ° C. or higher and lower than 1100 ° C. It has been found that it becomes minimum in the vicinity of ° C.
In a temperature range of 950 ° C. or higher and lower than 1100 ° C. under normal pressure, phosphorus is diffused out of the epitaxial layer to the vapor phase at a certain size, while the amount taken back into the epitaxial layer from the vapor phase is reduced. It is considered a thing. Therefore, by adopting a temperature range of 950 ° C. or higher and lower than 1100 ° C. as the heat treatment condition under normal pressure, the outward diffusion of phosphorus is promoted, while the amount taken into the crystal again is suppressed. The phosphorus concentration in the surface layer portion is lowered, and an advantageous state is formed in preventing the autodoping of phosphorus. In addition, by performing vapor phase growth of the sealing epitaxial layer while introducing a silicon source gas in a reduced pressure atmosphere, it is also effective to auto-dope phosphorous generated when sealing the surface of the phosphorus implantation layer. Can be suppressed. As a result, the lateral autodoping of phosphorus is significantly suppressed as a whole process. Even when the heat treatment atmosphere is reduced in pressure or when a normal pressure atmosphere is employed, if the temperature is outside the range of 950 ° C. or higher and lower than 1100 ° C., the effect of preventing the lateral autodoping of phosphorus cannot be sufficiently achieved. In addition, when the vapor phase growth of the sealing epitaxial layer is performed under normal pressure or a pressurized atmosphere, the effect of preventing the lateral autodoping of phosphorus cannot be achieved sufficiently. The reason for using dichlorosilane, trichlorosilane, or silicon tetrachloride as the silicon source gas for the sealing epitaxial layer is that the growth rate of the film is so high that out-diffusion of phosphorus is most likely to occur. In some cases, the growth time can be shortened, which is more advantageous in preventing lateral autodoping and is easy to handle. In this growth step, if dichlorosilane, trichlorosilane, or silicon tetrachloride is used as a source gas, the growth time until a second epitaxial layer having a film thickness required in this growth step can be shortened, and When shifting from the sealing epitaxial process to the main growth process, it is not necessary to switch the source gas species, which is advantageous for shortening the process and simplifying the manufacturing equipment.

  As a result of preventing the lateral auto-doping of phosphorus by the above method, a silicon epitaxial wafer having a structure in which a plurality of p-type epitaxial layers are stacked and a phosphorus implantation layer is embedded at the interface position between the epitaxial layers. In that case, the following structure can be achieved. That is, when the net carrier concentration profile in the epitaxial layer is measured across the interface between the epitaxial layers in the film thickness direction of the epitaxial layer at a position adjacent to the phosphorus implanted layer and not across the phosphorus implanted layer, Assuming that the lowest value of the net carrier concentration at the interface of the epitaxial layer is BH and the average net carrier concentration in the region where the carrier concentration is stable in the epitaxial layer is AH, (AH−BH) / AH is 0.5 or less. By setting (AH−BH) / AH to 0.5 or less at a position adjacent to the phosphorus implantation layer, the net carrier concentration distribution in the lateral direction becomes more uniform in the vicinity of the epitaxial layer interface, and thus stable and good characteristics. Can be obtained. Here, the net carrier concentration is the difference between the concentration of the majority carrier and the concentration of the minority carrier, and can be obtained, for example, by converting the spreading resistance value into the carrier concentration.

(Fourth aspect)
This is to solve the third problem. This relates to the production of an epitaxial wafer in which a boron buried layer and a phosphorus buried layer are simultaneously formed on the same substrate,
A boron implantation step of forming a boron implantation layer at a position corresponding to the first region by ion-implanting boron into the first region of the surface of the first epitaxial layer;
A phosphorus implantation step of forming a phosphorous implantation layer at a position corresponding to the second region by ion implantation of phosphorous into a second region different from the first region on the surface of the first epitaxial layer;
Prior to the phosphorus implantation step, a pre-implantation oxidation step for oxidizing the surface of the first epitaxial layer;
A second epitaxial layer is vapor-phase grown on the first epitaxial layer on which the boron implantation layer and the phosphorus implantation layer are formed, so that the first ion implantation layer and the second ion implantation layer are converted into the first buried layer and the first implantation layer, respectively. And a vapor phase growth step for forming the second buried layer.

  In general production of a silicon epitaxial wafer, an oxidation process before implantation prior to ion implantation and an oxide film forming process for an ion implantation mask for forming an oxide film for mask formation are often involved. In this case, the oxide film is mainly formed of silicon dioxide. For example, when an oxide film is formed on the surfaces of the boron implantation layer and the phosphorus implantation layer, the segregation coefficient of phosphorus and boron with respect to silicon dioxide is different. Boron has a different behavior in that it is easily taken into the oxide film, whereas phosphorus tends to collect near the interface with the oxide film. In this case, a particular problem is the order of formation of the phosphorus implantation layer and formation of the oxide film on the epitaxial layer on which the phosphorus implantation layer is formed. That is, after the formation of the phosphorus implantation layer, when a pre-implantation oxidation step for forming another ion implantation layer is performed on the surface of the first epitaxial layer on which the phosphorus implantation layer is formed, Since phosphorus collects and concentrates in the surface layer portion of the phosphorus implantation layer, there is a problem that lateral autodoping of phosphorus is likely to occur during vapor phase growth of the second epitaxial layer formed on the first epitaxial layer. However, in the method of the present invention, since the pre-implantation oxidation step is always performed prior to the phosphorus implantation step, phosphorus is concentrated in the surface layer portion of the phosphorus implantation layer before the growth of the second epitaxial layer. Is less likely to occur, and the lateral autodoping of phosphorus is effectively suppressed.

  For example, when a phosphorus implantation layer is first formed in the same epitaxial layer and then a boron implantation layer is formed, the phosphorous implantation layer previously formed when performing pre-implantation oxidation for forming the boron implantation layer An oxide film is also formed on the surface. Therefore, if the phosphorus implantation process is performed after the boron implantation process, the pre-implantation oxidation for the boron implantation does not precede the phosphorus implantation, which is effective in avoiding the lateral autodoping of phosphorus. In addition, performing the pre-implantation oxidation step prior to the boron implantation step is effective in preventing surface roughness of the epitaxial layer that is likely to occur during boron implantation.

  In addition, after forming the ion implantation layer, it is common to perform a heat treatment for recovering crystal damage generated during the ion implantation, but without performing such a heat treatment independently after the phosphorus implantation step, For example, if a heat treatment capable of recovering crystal damage generated during ion implantation is performed in the pre-heat treatment for vapor phase growth of the second epitaxial layer, it is more advantageous for preventing lateral autodoping of phosphorus and filling. Extra spreading due to thermal diffusion of the buried layer can be prevented. Crystal damage can also be recovered by a thermal history applied during vapor phase growth of the second epitaxial layer, or by a diffusion heat treatment performed after the formation of the second epitaxial layer (for example, for forming the longitudinally added region described above). Can do.

(Fifth aspect)
This is also for solving the third problem, and can be applied in combination with any of the first to fourth aspects (or the sixth or seventh aspect described later). That is, in a method of manufacturing a silicon epitaxial wafer having a structure in which a plurality of epitaxial layers in which ion implantation layers of the same conductivity type are embedded in the same region are stacked, the elements to be ion implanted are boron and phosphorus, and the same epitaxial A feature is that a dose ratio between boron and phosphorus implanted into the layer is inversely proportional to a ratio between boron and phosphorus implantation pattern areas. The phosphorus implantation pattern area is preferably 3 to 10 times the boron implantation pattern area. The phosphorus dose is preferably 1/3 to 1/10 of the boron dose.

  According to the above-described silicon epitaxial wafer manufacturing method, a silicon epitaxial wafer for manufacturing an element having a structure in which a plurality of impurity-added regions are connected to each other in the stacking direction of the epitaxial layer, the ion implantation layer having the same conductivity type In a silicon epitaxial wafer having a structure in which a plurality of epitaxial layers embedded in the same tilt region are stacked, the ion-implanted elements are boron and phosphorus, and boron and phosphorus implanted in the same epitaxial layer. A device characterized in that the dose ratio is inversely proportional to the ratio of boron and phosphorus implantation pattern area can be manufactured.

  For example, when boron and phosphorus having the same implantation pattern area and the same dose amount are implanted into the same epitaxial layer, when the epitaxial layer that embeds these implantation layers is vapor-phase grown, phosphorus is three times larger than boron. 10 times larger auto dope is generated. This difference in the amount of autodoping makes the lateral autodoping due to phosphorus remarkable in the vicinity of the epitaxial layer interface.

  If the autodoping amounts of phosphorus and boron can be made equal, the two cancel each other, so that lateral autodoping from the ion implantation layer can be effectively suppressed. Therefore, the amount of auto-doping of phosphorus and boron is investigated in advance, and the area and dose of the implantation pattern are determined so that the amounts of auto-doping from both are the same.

  That is, by utilizing the fact that the amount of autodoping is proportional to the surface impurity temperature of the ion implantation layer, for phosphorus with a large autodoping, the area of the implantation pattern is formed to be 3 to 10 times that of boron and the dose of phosphorus. The amount is reduced to 1/3 to 1/10 of boron. Then, the amount of phosphorous autodoping can be lowered while keeping the total amount of phosphorus implanted constant, so that a uniform additive impurity concentration distribution can be obtained near the epitaxial layer interface.

(Sixth aspect)
This is an invention that is effective in making the concentration distribution of the formed vertical addition region uniform, and can be combined with any of the first to fifth aspects (or the seventh aspect described later). That is, in a method of manufacturing a silicon epitaxial wafer having a structure in which a plurality of epitaxial layers in which ion implantation layers of the same conductivity type are embedded in the same region are stacked, the ion implantation layer located closer to the lower layer is implanted. It is characterized in that the impurity concentration is increased. The silicon epitaxial wafer thus obtained is a silicon epitaxial wafer for manufacturing an element having a structure in which a plurality of impurity-added regions are connected to each other in the stacking direction of the epitaxial layer, and the same conductivity type ion implantation layer In a silicon epitaxial wafer having a structure in which a plurality of epitaxial layers embedded in the same region are stacked, the ion-implanted layer located on the lower layer side is formed such that the implanted impurity concentration is higher. To do.

  The gist of this aspect is that when forming a structure in which a plurality of epitaxial layers in which an ion implantation layer of the same conductivity type is embedded in the same region is formed for the purpose of forming a longitudinally added region or the like, The layer is formed so that the concentration of the implanted impurity is higher as the layer is located on the lower layer side. Since the lower ion-implanted layer is repeatedly subjected to heat treatment by forming an upper-layer epitaxial layer, ion-implanted layer, or oxide film, the spread due to thermal diffusion increases and the impurity concentration decreases. Therefore, as shown in FIGS. 28A to 28C, the concentration of the implanted impurity is higher in the layer located on the lower layer side of the stacked epitaxial layers 103a through 103c, in other words, the epitaxial layer formed earlier. By forming the ion implantation layers 250 to 252 in this manner, as shown in FIG. 28D, implantation between the plurality of buried layers 250 ′, 251 ′ and 252 ′ arranged in the stacking direction of the epitaxial layers 103a to 103d is performed. The difference in impurity concentration can be reduced. That is, when the ion implantation concentrations of the ion implantation layers 250 to 252 are C1, C2, and C3, C1> C2> C3. In this case, the dose amount of the implanted ions may be increased as the ion implanted layer located on the lower layer side.

  Here, the ion-implanted layers 250 to 251 are formed such that the pattern area is smaller as the layer is located on the lower layer side. That is, when the pattern areas of the ion implantation layers 250 to 252 are S1, S2, and S3, S1 <S2 <S3. As a result, as shown in FIG. 28 (d), the difference in pattern area between the buried layers 250 ', 251' and 252 'can be reduced.

For example, when three buried layers are formed as described above, when the dose amount of ion implantation for forming each layer is D1, D2, and D3,
D1: D2: D3 = (S2 / S1) ² × C2: C2: (S2 / S3) ² × C2
It is effective to set the dose amount so that the difference in the implanted impurity concentration between the buried layers 250 ′, 251 ′ and 252 ′ is reduced. This relationship between the dose amount and the pattern area can also be applied when three buried layers are formed. As a result, a longitudinally added region obtained by subjecting this to a diffusion heat treatment can be obtained in which not only the impurity concentration but also the axial cross-sectional area is more uniform, for example, using the longitudinally added region. It is also possible to improve the integration density of the elements.

(Seventh aspect)
This aspect can be combined with any of the first to sixth aspects, and can be carried out independently regardless of the first to sixth aspects. This relates to a method of manufacturing a silicon epitaxial wafer having a structure in which a plurality of epitaxial layers are stacked with an ion implantation layer of an impurity element interposed therebetween,
A first vapor phase growth step of vapor phase growing the first epitaxial layer;
A first ion implantation step of forming a first ion implantation layer by implanting a first impurity element into a first region of the surface of the first epitaxial layer;
After the first ion implantation step, a second vapor phase growth step of vapor-phase-growing the second epitaxial layer;
By ion-implanting the second impurity element into the second region different from the first region on the surface of the first epitaxial layer on the surface of the second epitaxial layer, the second ion-implanted layer is formed at a position corresponding to the second region. And a second ion implantation step for forming
By repeating these process sets a plurality of times, the first ion implantation layer and the second ion implantation layer and the second ion implantation layer are formed in the same region so that the first ion implantation layer and the second ion implantation layer are formed between the respective epitaxial layers. The two ion implantation layers are formed alternately.

  A specific example is shown in FIG. Here, while the epitaxial layer 103 is stacked, the boron implantation layer 71 as the first ion implantation layer and the phosphorus implantation layer 72 as the second ion implantation layer are alternately formed between the layers of the epitaxial layer 103. As described above, boron and phosphorus have a large difference in behavior with respect to lateral autodoping, and the growth conditions of the epitaxial layer at which the influence is minimized are also different from each other. As described above, when two types of impurities having different lateral auto-doping behaviors are implanted into the same epitaxial layer, the growth condition of the second epitaxial layer when embedding the two impurities is such that if one of the impurities is given priority, the other impurity This causes a dilemma that is disadvantageous from the viewpoint of suppressing autodoping. In addition, even when an intermediate condition for both impurities is adopted, the condition is not optimized for suppressing lateral autodoping. Therefore, if the method as described above is employed, only one of the first ion implantation layer and the second ion implantation layer is formed in each epitaxial layer, so that the lateral direction of the corresponding impurity for each epitaxial layer. The growth conditions that minimize auto-doping can be set freely regardless of the other impurity. As a result, it is possible to effectively suppress the lateral autodoping of the buried layer of each impurity.

  When diffusion heat treatment is performed on the silicon epitaxial wafer obtained as described above, the corresponding ion implantation layers formed in each layer are connected to each other in the stacking direction of the epitaxial layers, and as shown in FIG. A plurality of vertical impurity-added regions (here, the vertical direction, the boron-added region 171 and the vertical phosphorus-added region 172) are formed. In this case, this has the following characteristics. That is, two types of connected impurity-added regions, a first impurity-added region 171 to which a first impurity is added and a second impurity-added region 172 to which a second impurity is added, are formed, both of which are epitaxial layers. 103 is formed in a non-uniform columnar shape in which small-diameter portions 171b and 172b having a minimum axial cross-sectional area and large-diameter portions 171a and 172a having a maximum axial cross-sectional area are alternately arranged. . The first impurity-added region 171 and the second impurity-added region 172 have one large-diameter portion 171a or 172a formed by shifting the formation cycle of the small-diameter portions 171b and 172b and the large-diameter portions 171a and 172a in the stacking direction. The other small diameter portion 172b or 171b is formed in a corresponding positional relationship. As a result, the distance between the axes of the first impurity added region 171 and the second impurity added region 172 can be reduced, and for example, the integration density of elements formed using these impurity added regions 171 and 172 can be improved. .

  In this case, as shown in FIG. 29E, when the first impurity added region 171 and the second impurity added region 172 formed adjacent to each other are viewed in plan, the large diameter portions 171a and 172a partially overlap each other. By forming in a positional relationship, in other words, by allowing the bulging portion due to the large diameter portion of one addition region to enter the inside of the constriction portion due to the small diameter portion of the other addition region, the first impurity The interaxial distance between the addition region 171 and the second impurity addition region 172 can be further reduced, and the above effect is further enhanced. In this case, the first ion implantation layer 71 and the second ion implantation layer 72 partially overlap each other when they are adjacent to each other with the epitaxial layer 103 interposed therebetween when viewed in the stacking direction of the epitaxial layer 103. It is made to form in the positional relationship which arises. As shown in FIG. 30A, the outer dimension of the ion implantation layers 71 and 72 when the first ion implantation layer 71 and the second ion implantation layer 72 are formed adjacent to each other in the same epitaxial layer is denoted by A. For example, as shown in FIG. 4B, the outer dimension B when the first ion implantation layers 71 and the second ion implantation layers 72 are alternately formed and further overlapped with each other is as follows. For example, it can be reduced by about 6% from A.

(Eighth aspect)
This relates to a method of manufacturing an epitaxial wafer corresponding to a combination of the first mode and the third mode (however, the source gas of the epitaxial layer is not limited to trichlorosilane and the impurity is not limited to phosphorus). ,
A first vapor phase growth step in which a first epitaxial layer is vapor-grown on a silicon single crystal substrate having a main surface orientation of (100);
A first mask forming step of directly forming a first ion implantation mask for ion implantation of the first impurity into the first region of the surface of the first epitaxial layer on the surface of the first epitaxial layer by a photoresist film;
A first ion implantation step of forming a first ion implantation layer at a position corresponding to the first region by implanting a first impurity into the first epitaxial layer on which the first ion implantation mask is formed; ,
A second ion implantation mask for ion-implanting a second impurity different in type from the first impurity into a second region different from the first region on the surface of the first epitaxial layer is formed by a photoresist film. A second mask forming step for forming directly on the surface of the epitaxial layer;
A second ion implantation step of forming a second ion implantation layer at a position corresponding to the second region by implanting a second impurity into the first epitaxial layer on which the second ion implantation mask is formed; ,
A hydrogen heat treatment step that is performed in a temperature range of 950 ° C. or higher and lower than 1100 ° C. under normal pressure after the second ion implantation step is completed;
After the hydrogen heat treatment step is completed, a sealing growth step in which the sealing epitaxial layer is vapor-phase grown in a reduced pressure atmosphere is taken as one set,
A plurality of epitaxial layers are stacked and formed by sandwiching an ion implantation layer as an embedded layer between layers by repeating a set of these steps a plurality of times.

  What is characteristic here is that the hydrogen heat treatment step of the first embodiment performed after the completion of the second ion implantation step is performed in a temperature range of 950 ° C. or more and 1100 ° C. or less under normal pressure. This is a point that also serves as a heat treatment step. After the hydrogen heat treatment step is completed, the sealing epitaxial layer is grown in a vapor phase under a reduced pressure atmosphere, thereby effectively reducing the lateral autodoping of impurities, for example, phosphorus in addition to the various effects of the first aspect. The effect of the third aspect that it can be suppressed is also achieved at the same time.

  In the method described above, only a part of the epitaxial layer including the lowermost epitaxial layer among the epitaxial layers formed with the buried layer is formed of a recess or a step, and the [011] direction or the [0-1-1] direction. If the positioning solid mark having a straight line portion oriented in a direction within 45 ° with respect to the direction is formed, the effect of the second aspect is also achieved at the same time. Further, if the ion-implanted layer is formed so as to have a higher implantation impurity concentration and a smaller pattern area as it is located on the lower layer side, the effect of the fifth aspect can be achieved at the same time.

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiments of the present invention will be described with reference to the drawings.
Here, an n ⁻ type (n-type doped at a low concentration) silicon epitaxial layer and two types of ions having different conductivity types are formed on a silicon single crystal substrate doped with impurities to have a predetermined conductivity type. An example of manufacturing an epitaxial wafer in which injection layers are alternately formed will be described. In order to clarify the operation and effect of the first aspect of the present invention, first, a reference technique example 1 for a method of manufacturing an epitaxial wafer of a reference technique using an oxide film as a mask for ion implantation will be described. Then, the embodiment of the first aspect will be described in comparison with the reference technique. Note that aspects other than the first aspect are basically described together after the description of the first aspect is completed. Further, the reference technique mentioned here means a comparison technique for clarifying the characteristics and superiority of the embodiment of the first aspect, and naturally does not mean a known technique.

(Reference Technology Example 1)
Hereinafter, the reference technique will be described with reference to FIGS. FIG. 17 is a process flow chart when six buried layers are formed.
First, as shown in FIG. 14A, a silicon single crystal substrate 1 having a back surface oxide film 2 formed on the back surface by a CVD method or the like is prepared. In this example, a silicon single crystal substrate 1 (hereinafter simply referred to as “substrate 1”) is an n ⁺ type (highly doped) having a resistivity of 0.010 Ω · cm to 0.015 Ω · cm by antimony doping. n-type) having a crystal axis orientation <100> is used, but is not limited thereto. Next, as shown in FIG. 14B, the n ⁻ -type first silicon epitaxial layer 3 (hereinafter also simply referred to as the epitaxial layer 3) is vapor-phase grown on the main surface of the silicon single crystal substrate 1. Here, the silicon single crystal substrate 1 is arranged in a vapor phase growth apparatus, and the silicon single crystal substrate 1 is heat-treated at a predetermined temperature (for example, 1100 ° C., hydrogen atmosphere) prior to the formation of the epitaxial layer 3, and then the epitaxial layer 3. (For example, film thickness: 5 μm to 10 μm, resistivity: 10 Ω · cm to 50 Ω · cm) is vapor-phase grown (FIG. 17: Step 1).

FIG. 4B is a side cross-sectional view schematically showing an example of the vapor phase growth apparatus 121. The vapor phase growth apparatus 121 includes a reaction vessel 122 formed in a flat box shape, and a source gas SG from a gas introduction port 171 formed at one end of the vapor growth device 121 passes through a flow control unit 124 and is an internal space of the vessel body 123. Supplied horizontally and in one direction. And in the container main body 123, only one wafer W is arrange | positioned on the susceptor 112 arrange | positioned in the susceptor accommodation recessed part 110 substantially horizontally. The target of processing here is a silicon single crystal substrate. However, in the following process, when an epitaxial layer is further formed on a silicon epitaxial wafer in which an epitaxial layer has already been formed on the main surface of the silicon single crystal substrate. Since this will be described with reference to FIG. 4, hereinafter, the processing object is simply referred to as a wafer W. A gas discharge port 128 is formed in the reaction vessel 122 through a venturi-shaped throttle 129 at the end opposite to where the source gas introduction port 171 is formed. The source gas SG introduced from the gas introduction port 171 is exhausted from the gas discharge port 128 after passing over the surface of the wafer W. The source gas SG is, for example, trichlorosilane (SiHCl ₃ ), and a dopant gas (here, n-type impurities are added so that phosphine (PH ₃ ) is used) and H ₂ is appropriately mixed as a carrier gas. The wafer W is rotationally driven by the motor M together with the susceptor 112, and is further heated by the infrared heating lamp 111 to receive the supply of the source gas SG to form an epitaxial layer.

  Returning to FIG. 14, a mark for forming a positioning solid mark 7 (hereinafter also simply referred to as a solid mark 7) shown in (f) on the epitaxial layer 3 formed on the main surface of the silicon single crystal substrate 1. An etching oxide film 4 is formed. The positioning solid mark 7 is used for pattern positioning of the ion implantation layer, and the mark etching oxide film 4 is etched through the following photolithography process (this is an ion implantation mask described later). The same applies to the oxide film forming step). First, the wafer on which the epitaxial layer 3 is formed is cleaned (FIG. 17: step 2), and then the surface of the epitaxial layer is thermally oxidized in an oxidation furnace, whereby the mark etching oxide film 4 having a thickness of about 600 nm, for example. (FIG. 17: Step 3). Subsequently, a photoresist film 51 is formed thereon, and a three-dimensional mark pattern is transferred to the photoresist film 51 through an exposure / development process (FIG. 17: processes 4 to 6).

  Next, the mark etching oxide film 4 is subjected to pattern etching by wet etching through the photoresist film 51. Prior to this, the back oxide film 2 is photo-etched on the back oxide film 2 in order to protect the back oxide film 2 from wet etching. A resist film is applied to form a protective film 52 (FIG. 14C), and a back surface coating process is performed (FIG. 17: step 7). Then, by performing wet etching in this state, the pattern opening 4a of the three-dimensional mark is etched in the mark etching oxide film 4 (FIG. 14C, FIG. 17: step 8). FIG. 14D shows a state where the front and back photoresist films are further removed (FIG. 17: step 9).

  Subsequently, after cleaning the wafer again (FIG. 17: step 10), as shown in FIG. 14E, the surface of the epitaxial layer 3 exposed at the pattern opening 4a has a predetermined thickness (for example, 600 nm). The mark forming oxide film 6 is formed (FIG. 17: step 11). Then, a back surface coating process is performed to protect the back surface oxide film 2 (FIG. 17: step 12), and wet etching for removing the oxide film is performed (FIG. 17: step 13). When the oxide film 6 for mark formation is formed, oxidation occurs. A concave solid mark 7 having a depth corresponding to the thickness of the epitaxial layer 3 thus etched is etched into the shape and position corresponding to the pattern opening 4a of (d). Thereafter, the photoresist film on the back surface side is removed (FIG. 14F, FIG. 17: step 14).

  Subsequently, proceeding to FIG. 15, an ion implantation mask oxide film 8 for forming a boron implantation layer (boron implantation layer) in the epitaxial layer 3 is formed by thermal oxidation. This process is basically the same as the formation process of the mark etching oxide film 4. Wafer cleaning → thermal oxide film formation → photoresist film formation → pattern exposure / development → back surface coating → wet etching (pattern opening etching) It is performed by a series of steps of → photoresist film removal → cleaning (FIG. 17: steps 15 to 23). 15A shows a state after wet etching is completed, and FIG. 15B shows a state where the photoresist film (FIG. 15A: 53, 54) has been removed. 8, a pattern opening 11 for forming a boron implantation layer is formed.

Subsequently, as shown in FIG. 15C, a pre-implantation oxidation step for forming a surface roughness preventing oxide film 12 (film thickness: for example, 50 nm) on the epitaxial layer 3 exposed in the pattern opening 11 is performed. (FIG. 17: Step 24). Then, as shown in FIG. 15D, boron (B) ion implantation (implantation energy: for example, 50 keV to 70 keV, dose amount: 2 × 10 ¹² / cm ² ) is performed based on a known ion implantation method. Then, a boron implantation layer 13 is formed at a position corresponding to the pattern opening 11 of the epitaxial layer 3 (FIG. 17: step 25). As shown in FIG. 15E, the pattern opening 11 formed by wet etching of the oxide film is likely to have a tapered inner surface, which causes variations in the formation area of the boron implantation layer 13.

  Next, as shown in FIG. 15 (f), a crystallinity recovery and activation heat treatment (for example, 950 ° C., for recovering the crystallinity of damage caused in the boron implanted layer 13 by ion implantation and activating carriers). Annealing for 30 minutes is performed in a nitrogen atmosphere with the oxide film 12 remaining (FIG. 17: step 26). As shown in FIG. 12B, surface roughness of the boron implantation layer 13 (ion implantation layer) is prevented by performing the crystallinity recovery and activation heat treatment with the oxide film 12 left. As shown in FIG. 15 (g), the boron implanted layer 13 is slightly affected by thermal diffusion due to the influence of the thermal history (corresponding to the second thermal history described in the problem to be solved by the invention) by this heat treatment. Spreading occurs.

  When the crystallinity recovery and activation heat treatment is completed, as shown in FIG. 15 (h), the back surface coating → wet etching (FIG. 17: Steps 27 and 28) is performed again, and the oxide film 8 for the ion implantation mask on the main surface. Then, the oxide film 12 for preventing surface roughness is removed. Since the oxide film 8 is formed by oxidization so that the surface layer portion of the epitaxial layer 3 is crushed, if this is removed, the width d of the three-dimensional mark 7 becomes the oxide film formation margin as shown in FIG. Is expanded by an amount equivalent to that of d to become d ′, and the shape is broken.

  Next, as shown in FIG. 16A, an ion implantation mask oxide film 15 for forming a phosphorus implantation layer in the epitaxial layer 3 is formed in the same manner as in the boron implantation layer formation (FIG. 17). : Steps 29-38). Reference numerals 55 and 56 denote photoresist films. A pattern opening 18 for forming a phosphorus implantation layer is formed in the oxide film 15 for the ion implantation mask. Here, the heat treatment (corresponding to the first thermal history) when forming the oxide film 15 promotes the expansion of the boron implantation layer 13 already formed as shown in FIG.

Also here, the pre-implantation oxidation step (formation of the oxide film 19 for preventing surface roughening, FIG. 17: step 39) shown in FIG. 16C is performed. As shown in FIG. Thermal diffusion of the boron implanted layer 13 further proceeds by heat treatment (corresponding to the third thermal history). Next, when phosphorus (P) ion implantation (implantation energy: for example, 120 keV to 150 keV, dose amount: 2 × 10 ¹² / cm ² ) is performed, phosphorus implantation is performed at a position corresponding to the pattern opening 18 of the epitaxial layer 3. Layer 20 is formed (FIG. 17: step 40). Then, as shown in FIG. 16E, crystallinity recovery and activation heat treatment is performed on the phosphorus implantation layer 20 with the oxide film 19 remaining (FIG. 17: step 41). As shown in FIG. 16F, thermal diffusion of the boron implantation layer 13 and the phosphorus implantation layer 20 proceeds by the heat treatment (second thermal history) at this time.

  After the boron implantation layer 13 and the phosphorus implantation layer 20 are thus formed, the oxide film 15 is removed through backside coating → wet etching (FIG. 17: steps 42 and 43) as shown in FIG. Then, as shown in FIG. 16 (h), the width d ′ of the solid mark 7 is further expanded to d ″, resulting in dimensional deformation. Then, the resist film 57 formed as the back coat is removed and washed. Thereafter (FIG. 17: Steps 44 and 45), the second silicon epitaxial layer 22 is vapor-grown on the epitaxial layer 3 (FIG. 17: Step 46), whereby the boron implantation layer 13 and the phosphorus implantation layer 20 are The buried boron implantation layer 13 ′ and the buried phosphorus implantation layer 20 ′ are formed, and thereafter, the same process is repeated to form a structure in which the buried boron implantation layer, the buried phosphorus implantation layer, and the epitaxial layer are alternately stacked. In order to use the boron implanted layer and the phosphorus implanted layer formed last as buried layers, an additional epitaxial layer forming step is performed thereafter.

  In the reference technique described above, the formation / removal of the oxide film is repeated with respect to the three-dimensional mark 7 formed by the formation / removal of the oxide film. Therefore, the surface layer portion of the epitaxial layer on which the three-dimensional mark 7 is formed becomes an oxide film. Lost by transformation and removal, it loses its shape. When the epitaxial layer 22 is vapor-phase grown on the solid mark 7, as shown in FIG. 16 (i), the solid shape 7 'remains slightly lifted on the surface of the epitaxial layer 22, but accurate pattern alignment is performed. It is almost the limit that can be used. Therefore, a positioning solid mark must be newly formed at a position different from the solid shape 7 'on the surface of the epitaxial layer 22 every cycle. In FIG. 17, every time the buried layer is formed, the entire steps 1 to 45 including the formation of the three-dimensional mark (steps 3 to 14) must be repeated. The number actually reaches 271. Further, in one cycle, the oxide film forming process is performed 6 times (3, 11, 16, 24, 31, 39) as described above, and the back surface coating process is performed 6 times (7, 12, 20, 27, 35, 42). The oxide film wet etching process (including the removal process) is 6 times (8, 13, 21, 28, 36, 43), and the oxide film formation and derivation process occupies 18 processes out of 45 processes. 108 steps out of 271 steps. Even if it sees from this, it will be clear how many processes are required in connection with formation / removal of an oxide film in the above-mentioned reference technique.

Further, in the cycle of steps 1 to 45, the thermal oxide film forming process for pattern formation is performed four times (3, 11, 16, 31), the pre-implantation oxidizing process is performed twice (24, 39), and the crystal In addition, the heat recovery and activation heat treatment is performed twice (26, 41), and the process of adding a thermal history to the wafer is included eight times in total. Therefore, when forming the buried layer 13 'and the phosphorus implanted layer 20' as a buried layer over six layers, the lowermost layer is limited to the one added at the time of forming the following five layers. 8 × 5 = 40 thermal histories will be accumulated. As a result, as already described with reference to FIG. 6C, the buried layer 101 located in the lower layer has a larger spread due to thermal diffusion, and the vertical and horizontal diffusions are non-uniform in the stacking direction. End up. Then, as shown in FIG. 6D, the vertical addition region 105 obtained by connecting these buried layers 101 in the vertical direction by diffusion heat treatment is also uneven and becomes thicker at the lower side.
This completes the description of the reference technology.

(Embodiment 1)
Next, an embodiment of the present invention will be described with reference to FIGS. FIG. 3 is a process flow chart when six buried layers are formed.
First, as shown in FIG. 1A, a silicon single crystal substrate 1 having a back surface oxide film 2 formed on the back surface by a CVD method or the like is prepared. Next, as shown in FIG. 1B, the n ⁻ -type first epitaxial layer 3 is vapor-phase grown on the main surface of the silicon single crystal substrate 1 (FIG. 3: step 1). The processes and conditions up to here are exactly the same as in the above-mentioned reference technique.

  Next, as shown in FIG. 1C, a photoresist film 60 (film thickness: about 1.2 μm, for example) for forming a positioning solid mark is formed. By exposing and developing the pattern of the positioning solid mark on the photoresist film 60, a pattern opening 61 is formed to form a mask for forming the solid mark (FIG. 3: steps 2 to 4). Here, the first positioning solid mark is positioned based on an orientation flat or notch previously formed on the silicon single crystal substrate. Then, as shown in FIG. 1D, by performing dry etching on the substrate in this state, a concave solid mark 7 is formed at a position corresponding to the pattern opening 61 (FIG. 3: step 5, depth). : For example, 200 nm to 300 nm). As the dry etching method, for example, reactive ion etching can be employed. Thereafter, the photoresist film 60 is removed (FIG. 3: step 6).

  The formation of the positioning solid mark 7 requires 13 steps of Steps 2 to 14 in FIG. 17 in the above-mentioned Reference Technology Example 1, whereas in this embodiment, Steps 2 to 6 in FIG. It is shortened to only 5 steps. This eliminates the need for forming the mark etching oxide film used in Reference Example 1, and corresponds to the cleaning process, the back surface coating process, the oxide film etching process, and the formation of the mark forming oxide film. This is due to the fact that the cleaning process, the back surface coating process, the oxide film removing process, and the like are unnecessary.

  Next, returning to FIG. 1, after cleaning the wafer (FIG. 3: step 7), a photoresist film is applied directly without actively forming an oxide film on the exposed first epitaxial layer 3 (FIG. 3: step). 8. Film thickness: For example, 1.2 μm, positive in the figure). Then, a pattern opening 63 for injecting boron (B) as a first impurity is formed by aligning the pattern with the solid mark 7 and exposing and developing the photoresist film. The first ion implantation mask 62 is formed (FIG. 3: steps 9 and 10).

  Then, as shown in FIG. 1E, when boron ions are implanted under the same conditions as in Reference Technology Example 1 with the first ion implantation mask 62 formed, the pattern of the epitaxial layer 3 is obtained. A region corresponding to the opening 63 is defined as a first region, and a boron implantation layer 71 as a first ion implantation layer is formed therein (FIG. 3: step 11). Thereafter, the first ion implantation mask 62 is removed (FIG. 1G, FIG. 3: step 12). Here, the pattern opening 63 formed by exposure / development of the photoresist film has an inner surface formed by wet etching of an oxide film as shown in FIG. 1 (f) (FIG. 15 (e)). It becomes steeper and sharper, and variations in the formation area of the boron implantation layer 71 hardly occur.

  Now, the formation of the boron implantation layer 71 required 12 steps of steps 15 to 26 in FIG. 17 including the crystallinity recovery and activation heat treatment in the above-mentioned reference technology example 1. In the embodiment, the number of steps is shortened to 6 steps 7 to 12 in FIG. This is because the oxide film is not used for the ion implantation mask and the pre-implantation oxidation is not performed, so that in addition to these two oxidation steps, the steps of cleaning, back surface coating, and oxide film etching are omitted. To do.

  After the boron implantation layer 71 is formed, the wafer is cleaned (FIG. 3: step 13), and then the exposed first epitaxial layer 3 is formed on the exposed first epitaxial layer 3 without performing the crystallinity recovery and activation heat treatment. In the same manner, a photoresist film is directly applied without actively forming an oxide film (FIG. 3: step 14). The pattern opening 65 for injecting phosphorus (P) as the second impurity by aligning the pattern with the three-dimensional mark 7 with respect to the photoresist film and further exposing and developing the pattern opening 65 is described above. A second ion implantation mask 64 is formed at a position different from the pattern opening 63 (FIG. 1E) for boron implantation (FIG. 3: steps 15 and 16). When the second ion implantation mask 64 is formed and phosphorus is ion-implanted as the second impurity under the same conditions as in the reference technique, the pattern opening 65 of the first epitaxial layer 3 is supported. In this region, a phosphorus implantation layer 72 as a second ion implantation layer is formed using this as a second region (FIG. 3: step 17). Thereafter, the second ion implantation mask 64 is removed (FIG. 2B, FIG. 3: step 18).

  In the reference technique example 1 described above, 15 steps of steps 27 to 41 in FIG. 17 including etching for removing the oxide film and heat treatment for activating crystallinity are required. In this embodiment, boron is used. Similar to the formation of the implantation layer, the steps related to the formation / removal of the oxide film are omitted, so that the number of steps is shortened to six steps 13 to 18 in FIG.

  Then, after cleaning the wafer (FIG. 3: step 19), as shown in FIG. 2D, crystallinity recovery and activation heat treatment is performed. As shown in FIG. 4A, this heat treatment is performed immediately before the wafer W is placed in the vapor phase growth apparatus 121 and the second epitaxial layer 22 (FIG. 2F) is vapor-phase grown. This is performed by introducing hydrogen into the vapor phase growth apparatus 121 (FIG. 3: step 20). This heat treatment in a hydrogen atmosphere is efficient because it can also serve as a heat treatment for removing the natural oxide film on the wafer surface that is normally performed before vapor phase growth.

  By performing the crystallinity recovery and activation heat treatment after the ion implantation in the hydrogen atmosphere as described above, as shown in FIG. 13, although the oxide film is not actively formed before the ion implantation, Not only is the surface roughness of the injection layer less likely to occur, but the roughness of the surface roughness is reduced. As already explained repeatedly, the most contributing factor to the process shortening effect according to the present invention is that the oxide film formation / removal is not necessary, but the oxide film formation process can be omitted. It can also be said that the fundamental factor is the achievement of the rough surface prevention effect by the hydrogen heat treatment.

  Further, in the above-described Reference Technique Example 1, the boron implantation layer 13 and the phosphorus implantation layer 20 were individually subjected to crystallinity recovery and activation heat treatment, whereas in this embodiment, in the above hydrogen atmosphere Due to the heat treatment, the crystallinity recovery and activation heat treatment for the boron implantation layer 71 and the phosphorus implantation layer 72 is performed at one time, and the process is further shortened.

  The treatment temperature in the heat treatment step in the hydrogen atmosphere is preferably adjusted at 700 ° C. or higher. When the processing temperature is less than 700 ° C., the crystallinity recovery and activation of the ion implantation layer are not sufficiently performed. The treatment temperature is more preferably adjusted in the range of 850 ° C to 1100 ° C. When the heat treatment temperature is less than 850 ° C., the natural oxide film on the wafer surface is hardly etched with hydrogen. Further, when the heat treatment temperature exceeds 1100 ° C., impurity diffusion in the ion implantation layer cannot be ignored. Further, the heat treatment step in a hydrogen atmosphere can be performed under normal pressure to achieve a sufficient surface roughness prevention effect, but within a range where the surface roughness prevention effect is not impaired, a reduced hydrogen atmosphere (for example, 20 torr). (About 760 torr).

When the heat treatment in the hydrogen atmosphere is completed, as shown in FIG. 4B, the vapor phase growth process is performed by continuously flowing trichlorosilane (SiHCl ₃ ) as the source gas SG in the vapor phase growth apparatus 121. As shown in FIG. 2 (f), the second epitaxial layer 22 is formed, and the boron implantation layer 71 and the phosphorus implantation layer 72, which are the first and second ion implantation layers, are formed by the first and second buried layers. A boron buried layer 71 ′ and a phosphorus buried layer 72 ′ are formed (FIG. 3: step 20). Thus, the heat treatment step in the hydrogen atmosphere and the vapor phase growth step for forming the second epitaxial layer are performed as a series of steps (effectively one step) in one vapor phase growth apparatus. Therefore, the entire process can be further shortened.

  In this vapor phase growth step, a thin epitaxial layer for sealing is first vapor phase grown (so-called cap deposition process) in order to suppress lateral auto-doping from the boron implantation layer 71 and the phosphorus implantation layer 72. It is desirable to perform a multi-step process in which the second epitaxial layer 22 is finally grown.

  Thus, the cycle from the formation of the solid mark on the epitaxial layer to the formation of the boron buried layer 71 ′ and the phosphorus buried layer 72 ′ is completed, but as is apparent from FIG. It can be seen that the number of steps in the cycle is 19 steps of 2 to 20, which is reduced to less than half of Reference Technique Example 1 (45 steps) using the oxide film as an ion implantation mask. In addition, the process of adding a thermal history to the wafer includes 8 processes in the reference technique example 1, whereas the first embodiment of the present invention includes only one process of the epitaxial growth process. Therefore, as shown in FIG. 2 (e), the thermal diffusion of the ion implantation layer (boron implantation layer 71 and phosphorus implantation layer 72) generated per cycle for forming one buried layer is compared with the reference technique. Become much smaller. As a result, as shown in FIG. 5, the buried layers arranged in the vertical direction have a small difference in the spread in the horizontal direction, and uniform layers separated from each other in the vertical direction can be obtained. Also, a longitudinal addition region (also referred to as a “longitudinal impurity addition region”) obtained by laminating and forming a plurality of epitaxial layers and connecting these buried layers in the longitudinal direction by diffusion heat treatment is also a lamination of cross-sectional areas. A uniform one can be realized depending on the direction.

FIG. 7 is a cross-sectional view schematically showing a main part of the silicon epitaxial wafer obtained by the manufacturing method of the first embodiment. Between each epitaxial layer, a p-type boron buried layer as a first buried layer and an n-type phosphorus buried layer as a second buried layer are formed in the same region of each epitaxial layer. In addition, the boron implantation layers and the phosphorus implantation layers that are continuous in the stacking direction of the epitaxial layers are all formed so as to be separated from each other in the stacking direction via the n ⁻ type epitaxial layer region. When diffusion heat treatment is performed on such an epitaxial wafer, the boron buried layer and the phosphorus buried layer constituting the impurity doped region are connected in the vertical direction as shown in FIG. It becomes an addition region. These longitudinally added regions have remarkably uniform cross-sectional areas in the stacking direction as compared with the reference technique shown in FIG.

FIG. 10A shows an example in which the manufacturing method of the present invention is applied to the manufacture of an epitaxial wafer for MOSFET elements. A plurality of n ⁻ type epitaxial layers 253a to 253c are stacked on a p ⁻ type silicon single crystal substrate 251, and an n ⁺ type buried layer 252 is formed between the substrate 251 and the lowermost epitaxial layer 253a. At the same time, a ring-shaped boron implantation layer and a phosphorus implantation layer are buried in a separated form between the layers of the epitaxial layers 253a to 253c. In FIG. 10A, a column of boron implantation layers in the vertical direction is formed outside the buried layer 252 so as to surround it. On the other hand, the column of the phosphorus implantation layers in the vertical direction is formed at a position overlapping the buried layer 252 in projection onto a plane orthogonal to the stacking direction of the epitaxial layers 253a to 253c. As shown in FIG. 10B, by performing diffusion heat treatment on this, the boron implantation layer becomes a cylindrical p ⁺ -type element isolation region 254 which is a vertical boron addition region, and the phosphorus implantation layer becomes a vertical phosphorous layer. A cylindrical n ⁺ -type drain region 255 (conductive to the buried layer 252), which is an addition region, is formed. FIG. 10B shows a state in which a p-type well, an n-type source region, and a gate are formed inside the drain region 255 to form an n-channel MOSFET element.

On the other hand, FIG. 11A shows an example in which the manufacturing method of the present invention is applied to the manufacture of an epitaxial wafer for bipolar elements. A plurality of n ⁻ type epitaxial layers 263a to 263c are stacked on a p ⁻ type silicon single crystal substrate 261, and an n ⁺ type buried layer 262 is formed between the substrate 261 and the lowermost epitaxial layer 263a. At the same time, a ring-like boron implantation layer and a flat-plate-like phosphorus implantation layer are buried in a separated form between the epitaxial layers 263a to 263c. As shown in FIG. 11B, by performing diffusion heat treatment on this, the boron implantation layer becomes a cylindrical p ⁺ type element isolation region 264 which is a vertical boron addition region, and the phosphorus implantation layer is added with vertical phosphorus addition. The region is a columnar n ⁺ -type collector region 265. FIG. 11B shows a state in which an npn bipolar element is formed by forming a p-type base and an n-type emitter region inside the element isolation region 264.
In addition, the manufacturing method of this invention shown in FIG.10 and FIG.11 has illustrated the case where the semiconductor element using a p < ^- > type | mold silicon single crystal substrate is manufactured. However, the manufacturing method and silicon epitaxial wafer according to the present invention are not limited to this, and can be applied to an epitaxial wafer for a semiconductor device manufactured using a p ⁺ type silicon single crystal substrate and a manufacturing method thereof. is there. Furthermore, it goes without saying that the present invention can also be applied to an n-type silicon single crystal substrate.

(Embodiment 2)
Next, an embodiment of the second aspect will be described.
As shown in FIGS. 1 and 2, in the above-described first embodiment, the shape of the three-dimensional mark 7 (transfer source positioning three-dimensional mark) on the first epitaxial layer 3 is not significantly collapsed, and the above-described buried layer is formed. The original state is substantially maintained even at the end of one cycle of forming one layer (FIG. 2C). As a result, as shown in FIG. 2 (f), when the second epitaxial layer 22 is stacked on the upper side, the solid mark 7 on the lower layer side is lifted and transferred without much deformation. Therefore, when the second epitaxial layer 22 is newly used as the first epitaxial layer and the process cycle of ion implantation and vapor phase growth is repeated, the transferred mark can be used as the positioning solid mark 7 ′. (Ie, used as a transfer solid mark).

  As a result, in the cycle for forming the second boron buried layer and the phosphorus buried layer, the solid mark forming step (steps 2 to 7 in FIG. 3) can be omitted, and the process can be further shortened. It becomes. In addition, in the epitaxial wafer obtained as a result, the three-dimensional mark for transfer source positioning that does not originate from the three-dimensional mark for positioning of the lower epitaxial layer and serves as a transfer source for forming the transfer three-dimensional mark on the subsequent layers, Of the epitaxial layer in which the buried layer is formed, only a part including the lowermost layer is formed. In FIG. 3, the first cycle including the solid mark forming step is 19 steps of steps 2 to 20, whereas the second cycle not forming the solid mark is shortened by 6 steps, 13 steps of steps 21 to 33. It is. When the epitaxial layer and the buried layer are formed in a plurality of layers, the first cycle may be only the first layer, and thereafter only the second cycle may be repeated. Further, depending on the formation thickness of the epitaxial layer, as shown in FIG. 9, as shown in FIG. 9, the solid marks 7b (FIG. 9 (a)) and 7c (FIG. )) May be cut off at a fixed number of layers, and a new solid mark 7d may be formed at another position (FIG. 9C). Then, the positioning solid marks are formed on the uppermost layer of the epitaxial layers in which the buried layer is formed, in a positional relationship that does not overlap each other by a number smaller than the number of epitaxial layers. At this time, among the plurality of epitaxial layers 3a to 3c, 7a formed on the lowermost epitaxial layer 3a and 7d formed on the two epitaxial layers 3c function as a transfer source positioning solid mark.

  For example, in FIG. 3, it is designed so that a solid mark is newly formed every other layer, and as a result, the first cycle and the second cycle are alternately repeated. In the above-described embodiment of the present invention, the final number of steps required to form six buried layers is 97, which is reduced to more than one third of the number of steps 271 of the reference technique of FIG. I understand.

  In the above process, a process that does not require the formation / removal of the oxide film through the formation of the boron implantation layer 71 and the phosphorus implantation layer 72 is employed. It can be said that it is more advantageous. However, even in the case of adopting the process of performing the pre-implantation oxidation process as usual without performing the heat treatment in the hydrogen atmosphere, the thickness of the oxide film formed by the pre-implantation oxidation process is as small as about 50 nm. Can be applied.

  In the above process, the transfer solid mark can be directly used as a positioning solid mark for the layer, and an oxide film mask is not used, so that a plurality of ion implantation layers of a plurality of conductivity types are patterned in the same epitaxial layer. Even in this case, the three-dimensional mark used for mask positioning of the previous conductivity type ion implantation layer pattern can also be used for mask positioning of the next conductivity type ion implantation layer pattern. Therefore, at least one positioning solid mark for mask positioning is sufficient regardless of how many types of patterns are formed in one epitaxial layer. This is one of the main factors that can reduce the number of three-dimensional positioning marks to be newly etched, and also has a new advantage that the number of masks can be greatly reduced. Further, there is an effect that the area occupied by the positioning solid mark on the main surface of the epitaxial wafer can be reduced.

(Reference Technology Example 2)
On the other hand, in the process of Reference Technology Example 1 in which an oxide film is used as the ion implantation mask, ion implantation layers having different conductivity types, for example, a boron implantation layer 71 and a phosphorus implantation layer 72 are formed on the epitaxial layer 3 as shown in FIG. , The shape of the positioning solid mark 7 collapses with the formation and peeling of the oxide film used as the ion implantation mask once. Therefore, as the positioning solid mark 7, the positioning solid mark 7 h for pattern formation of the boron implantation layer 71 and the positioning solid mark 7 i for pattern formation of the phosphorus implantation layer 72 are individually provided on the same epitaxial layer 3. Form. When the epitaxial layer 22 is formed so as to overlap therewith, a new positioning solid mark is formed on the epitaxial layer 22. In this case, since the positioning solid mark 7 on the lower epitaxial layer 3 is somewhat transferred to the upper epitaxial layer 22, the upper positioning solid mark is positioned using this. At this time, since the positioning accuracy cannot be ensured with the transfer solid mark based on the solid marks 7h and 7i broken by the formation / peeling of the oxide film, before the upper epitaxial layer 22 is formed, the positioning solid mark on the upper layer is attached. A new positioning solid mark 7j used for forming is formed. As shown in FIG. 23B, a positioning solid mark is newly formed using a transfer solid mark 7j ′ based on the positioning solid mark 7j. In any case, a plurality of, in this case, three positioning solid marks are formed for one epitaxial layer.

  In this case, since the shape of the positioning solid mark on the lower layer side can be recognized from the upper layer side, the positioning solid mark on the upper layer side needs to be formed so as not to overlap with the positioning solid mark on the lower layer side. . As a result, when a positioning solid mark is formed for each layer, the number of solid marks corresponding to the number of layers is formed or transferred to the uppermost epitaxial layer. For example, FIG. 23 (d) shows an example in which the three epitaxial layers 103a to 103c are formed while the buried layers 71 ′ and 72 ′ or the ion implantation layers 71 and 72 are formed. In addition to the positioning solid mark 7 newly etched on the layer 103c, the epitaxial layer 103c is transferred to the epitaxial layer 103c by passing the transfer mark 207 on the intermediate layer 103b based on the positioning solid mark 7 etched below the two layers. A total of three sets of three-dimensional marks, that is, a three-dimensional solid mark 307 that has been transferred onto the surface and a three-dimensional solid mark 207 based on the positioning solid mark 7 that has been newly etched in the intermediate layer 103b, appear. In particular, as shown in FIGS. 23B and 23C, when a plurality of positioning solid marks are formed for one layer, the number further increases. As a result, in the uppermost epitaxial layer of the obtained epitaxial wafer, a much larger number of three-dimensional marks appear than the number of formed epitaxial layers, and there is a problem that a space for displaying the three-dimensional marks must be prepared. There is.

  Further, in order to form the vertical diffusion region, for example, as shown in FIG. 7, when the same conductivity type buried layer is formed at the same position, the mask pattern of the ion implantation layer may be exactly the same for each layer. . However, since the formation position of the positioning solid mark must be changed for each layer, the pattern of the ion implantation layer is the same, but in the end, only a large number of the pattern positions of the positioning solid mark are changed. There is also a problem that a mask must be prepared.

(Embodiment 3)
In order to secure the shape accuracy that can be used for positioning, it is important to consider the shape of the transfer solid mark that is unlikely to be deformed due to the vapor phase growth mechanism of silicon. For example, FIG. 22 shows a silicon single crystal substrate with a plane orientation (100), but a cross-shaped solid in which a straight portion 407a in the [011] direction and a straight portion 407b in the [01-1] direction intersect. When the mark 407 is used, the transfer solid mark 407 ′ transferred to the epitaxial layer formed on the solid mark 407 is reduced in width of the straight portion 407a ′ in the [011] direction, for example. The pattern deformation that the width of the straight portion 407b ′ in the [01-1] direction orthogonal to the width increases conversely tends to occur.

  As a result of intensive studies by the present inventors, when an epitaxial layer is formed on a silicon single crystal substrate having a plane orientation (100), as shown in FIG. 20, the positioning solid mark 507 has a [011] direction or [0] -1-1] It has been found that if the linear θ is formed so that the angle θ with respect to the direction is within 45 °, the transfer solid mark is not easily deformed based on the linear portion. FIG. 18 shows a specific example of such a positioning solid mark 507, and two line patterns 507a and 507b (for example, a width of about 4 μm and a depth of about 0.2 μm, respectively) formed in a groove shape. Are formed in an L shape in which one end is shared with each other. However, as shown in FIG. 19, it is also possible to form the solid mark in a convex shape. Here, the three-dimensional mark 517 is formed in an L shape in a form that is substantially perpendicular to the two line patterns 517a and 517b having a convex shape in a shallow concave portion 517c on the surface of the substrate. An off-angle of up to about 4 ° can be given to the main surface of the substrate. In this case, it is considered that the crystal axis orientation is approximately the same as that when no off-angle is given.

The following experiment was conducted to confirm the above effect. First, as a silicon single crystal substrate, a silicon single crystal substrate of the form shown in FIG. 18A having a crystal axis orientation of [100] (but no off-angle) and an orientation flat surface of (011) is prepared. A three-dimensional mark 527 having a linear convex shape with a height of 130 nm and a width of 12 μm shown in FIG. 21 was formed. However, the direction of the edge of the solid mark 527 was set in various directions, with the [011] direction being θ = 0 ° and the [01-1] direction being θ = 90 °. Next, with the vapor phase growth apparatus 122 of the type shown in FIG. 4, the epitaxial layer is formed on the main surface on which the solid mark 527 is formed, using trichlorosilane (SiHCl ₃ ) at 1080 ° C. and 80 torr to a thickness of 24 μm. Only formed.

  Then, a negative photoresist is applied to the substrate after the growth of the epitaxial layer by 0.8 μm, and the three-dimensional mark 527 is used as an alignment pattern, whereby the patterned mask is formed using a known aligner. An attempt was made to perform automatic positioning (auto alignment) on the epitaxial wafer. In this auto alignment, the reflected light from the pattern edge of the three-dimensional mark 527 and the mask formed on the epitaxial wafer is detected photoelectrically, and the epitaxial wafer and the mask are relatively moved so that the deviation of the edge position is eliminated. Is what you do. FIG. 21 shows a measurement profile of the pattern position signal for each value of θ. As a result, when θ exceeds 45 °, the reflection peak from one edge becomes extremely small and auto-alignment becomes impossible. However, it is found that auto-alignment can be performed without any problem if θ is 45 ° or less. This is because, in the transferred solid mark of the solid mark 527 transferred to the epitaxial layer, one edge of the three-dimensional mark is significantly deformed. However, if θ is 45 ° or less, the pattern can be deformed to the extent that auto alignment can be performed. It means that there is an effect that it can be suppressed to be small.

(Embodiment 4)
Next, an embodiment of the third aspect will be described. As described in the embodiment of the first aspect, the epitaxial layer vapor phase growth step is performed by first forming a thin epitaxial layer for sealing in order to suppress lateral autodoping from the boron implantation layer and the phosphorus implantation layer. It is desirable to use a two-stage process in which the second epitaxial layer is grown after vapor phase growth (so-called cap deposition process). This is particularly important from the viewpoint of preventing lateral autodoping of phosphorus from the phosphorus implantation layer.

  As a result of studies by the present inventors, as shown in FIG. 24, for the phosphorus implantation layer 72 shown in FIG. First, as shown in FIG. 5B, a heat treatment step is performed in which a heat treatment is performed in a hydrogen atmosphere at 950 ° C. to 1100 ° C. (preferably 1060 ° C. to 1100 ° C.) under normal pressure. A portion of the substrate is diffused out in advance into the gas phase to lower the temperature of the surface of the phosphorus implantation layer, and after the heat treatment step is completed, a silicon source gas is supplied in a reduced-pressure atmosphere as shown in (c). Then, the epitaxial growth layer 22a is vapor-phase grown (sealing growth step), and the second epitaxial layer 22 is vapor-grown on the sealing epitaxial layer 22a as shown in FIG. Can do the phosphorus lateral auto-dopin That there is a very effective it has been found to prevent. If the embodiment of the first aspect described above is applied, the crystallinity recovery and activation heat treatment can be performed simultaneously by performing the heat treatment in the hydrogen atmosphere shown in FIG. 2B for about 30 minutes. . This corresponds to the embodiment of the seventh aspect. Further, no dopant gas is supplied during vapor phase growth of the sealing epitaxial layer 22a. However, if the formation thickness of the sealing epitaxial layer 22a is greater than 1 μm, a difference in the net carrier concentration occurs at the interface with the second epitaxial layer 22, so the thickness is preferably 1 μm or less. However, since the sealing effect is insufficient when the thickness is less than 0.2 μm, the thickness of the sealing epitaxial layer 22 a is preferably 0.2 μm to 1 μm or less.

  The sealing growth step is desirably performed at a pressure of 5 to 60 torr. If the pressure is less than 5 torr, the vapor phase growth rate is low and the efficiency is poor, and if the pressure exceeds 60 torr, the effect of suppressing the lateral autodoping of phosphorus becomes insufficient.

  In addition, since auto-doping is sufficiently prevented after the sealing growth step, this growth step is performed in the same vapor phase growth apparatus under conditions of high temperature and / or high pressure with higher production efficiency than the sealing growth step. be able to.

The following experiment was conducted to confirm the effect of the third aspect. First, as a silicon single crystal substrate, it has a diameter of 200 mm, crystal axis orientation [100] (but no off-angle), n ⁺ type (resistivity: 0.010 to 0.015 Ω · cm), and is used for preventing autodoping on the back surface. An oxide film having a thickness of 0.5 μm was prepared. Next, a p ^- type first epitaxial layer (net carrier concentration 3 × 10 ¹⁵ atoms / cm ³ ) is diluted on the main surface with hydrogen as a dopant gas using trichlorosilane (SiHCl ₃ ) as a silicon source gas. By using diborane (B ₂ H ₆ ), a thickness of 10 μm was formed at a vapor phase growth temperature of 1130 ° C. and a normal pressure (resistivity: 4.5 Ω · cm). Next, a plurality of phosphorus implantation layers are formed by ion implantation so that the dimensions of the individual implantation regions are 1730 μm × 8 μm in a vertically long shape and are arranged at intervals of about 16 μm in the width direction with respect to the first epitaxial layer. . However, prior to the formation of the ion implantation layer, pre-implantation oxidation treatment is performed so that an oxide film having a thickness of about 50 nm is formed. The ion implantation is performed at an acceleration voltage of 120 keV to 150 keV and a dose of 2 × 10 ¹² / cm ² . went. Further, after the implantation, heat treatment was performed at 950 ° C. for 30 minutes in a nitrogen atmosphere in order to recover and activate the crystallinity.

Subsequently, after the oxide film formed by the pre-implantation oxidation is removed by wet etching, the substrate is placed in a reaction vessel 122 of a vapor phase growth apparatus 121 of the type shown in FIG. 4, and 900 ° C. and 1080 ° C. in a hydrogen atmosphere. And a heat treatment at normal temperature (760 torr) at each temperature of 1190 ° C. for 10 minutes. Then, a sealing epitaxial layer having a thickness of 0.5 μm is grown at 850 ° C. and 25 torr using the same raw material gas as that of the first epitaxial layer and without supplying a dopant gas, and subsequently thickened at 1080 ° C. and 80 torr. A 10 μm second epitaxial layer was grown by supplying diborane (B ₂ H ₆ ) as a dopant gas (net carrier concentration: 3 × 10 ¹⁵ atoms / cm ³ ).

  The epitaxial wafer having the phosphorus buried layer thus obtained was angle-polished so as to form an angle of about 1 ° with the main surface so that a plurality of phosphorus buried layers arranged in the lateral direction appeared on the polished surface. Further, as shown in FIG. 26, on the polished surface, a measurement line is set in a direction perpendicular to the interface of the epitaxial layer between adjacent phosphorus buried layers (that is, at a position not crossing the phosphorus buried layer). The net carrier concentration profile in the epitaxial layer was measured by the spreading resistance method. In the measurement profile, BH is the lowest net carrier concentration at the interface of the epitaxial layer, AH is the average net carrier concentration in the most stable region of the carrier concentration in the epitaxial layer, and the value of (AH−BH) / AH is I asked for each. A smaller value of (AH−BH) / AH means that the lateral autodoping of phosphorus at the epitaxial layer interface is smaller. The above measurement results are shown in Table 1.

  That is, (AH-BH) / AH becomes 0.5 or less only when the atmospheric pressure heat treatment temperature before the growth of the sealing epitaxial layer is 1080 ° C. Autodoping is effectively suppressed. FIGS. 27A and 27B are measurement examples of the carrier concentration profile by the spreading resistance method. FIG. 27A shows the case where the atmospheric pressure heat treatment temperature is 1080 ° C., and FIG. In (a), the carrier concentration does not decrease so much at the interface position, whereas in (b), the carrier concentration rapidly decreases due to the lateral autodoping of the phosphorus component into the p-type epitaxial layer. Recognize. FIG. 2 shows an enlarged photograph of a sample surface obtained by immersing the sample surface on which the carrier concentration was measured in a stain solution made of a hydrofluoric acid-nitric acid aqueous solution and then irradiating with light. The black portion of the background is the p-type epitaxial layer, and the bright portion of the background is the n-type phosphorus buried layer. In (a), there is no connection between the adjacent phosphor buried layers. In contrast, in (b), the phosphorous buried layer is connected at the interface position by the lateral autodoping of the phosphorous component.

(Embodiment 5)
Next, an embodiment of the fourth aspect will be described. The gist of this aspect is that when both the boron implantation layer and the phosphorus implantation layer are formed in the first epitaxial layer, the pre-implantation oxidation step for oxidizing the surface of the first epitaxial layer is not performed after the phosphorus implantation layer is formed. . That is, the phosphorus implantation step is performed after the boron implantation step. And this process has already been demonstrated as the said reference technical example 1 shown in FIGS.

  That is, after the boron implantation layer 13 is formed in FIG. 15 (h), the ion implantation mask oxide film 15 is formed, and the boron implantation layer 13 is covered with the oxide film 15 (FIG. 16 (c)). However, since boron is easily taken into the oxide film, even if the oxide film 15 is formed, it is not concentrated on the surface layer portion of the boron implantation layer 13 but rather the surface concentration is lowered, so that autodoping is reduced. Works. On the other hand, phosphorus is likely to gather at the interface with the oxide film. However, as shown in FIG. 16C, phosphorus is injected after the formation of the pre-implantation oxide film 19, so that the surface of the phosphorus implanted layer 20 is formed. The phosphorus enrichment is avoided. As a result, even if the second epitaxial layer 22 is formed, lateral autodoping of phosphorus and boron is effectively prevented. Note that, after the phosphorus implantation, if the heat treatment is performed for a long time with the oxide film 15 left, the phosphorus component is concentrated in the surface layer portion of the phosphorus implantation layer 20, so that the crystal recovery in FIG. It is desirable to omit the heat treatment and immediately grow the epitaxial layer 22.

  The fourth aspect can also be applied to an epitaxial wafer manufacturing method using a photoresist film as an ion implantation mask. In this case, as shown in FIG. 25A, a boron implantation layer 71 is first formed in the first epitaxial layer 3, and then an oxide film 19 before implantation is formed. Since boron in the boron implantation layer 71 is unlikely to collect at the interface with the pre-implantation oxide film 19 for the same reason as described above, concentration of boron in the surface layer portion does not occur. Next, as shown in (b), an ion implantation mask 60 for forming a phosphorus implantation layer is formed of a photoresist film, and after implantation of phosphorus, as shown in (c), before the ion implantation mask 60 and implantation. The oxide film 19 is removed, and the second epitaxial layer 22 is grown as shown in (d) to obtain a boron buried layer 71 ′ and a phosphorus buried layer 72 ′.

Process explanatory drawing which shows one Example of the manufacturing method of a 1st aspect. Process explanatory drawing following FIG. The process flowchart in the case of forming six buried layers by the process of the said Example. Explanatory drawing which shows the process of performing a hydrogen heat treatment process and a vapor phase growth process continuously in a vapor phase reactor with the cross-sectional structure of a vapor phase reactor. The cross-sectional schematic diagram which shows the characteristic of the embedding layer formed by the manufacturing method of a 1st aspect, and the vertical direction addition area | region formed based on it. The cross-sectional schematic diagram which shows the characteristic of the embedding layer formed by the manufacturing method of the reference technique, and the vertical direction addition area | region formed based on it. The figure which shows typically the cross-section of the epitaxial wafer of this invention which formed the embedding layer in the multilayer. The cross-sectional schematic diagram which shows the example of the vertical direction addition area | region obtained by heat-processing the epitaxial wafer of FIG. Process explanatory drawing which shows the characteristic of a 2nd aspect. The schematic diagram which shows an example of the cross-section of the epitaxial wafer manufactured by the manufacturing method of this invention. The schematic diagram which shows another example similarly. Explanatory drawing showing a mode that surface roughening generate | occur | produces in an ion implantation layer when crystal recovery heat processing is performed, and a mode that this is prevented by the oxidation process before implantation. The figure explaining the effect of hydrogen heat processing. Process explanatory drawing which shows the manufacturing method of the epitaxial wafer of a reference technique (an example of a 4th aspect). Process explanatory drawing following FIG. Process explanatory drawing following FIG. 6 is a process flowchart in the case of forming six buried layers by the process of the reference technique. The figure which shows typically one of the suitable Examples of the positioning solid mark. The schematic diagram which shows the position modification of the positioning solid mark of FIG. Explanatory drawing which shows the suitable angle range of the linear part contained in the positioning solid mark. Explanatory drawing which shows the experimental result which backs up the angle range of FIG. The figure explaining a mode that the conventional positioning solid mark deform | transforms by the growth of an epitaxial layer. The figure explaining the problem of the manufacturing method of the silicon epitaxial wafer using the conventional positioning solid mark. Explanatory drawing of the effect of a 3rd aspect. The figure explaining the summary of the process of the manufacturing method concerning the modification of the 4th mode. The figure explaining the setting aspect of the measurement line of a carrier concentration profile in the effect confirmation experiment of a 3rd aspect. The figure which shows the example of a measurement of the carrier concentration profile. Process explanatory drawing of the manufacturing method of a 6th aspect. Process explanatory drawing of the manufacturing method of a 7th aspect. The figure explaining an example of the effect.

Explanation of symbols

1 Silicon Single Crystal Substrate 3 First Epitaxial Layer 7 Positioning Solid Mark 62 First Ion Implantation Mask 64 Second Ion Implantation Mask 71 Boron Implantation Layer (First Ion Implantation Layer)
72 Phosphorus implantation layer (second ion implantation layer)
22 Second epitaxial layer

Claims (5)

Phosphorus is ion-implanted into the first epitaxial layer to form a plurality of phosphorus-implanted layers aligned in the width direction, and a second epitaxial layer is vapor-grown and stacked thereon to stack the phosphorus-implanted layer into the first epitaxial layer. In the method of manufacturing a silicon epitaxial wafer embedded between one epitaxial layer and the second epitaxial layer to form a phosphorous buried layer,
An ion implantation step of ion-implanting phosphorus into the first epitaxial layer;
A heat treatment step of performing a heat treatment at 950 ° C. or more and less than 1100 ° C. under atmospheric pressure before vapor-phase growth of the second epitaxial layer after the ion implantation step is completed;
A sealing growth step in which after the heat treatment step is completed, a silicon source gas is introduced under a reduced pressure atmosphere, and a sealing epitaxial layer is vapor-phase grown at a pressure of 5 to 60 torr ;
And a main growth step of vapor-phase-growing the second epitaxial layer on the sealing epitaxial layer.   2. The method for producing a silicon epitaxial wafer according to claim 1, wherein the silicon source gas is dichlorosilane, trichlorosilane, or silicon tetrachloride diluted with hydrogen. The sealing growth step, method for producing a silicon epitaxial wafer according to claim 1 or 2 carried out at growth temperature 800 ° C. to 950 ° C..   The method for producing a silicon epitaxial wafer according to claim 1, wherein a formation thickness of the sealing epitaxial layer is 0.2 μm to 1 μm.   5. The silicon according to claim 1, wherein the main growth step is performed at a higher temperature and / or higher pressure than the sealing growth step in the same vapor deposition apparatus following the sealing growth step. Epitaxial wafer manufacturing method.

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