CN1174474C - 在势垒层上淀积铜的方法 - Google Patents
在势垒层上淀积铜的方法 Download PDFInfo
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- CN1174474C CN1174474C CNB011218819A CN01121881A CN1174474C CN 1174474 C CN1174474 C CN 1174474C CN B011218819 A CNB011218819 A CN B011218819A CN 01121881 A CN01121881 A CN 01121881A CN 1174474 C CN1174474 C CN 1174474C
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- copper
- barrier layer
- tungsten
- plating bath
- tantalum
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- 239000010949 copper Substances 0.000 title claims abstract description 69
- 229910052802 copper Inorganic materials 0.000 title claims abstract description 39
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 title claims abstract description 37
- 230000004888 barrier function Effects 0.000 title claims abstract description 32
- 238000000034 method Methods 0.000 title claims description 34
- 238000007747 plating Methods 0.000 claims abstract description 26
- 229910052721 tungsten Inorganic materials 0.000 claims abstract description 26
- 239000010937 tungsten Substances 0.000 claims abstract description 26
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims abstract description 25
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 10
- 239000008139 complexing agent Substances 0.000 claims description 10
- 229910001431 copper ion Inorganic materials 0.000 claims description 10
- 239000013078 crystal Substances 0.000 claims description 10
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- 229960001484 edetic acid Drugs 0.000 claims description 8
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 claims description 8
- 239000003638 chemical reducing agent Substances 0.000 claims description 7
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- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 4
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 4
- 238000007772 electroless plating Methods 0.000 claims description 4
- 229910021332 silicide Inorganic materials 0.000 claims description 4
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 4
- 239000004094 surface-active agent Substances 0.000 claims description 4
- 229910052715 tantalum Inorganic materials 0.000 claims description 4
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 4
- 229910052719 titanium Inorganic materials 0.000 claims description 4
- 239000010936 titanium Substances 0.000 claims description 4
- ROFVEXUMMXZLPA-UHFFFAOYSA-N Bipyridyl Chemical group N1=CC=CC=C1C1=CC=CC=N1 ROFVEXUMMXZLPA-UHFFFAOYSA-N 0.000 claims description 3
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
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- 150000001875 compounds Chemical class 0.000 description 1
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- 239000001257 hydrogen Substances 0.000 description 1
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- 229910010272 inorganic material Inorganic materials 0.000 description 1
- 239000011147 inorganic material Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
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- 229940073020 nitrol Drugs 0.000 description 1
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- 125000001997 phenyl group Chemical group [H]C1=C([H])C([H])=C(*)C([H])=C1[H] 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C18/00—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
- C23C18/16—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, e.g. electroless plating
- C23C18/31—Coating with metals
- C23C18/38—Coating with copper
- C23C18/40—Coating with copper using reducing agents
- C23C18/405—Formaldehyde
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
- H01L21/76874—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroless plating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
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Abstract
本发明涉及到在势垒层或衬垫层上淀积铜的方法,尤其是关于提供共形粘附的铜薄膜。根据本发明的一种淀积铜到势垒层上的方法,该方法包括采用无电镀镀浴直接淀积铜到势垒层上,其中在所述势垒层和所述淀积的铜层之间不存在籽晶层,所述镀浴包含铜离子源、还原剂和络合剂,并且有至少为12.89的pH值以及50nm/min或更低的淀积速率。
Description
技术领域
本发明涉及到在势垒层或衬垫层上淀积铜,尤其是关于提供共形粘附的铜薄膜。
本发明尤其适用于甚大规模集成电路(VLSI)和超大规模集成电路(ULSI)金属互连、接柱、半导体芯片上的CMOS门堆以及封装和显示源中的电互连。
本发明对在高形状比/沟槽结构中(深度/宽度>3∶1)尤其具有优势。
背景技术
Al(Cu)及其相关合金对在诸如集成电路芯片的电子器件上形成互连来说是优选的合金。Al(Cu)中Cu的典型数量范围在0.3-4%之间。
用Cu和Cu合金取代AL(Cu)作为芯片互连材料,在性能上具有优势。性能得到提高是因为Cu和某些铜合金的电阻率比Al(Cu)的电阻率低,所以能够使用更窄的引线和实现更高的布线密度。
在制造高性能互连结构时,Cu导线材料必须镶嵌在具有沟槽或通道形成于其中的电介质材料中。电介质材料可以包含有机材料和无机材料,或它们的组合。这种材料的例子包含聚酰亚胺、聚对二甲苯聚合物、聚亚芳基醚聚合物、类金刚石碳、包含不同量碳、硅、氧和氢的材料、聚硅氧烷、SiO2和Si3N4。这样的材料可以是致密的或多孔的。
当Cu是这些应用中的被选导体时,它有一个重要的不希望有的与电介质基体相互作用的特性。铜一般地在后续处理中遇到中等升高的温度时,会扩散通过电介质材料。这会有许多破坏性的结果,包含线路的可能短路或它们所连接的MOS器件性能的退化。为了避免这些效应,因此需要在结构中并入扩散势垒,把Cu与电介质材料隔离开来。
在建议作为势垒材料的材料中,有钨(W)及其合金、钛、钛合金、氮化钛、钽、钽合金、氮化钽和氮硅化钽。
然而,用来制造铜线的诸如电镀、蒸发、或溶液无电镀淀积的多种镀层方法,导致扩散势垒和铜线之间粘附很差。结果,这样制造的结构缺乏经受住诸如化学-机械抛光(CMP)那样的后续处理步骤而不导致灾难性结构毁坏所必需的牢固性。
作为上述粘附问题的结果,发现在实际中需要在两个不同的步骤中淀积包含引线的Cu。第一步是镀上扩散势垒,它有一个薄的Cu层,典型地为几百埃厚。在目前的实际应用中,这个称为籽晶层的层由溅射来淀积,它是到目前为止所发现的唯一能够在Cu和任何用作扩散势垒的材料之间提供良好粘附的方法。一旦籽晶层就位,包含引线的Cu的其余部分就可以用很多方法来淀积,诸如CVD或电镀,因为体引线Cu和籽晶层Cu之间的粘附不成问题。由于多种原因,需要两个步骤,因为通过溅射淀积制造整个导线是不实际的。
迄今用溅射淀积制造籽晶层的必要性导致第二个主要的问题。这就是共形性问题,目前实际的以及将来不断增加的高性能布线结构会包含电介质中高形状比的沟槽。形状比被定义为沟槽的深度和宽度之比,高的形状比是指3∶1或更大的比率。溅射淀积本质上是共形性很差的工艺,因此很难在沟槽的侧壁上实现籽晶层的足够覆盖。这是不希望的,因为它使结构变差。尽管溅射淀积工艺可以通过本技术领域的熟练人员所熟知的方法加以“调整”和修正以便优化共形度,但这本身涉及到复杂的成本高的设备,还不清楚能否推广以满足可以预见的需要。
因此,非常希望能够有一种成本低的固有共形的方法来制造籽晶层以取代溅射淀积。
在CVD钨扩散势垒上淀积一种特殊的无电镀铜的建议可以在Maket al,Electrochemical Society Proceedings,Vol.93-20,1993,Romankiw et al(Eds.),p.233中找到。钨的化学汽相淀积(CVD)由使用WF6做钨源的选择性钨工艺实现。在这个工艺中,W只是选择性地淀积在图形化于二氧化硅中暴露的Si通道和沟槽的底部,但不淀积在二氧化硅(SiO2)上。接着,无电镀的铜选择性地淀积在钨的表面上。图1示意性显示了由选择性钨-无电镀铜工艺制造的Cu互连的表示。从图1可以看到,根据这种工艺的Cu互连只在互连的底部有扩散势垒。因此只有Cu到Si的扩散被阻挡了。然而,Cu原子扩散可以不但来源于互连底部,也来源于互连的侧面或顶部。Cu从侧面进入SiO2的扩散,使SiO2绝缘体退化并导致缺陷。因此,这个工艺的产品并不令人满意。
在另外一种技术中,硅被注入在SiO2沟槽的底部,然后CVD W被选择性地淀积在注入的硅上。无电镀的铜被选择性地淀积在钨上以产生Cu互连(Angyal et al,Electrochemical Society ExtendedAbstracts,93-1,1993,p465)。在这个与前面相似的工艺中,Cu扩散只是在底部而不是在侧面被阻挡,Cu可以轻而易举地扩散进入SiO2绝缘体。因此,此工艺也不能令人满意。图2示意地显示了Si籽晶层注入工艺的表示。
因此,提供一种能够制造集成电路的完全被包封的铜互连,也是可取的。
发明内容
本发明使通过相对低成本和简单的方法共形地淀积籽晶层成为可能。
已经发现,根据本发明,铜可以从某种无电镀的淀积镀浴中淀积。因为无电镀淀积不涉及到外部电势的使用和不具有任何其他的外部规定空间中单一轴的特征(诸如溅射中离子束的传播方向),故它本质上是一种共形的工艺,解决了共形性问题。本发明也解决了粘附问题,粘附问题迄今阻碍通过使用具有某种特性的组分而为这个目的使用无电镀淀积。
本发明提供了一种淀积铜到势垒层上的方法,该方法包括采用无电镀镀浴直接淀积铜到势垒层上,其中在所述势垒层和所述淀积的铜层之间不存在籽晶层,所述镀浴包含铜离子源、还原剂和络合剂,并且有至少为12.89的pH值以及50nm/min或更低的淀积速率。
对于本技术领域的熟练人员,从下面的详细描述中会容易地明白本发明的又一个目的和优势,其中,简单地通过考虑实施本发明的最好模式的阐述,显示和描述了本发明的优选实施方案。如可理解的那样,本发明能够有其他的不同的实施方案,且它的一些细节能够在多个明显的方面进行修改而不脱离本发明。因此,描述在本质上被认为是阐述性的而不是限制性的。
附图说明
图1和2是现有技术结构例子的剖面图。
图3和4是根据本发明的结构的剖面图。
具体实施方式
为了方便对本发明的理解,可以参考下面的图。
本发明涉及到半导体器件的互连结构,具体涉及位于电介质基体沟槽中的包含Cu互连线的结构,其特征是在Cu和电介质之间的衬垫或势垒。本发明提供了一种在势垒层上共形地制造铜粘附层的方法,以便能够通过诸如电镀或化学汽相淀积(CVD)的多种方法来制造Cu导线本体,或在单一步骤中制造整个Cu导线本体。
本发明可应用于任何结合电介质基体中的势垒层使用铜导线的互连结构的制造中。这包含但并不局限于镶嵌结构、存储单元电容器、和所有其他逻辑布线应用、储存器和输入/输出应用。这种方法也可以广泛地应用在任何需要在势垒金属上淀积一层薄Cu粘附层而没有中间层的应用中,尤其是在那些考虑共形性和在10nm-100nm并优选地在20nm-50nm范围内精确控制厚度的例子中。
根据本发明,发现为了实现在势垒层和铜之间有足够粘附性和可控厚度的共形镀层,应该使用pH值至少为12.89且镀敷速率为50nm/min或更低的无电镀镀浴。
更具体而言,铜无电镀水镀浴包含铜离子源、铜离子的还原剂、铜离子的络合剂和pH调节剂。镀浴也能包含可选的组分诸如稳定剂、表面活化剂和氰离子。
镀浴通常包含约0.015M(摩尔)到约0.20M,更典型为约0.05M到约0.10M的铜离子源。
还原剂的典型量约为0.01M到约0.2M,更典型地约为0.01M到约0.1M。
络合剂的典型量约为0.02M到约0.3M,更典型地约为0.1M到约0.2M。
如果有的话,稳定剂的典型量约为1μM到约50μM,更典型地约为5μM到约20μM。
如果采用的话,氰离子的典型量约为1mg/L到约200mg/L,更典型地约为5mg/L到约50mg/L。
如果有的话,表面活化剂的典型量约为0.1mg/L到约500mg/L,更典型地约为2mg/L到约300mg/L。
通常使用的铜离子源是硫酸铜(即CuSO4·5H2O)或采用络合剂的铜盐。
其他一些还原剂的例子包含诸如多聚甲醛、三氧环己烷、二甲基乙内酰脲、乙二醛、乙二醛酸之类的甲醛的产物母体或衍生物;诸如碱金属氢硼化物(钠和钾氢硼化物)之类的氢硼化物和诸如钠三甲氧基氢硼化物之类的替位硼氢化物;诸如胺硼烷(异丙基胺硼烷和吗琳硼烷)和次磷酸盐之类的硼烷。
某些合适的络合剂的例子包含罗谢尔盐、乙二胺四乙酸、乙二胺四乙酸的钠盐(单,二,三,和四-钠)、硝脑四乙酸及其碱金属盐、葡萄糖酸、葡萄糖酸盐、三羟乙基胺、葡萄糖(伽玛)-内酯、诸如N-羟乙基的改良乙二胺乙酸和乙二胺三乙酸。而且,在美国专利第2996408、3075856、3075855和2938805中建议了很多种其他合适的铜络合剂。络合剂的数量取决于溶液中的铜离子数量。
pH调节剂可以是诸如氢氧化钠、氢氧化钾或氢氧化四乙铵之类的碱性化合物。
根据本发明可采用的一些氰化物例子是碱金属、碱稀土元素、和铵的氰化物。此外,镀浴可以包含本技术领域内熟知的其他少量附加物。
优选的铜离子源是CuSO4·5H2O。
合适的络合剂的特殊例子是乙二胺四乙酸(EDTA)或它的盐。
还原剂的特殊例子是甲醛。
合适的稳定剂是2,2’-联吡啶。
表面活化剂的一个特例是Triton X-114(异辛基苯基聚乙二醇醚)。
优选的pH调节剂是氢氧化钠。
上面所讨论的图1阐述了先前建议的结构,其中钨3通过化学汽相淀积只淀积在暴露的Si 1的沟槽4的底部。钨3没有阻挡Cu 5扩散进诸如SiO2的电介质2。
上面所讨论的图2阐述了另外一种先前建议的结构,其中硅6被注入到被图形化于二氧化硅2中的沟槽4的底部。CVD淀积的钨3被选择性地淀积在注入的硅6上。钨3没有阻挡Cu 5扩散进SiO2电介质2。
图3阐述了根据本发明的一种结构,其中势垒层3被淀积在诸如二氧化硅的绝缘体2中的沟槽、通道或接触孔的底部和侧壁上。一些势垒层的例子是钨、钨合金、钛、钛合金、氮化钛、钽、钽合金、氮化钽、氮硅化钽,钨是优选的势垒层。
钨可以通过使用W(CO)6做钨源的CVD来淀积。该工艺能够在本底压力约为10-9torr的超高真空中,在典型的淀积温度约350℃到约500℃,更加典型的是约380℃到约400℃下进行。反应气体的分压典型的是约1到约100mtorr,更加典型的是约5-20mtorr。可以采用诸如使用卤化钨产物母体蒸发或溅射淀积的CVD的对钨基本上共形的非选择性淀积的其它方法。层3典型为至少4nm,更加典型为约5nm到约40nm,而最好是约为5nm到约10nm。
然后使用根据本发明的镀浴,将铜5选择性地淀积在势垒层上。见图4。
下面的非限制性例子用来进一步阐述本发明。
例1
在包含硅片上图形化SiO2的衬底上覆盖钨。使用产物母体W(CO)6,用化学汽相淀积(CVD)方法来淀积钨。在不锈钢高真空系统反应器内进行淀积,本底压力约为1×10-9torr,温度约为380-400℃。W(CO)6的分压约为10mtorr。钨层约为20nm厚。
然后pH值为12.89的无电镀铜镀浴中选择性地将铜覆盖在钨上,该镀浴包含:
CuSO4·5H2O 12.5g/L
Na2EDTA 37.2g/L(EDTA即乙二胺四乙酸)
2,2’-1联吡啶 0.015-0.0156g/L
Triton X-114 0.10-0.30mL/L(Triton X-114:异辛基
苯基聚乙二醇醚)
CH2O 6.0mL/L(甲醛,37%溶液)
H2O 到1L
NaOH 到提供pH值12.89
电镀是在镀浴温度约为60℃时进行。镀覆速率约为50nm/min,能够精确地控制镀层厚度。铜表现良好的粘附特性。
比较例2
除了铜镀浴的pH值为12.17以外,重复例1。淀积了连续和光泽的Cu薄膜,但是Cu和W衬底之间的粘附非常差。
比较例3
除了铜镀浴的pH值小于12.17以外,重复例1。没有铜淀积。
比较例4
除了镀浴为pH值是13.0-13.2的LeaRonal Coppermerse 80溶液以外,重复例1,这是一种商用镀浴。该镀浴的淀积速率超过200nm/min,这对于在典型的晶片上粘附可控厚度来说是太高了。尽管铜淀积产生粘附覆盖层,但该例因为它的淀积速率而并不适用。
例5
除了在LeaRonal Coppermerse 80溶液中加入氰化钠以外,重复比较例4。这通过在铜镀浴中加入5ml/L的LeaRonal“Compomemt 80p”溶液(一种标准的氰化钠溶液)而实现。这样成功地把淀积速率降低到50nm/min。铜淀积物是粘附涂层,适合本发明。
前面关于本发明的描述阐述和描述了本发明。而且,公开的内容只是显示和描述了本发明的优选实施方案,但是,正如上面所提到的,应该明白本发明能够用在各种其它的组合、修正、和环境中,并能够在如本文中所表达的本发明概念范围内进行改动或修改,这是与相关技术领域相称的。上面所描述的实施方案能够进一步用来解释实施本发明的众所周知的最佳模式,能够用来使本技术领域中的其他熟练人员以这样的或其他的实施方案和由本发明的应用或使用所需的多种修正来使用本发明。因此,此描述不是用来把本发明限制于本文所公开的形式的。所附权利要求也是打算用来包含其它的实施方案。
Claims (18)
1.一种淀积铜到势垒层上的方法,该方法包括采用无电镀镀浴直接淀积铜到势垒层上,其中在所述势垒层和所述淀积的铜层之间不存在籽晶层,所述镀浴包含铜离子源、还原剂和络合剂,并且有至少为12.89的pH值以及50nm/min或更低的淀积速率。
2.权利要求1的方法,其特征在于,其中淀积厚度为10nm到100nm的铜。
3.权利要求1的方法,其特征在于,其中淀积厚度20nm到50nm的铜。
4.权利要求1的方法,其特征在于,其中势垒层位于镶嵌在电介质中的沟槽或通道的底部和侧壁上。
5.权利要求4的方法,其特征在于,其中势垒层选自钨、钨合金、钛、钛合金、氮化钛、钽、氮化钽和氮硅化钽。
6.权利要求5的方法,其特征在于,其中势垒层至少为4nm厚。
7.权利要求4的方法,其特征在于,其中势垒层是钨。
8.权利要求4的方法,其特征在于,其中电介质是二氧化硅。
9.权利要求1的方法,其特征在于,其中势垒层选自钨、钨合金、钛、钛合金、氮化钛、钽、氮化钽和氮硅化钽。
10.权利要求1的方法,其特征在于,其中势垒层至少为4nm厚。
11.权利要求1的方法,其特征在于,其中势垒层是钨。
12.权利要求4的方法,其特征在于,其中沟槽或通道的深度与宽度之比大于3∶1。
13.权利要求1的方法,其特征在于,其中镀浴的温度为60℃。
14.权利要求1的方法,其特征在于,其中铜离子源是CuSO4,还原剂是甲醛,络合剂是乙二胺四乙酸或它的盐。
15.权利要求14的方法,其特征在于,其中镀浴包含氢氧化钠。
16.权利要求1的方法,其特征在于,其中镀浴还包含稳定剂和表面活化剂。
17.权利要求16的方法,其特征在于,其中稳定剂是2,2’-联吡啶。
18.权利要求1的方法,其特征在于,其中镀浴还包含氰化物离子。
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JP2011154380A (ja) * | 2003-03-20 | 2011-08-11 | Toshiba Mobile Display Co Ltd | 表示装置の形成方法 |
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US6284652B1 (en) * | 1998-07-01 | 2001-09-04 | Advanced Technology Materials, Inc. | Adhesion promotion method for electro-chemical copper metallization in IC applications |
US6221763B1 (en) * | 1999-04-05 | 2001-04-24 | Micron Technology, Inc. | Method of forming a metal seed layer for subsequent plating |
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- 2001-06-28 CN CNB011218819A patent/CN1174474C/zh not_active Expired - Fee Related
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JP2002075913A (ja) | 2002-03-15 |
KR100449223B1 (ko) | 2004-09-18 |
KR20020004826A (ko) | 2002-01-16 |
US6416812B1 (en) | 2002-07-09 |
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