CN1173803A - 带埋置式去耦电容的印刷电路板及其制造方法 - Google Patents

带埋置式去耦电容的印刷电路板及其制造方法 Download PDF

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CN1173803A
CN1173803A CN97113438A CN97113438A CN1173803A CN 1173803 A CN1173803 A CN 1173803A CN 97113438 A CN97113438 A CN 97113438A CN 97113438 A CN97113438 A CN 97113438A CN 1173803 A CN1173803 A CN 1173803A
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J·M·劳弗
K·帕帕托马斯
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Abstract

一种制造埋置在电子电路组件中的电容器的方法,包括下列步骤:选择第一导电薄片;选择介电材料;将介电材料被覆到第一导电薄片的至少一面上;再将被覆过的薄片连同第二导电薄片分别堆制在介电材料的被覆层上面。本发明还涉及装有至少一个按本发明制取的埋置式电容器的电子电路组件。

Description

带埋置式去耦电容的印刷电路板及其制造方法
本发明涉及一种带埋置式去耦电容的印刷电路板及其制造方法。更具体地说，本发明涉及一种将被覆有介电材料、预选钻好孔或预先蚀刻好的导电薄片成多层堆置制成的因而集成去耦电容极高的印刷电路板。预钻好孔或预蚀刻好的导电薄片呈电压层或接地层的形式。被覆上介电材料之后，各薄片堆置起来，使电压层和接地层交替堆置。接着将交替堆置体与其它信号层层压在一起，形成所要求的多层电路板。
电子电路通常都含有许多(有时是数百个)元件，例如电阻器、电容器、电感器、二极管、机电开关和晶体管等。电子元件的高密度封装对大量数据能否在计算机中快速存取是非常重要的。高密度电子电路组件在高频设备和通信设备中也很重要。各元件连接成电路，各电路连接成功能器件。这些接线起分配电能和分配信号的作用。在多层电子电路组件中，组件中有些层用作电源层，其它组件层用作信号层，这视乎器件的工作要求而定。这些器件既要有一定的机械强度，在结构上又要有一定的保护措施。各电路本身需要有电源才能工作。但无论怎么说，功能器件会产生热量或热能，这些热量或热能都必须散除，器件才不致停止工作。此外，虽然大量元件的高密度封装能提高器件的性能，但耗电元件所产生的热量对器件的性能和可靠性有有害的影响。这种有害影响起因于由象电阻率增高之类的电气问题和象热量增加引起的热应力之类的机械问题。
高密度封装必然提高多层电子电路组件中布线的密度，减小各层之间介电被覆层的厚度。多层组件中的各层是用通路孔和通孔电连接的。这里“通路孔”一词是指多层电子电路组件中毗邻的各层之间的导电通路。“通孔”一词是指延伸到非毗邻层的导电通路。高密度组件的通孔，直径越来越小，且各层的各通孔必须精确对齐。
因此，象芯片、模件、电路卡、电路板以及这些元件的组合件之类的电子电路组件，要达到最佳的工作性能就必须满足一系列要求。组件的结构必须牢固，足以支撑和保护各元件和布线。此外，组件一定要能够散热，其热膨系数一定要和元件的相称。最后，要能在市面上有市场，组件就应该生产成本低，易于制造。
电子电路组件通常既可用在数字电路又可用在模拟电路，但用得最多的还是数字电路。在数字电路中，一个电压离散值附近的小范围对应于逻辑“0”，另一电压离散值附近的另一小范围对应于逻辑“1”。具有这些性能的信号为“数字信号”。数字信息处理与这些数字信号的传输、存储和应用有关。
在数字信息处理过程中，信号从一种二进制值变为另一种二进制值。这个转变在理想情况下是以“阶跃函数”的形式传输的。但这个理想的阶跃函数因传输线路和组件中其它传输线路上电阻、电容、电感和传输线路的作用而畸变。此外，这个阶跃函数，无论是理想的抑或畸变的，还会引起其它畸变和寄生信号(即噪声)和在电路组件中的其它线路上的感应信号。因此需要将噪声从数字电路中滤除。
可以通过设置RC时间常数和带通特性适当的内部RC滤波电路在数字电路组件中进行噪声的滤除，从而将信号线路与例如电源线路、接地线路或其它信号线路电容性耦合或去耦合。
大家知道，现有技术中尝试过提供埋置的去耦电容。举例说，颁发给Lauffer等人的美国专利No.5,027,523中提出的集成埋置电容器，其第一电极通过一根导线与第一信号芯层相连接，其第二电极通过一根导线与第二信号芯层相连接。第二电极至少一部分与第一电极重叠，但由一介电材料薄膜将两电极分隔开。这两个电极和介电材料薄膜形成整体的埋置式电容器。
颁发给Lucas(“lucas”)的美国专利5,261,153提供了一种在印刷电路板内形成电容元件的方法。Lucas公开了在未经处理的介电片材两侧层压上导电薄片，再装入印刷电路板中作为电路板中的一个板层的作法。
Lucas的方法是通过逐一蚀刻各薄片上绘有线路图形的光刻胶材料而形成间隙孔的。本发明可以将多个薄片堆置在一起，同时钻孔或冲孔，因而降低了组件的造价。此外，Lucas的方法由于沿薄介电材料的玻璃纤维镀上了树枝状铜，因而各层之间容易短路，很不可靠。本发明非玻璃的介电材料则不含任何规定的树枝状铜的通路。
本发明的一个目的是提供一种带去耦接地和电源母线因而可以妥善起开关控制作用(stimulus)的印刷电路板。
本发明的另一个目的是提供一种去耦电容值极高的印刷电路板。
本发明的第三个目的提供一种制造带集成去耦电容的印刷电路板的方法。
因此，本发明提供的制造待埋置在电子电路组件中的电容器的方法包括下列步骤：选择第一导电薄片；选择介电材料；将介电材料被覆到第一导电薄片的至少一面上；再将经被覆的薄片连同第二导电薄片分层层叠在介电材料的被覆层上。此外，本发明还涉及装有至少一个按本发明制造的埋置式电容器的电子电路组件。
本发明的好处在于，提供的电容器是埋置在电子电路组件中的，因而可以少装或无需表面安装式电容。
本发明的另一个好处是，提供的埋置式电容器对接地母线和电源母线起去耦合作用，从而使开关控制作用得以正确发挥。
本发明的再一个好处是，埋置式电容器的采用使印刷电路板的去耦电容值非常高。
从下面结合附图和实例对本发明的最佳实施例进行的详细说明可以清楚了解本发明的其它特点和优点。
图1是本发明多层印刷电路板的一个单层的示意图。
图2是本发明多层印刷电路板一个单层的另一个实施例的示意图。
本发明涉及一种带埋置式去耦电容的印刷电路板及其制造方法。本发明制造集成去耦电容值极高的印刷电路板的方法是将多个预先钻好孔或预先蚀刻好被覆有介电电材料的导电薄片多层叠置在印刷电路内的。预先钻好孔或预先蚀刻好的导电薄片形成电压层或接地层。被覆上介电材料之后，这些导电薄片交替埋置起来(即电压层/接地层/电压层)，再与其它信号层层压在一起，制成多层印刷电路板成品。
在本发明的最佳实施例中，导电薄片是铜质的。其它适用的导电薄片还有：铜-因瓦铁镍合金-铜，因瓦铁镍合金，铝和铜，但并不局限于这些。这些都预先层压到介电材料上。
介电被覆层可以是由以下物质组成的任何类型的介电材料，例如标准的液体环氧树脂，聚酰亚胺，聚四氟乙烯，氰酸酯树脂、树脂粉料或介电常数大的填料树脂系统。介电材料被覆到导电薄片上可采用工业上周知的许多方法进行，例如，滚筒、拉延、粉料或料帘被覆法，静电或电泳淀积法，丝网印刷法，喷涂法，浸渍法或干膜转移法等。这些被覆方法形成均匀的薄膜(0.0001英寸～0.003英寸厚)。一经多层层压，这些被覆膜的厚度就不受玻璃布料的限制了。
下面就两个实例进一步说明本发明的内容。第一实例采用高级焊接式掩模(ASM)干膜形成本发明带集成堆置式电容的复合多层印刷电路板。一般的信号-信号芯层和信号-电压芯层通过层压和电路化而制成。这些经电路化的芯层要经过氧化铜处理以提高复合层压层的粘合性。此外，本发明的薄铜片/介质构件按下列步骤进行预加工：
1.在三片1盎司双处理过的薄铜片上冲压出工艺孔对正槽口。
2.在三铜片上钻孔。将上下两个堆置片堆置在钻床上，钻成接地层间隙孔的图形。第三铜片钻成电压层间隙图形，供在多层印刷电路板的中心使用。
3.介电材料选用0.002英寸厚带聚酯薄膜载片的ASM干膜。将介电材料热轧层压到上接地层铜薄片的顶面、下接地层铜薄片的底面和中间电压层薄铜片的两面上。
4.剥除所有ASM被覆层上的聚酯薄膜载片，再将薄铜片/ASM构件放入150℃的烘炉中历时30分钟。以除去ASM中的溶剂。
5.接着将这些薄铜片/ASM构件连同预制的芯件、玻璃布和外铜薄片埋置在对正销子上，再在190℃和500磅/平方英寸的压力下对堆置体进行真空层压处理，获得复合多层板成品。接着对复合板进行一般的钻孔、镀敷和外电路化加工，于是得出有四层彼此平行的电容层的电路板成品。
经干燥和层压之后电路板成品每层总的ASM厚度为0.001英寸。板的介电常数为3.5。得出的板电容值为每平方英寸板面积3.2纳法。
图1示出了按实例1所述制作的印刷电路板。图1中，钻了孔的三个铜片的编号分别为10、12和14。铜片10和14钻成接地层间隙孔图形。铜片12钻成电压层间隙孔图形。接着将一片ASM干膜16层压到铜片10的顶部表面。ASM干膜18和20分别层压在铜片12部和底部表面。ASM干膜片22层压到铜片14的底部表面。接着按上述方式处理这些铜片/ASM干膜构件，然后如图1所示那样堆置。从图1还可以看到两个电路处理过的芯层24和26。电路化处理过的芯层24的顶部表面为信号层28，底部表面为经蚀刻的薄铜片30。薄铜片30蚀刻成电压图形。两个环氧树脂玻璃层36和38和薄铜片40和42将整个印刷电路板的顶部和底部外表面封闭住。
图1中，四层彼此平行的电容层的编号分别为44、46、48和50。各电容层的两导电金属(铜)片之间为介电材料。
在第二实例中，采用重量为85％的BaTiO3粒状/多功能环氧树脂系统制作带整体埋置式电容的复合电路板构件。印刷电路板的制造过程如下：
1.按一般层压和减(subtractive)蚀刻法制取信号-电压和信号-信号芯层。
2.将粒度小于5微米的BaTiO3粉料按重量85％的混合比与多功能环氧树脂混合。往混合料中加入甲基乙基酮(“MEK”)溶剂以促进混合作用并使被覆料达到合适的粘度。
3.将树脂填料系统在第一芯层的底部(电压)表面和第二芯层的顶部(电压)表面轧压被覆成大约0.0015英寸的厚度。被覆之后，将芯层在140℃的烘炉中干燥五分钟，以除去任何残留的甲基乙基酮。
4.在1盎司双处理过的薄铜片上钻孔，钻成接地层间隙孔图形。
5.接着将两个被覆过的芯层和钻好孔的薄铜片与其它预制的芯层堆置起来，然后在188℃温度500磅/平方英寸的压力下层压90分钟，于是形成带整体埋置式电容层的多层层压件。
所获得的构件有两个平行的电容层。构件厚0.001英寸，介电常数40，每平方英寸板面积的电容值为18纳法。
图2示出了按实例2制作的印刷电路板。图2中，两芯层的编号为52和54。芯层52的顶部表面上有信号层56，底部表面上有经蚀刻的电压层58。芯层54的顶部有经蚀刻的铜电压层60，底部有信号层62。两个经蚀刻的铜电压层58和60被覆有介电材料，分别形成被覆层64和66。介电材料和上面所述的一样为BaTiO3粉料、多功能环氧树脂和MEK溶剂组成的树脂填料系统。介电材料用轧制被覆法敷上。介电材料层64和66之间为钻成接地层间隙孔图形的双处理过的薄铜片68。印刷电路板的外表面由两个环氧树脂玻璃层70、72和薄铜片74和76构成。
图2的印刷电路板有两层彼此平行的电容层78，80。
上述实例仅仅是举例说明本发明用途的两个制造过程和得出的集成电容构件。显然，本发明技术领域的技术人员都知道，实施本发明的方法和改型可能很多，其中包括下面所述但不局限于下列方案：
1.处理大量的印刷电路板时，薄铜片可以用卷装进出方法(roll toroll process)被覆上介电材料。同样，薄铜片上的间隙孔也可以在被覆介电材料之前或之后通过顺次分批冲出对正孔和间隙孔成卷制取。薄铜片的铺设是在完成被覆和穿孔工序之后进行的。
2.介电被覆层不是只被覆在薄铜片的一面而是被覆在薄铜片的两面，这项技术可以最大限度地减少介电层穿孔的可能性，同时不致使介电层的总厚度大幅度增加。
3.有被覆层的薄铜片可按任意数目堆置以达到所要求的电容值。
4.有被覆层的薄片可以顺次堆置或在整个横截面上交错堆置以形成通常叫做三板结构的构件。无论是顺次堆置抑或交错堆置，所有各层都与成品构件中的镀敷的通孔并联容性耦合。
5.在未改型或介电常数提高的系统中，介电被覆层可包括环氧树脂、聚酰亚胺、聚四氟乙烯、氰酸酯、环氧树脂-丙烯酸酯焊接掩模等。
6.虽然铜是较理想的印刷电路板导电材料，但也可以采用诸如铝、因瓦铁镍合金等和它们的组合之类的任何导电材料。
上面为举例说明起见对本发明的一些具体实施例和实例进行了说明，但在不脱离本发明精神实质或范围的前提下是可以对上述实施例进行种种修改的。

Claims (23)

1.一种制造埋置在电子电路组件中的电容器的方法，其特征在于，它包括下列步骤：
选择第一导电薄片；
在第一导电薄片上限定间隙孔；
选择介电材料；
将介电材料被覆到第一导电薄片的至少一面上；和
将被覆过的薄片与第二导电薄片分层堆置，介电材料的被覆层上面开有间隙孔。
2.如权利要求1所述的方法，其特征在于，第一导电薄片和第二导电薄片是铜材。
3.如权利要求1所述的方法，其特征在于，介电材料被覆到第一导电薄片上的步骤还包括下列步骤：
介电材料的敷设是通过滚筒、拉延、粉料或料帘被覆法，静电或电泳淀积法，丝网印刷法，喷涂法，浸渍法或干膜转移法等进行的。
4.如权利要求1所述的方法，其特征在于，被覆在第一导电薄片上的介电材料层厚0.0001英寸～0.003英寸。
5.如权利要求1所述的方法，其特征在于，第一导电薄片的两面都被覆上介电材料。
6.如权利要求1所述的方法，其特征在于，第二导电薄片的至少一面被覆有介电材料。
7.如权利要求1所述的方法，其特征在于，第一和第二导电薄片上的间隙孔是钻出来的。
8.如权利要求1所述的方法，其特征在于，第一和第二导电薄片上的间隙孔是蚀刻出来的。
9.如权利要求1所述的方法，其特征在于，第一和第二导电薄片上的间隙孔是冲出来的。
10.一种电子电路组件，其特征在于，它包括第一芯层和第二芯层，各自通过层压和电路化而制作；和
一个或多个埋置式电容器，分插在第一芯层与第二芯层之间；
各埋置式电容器包括：
第一导电薄片，至少其一面被覆有介电材料；和
第二导电薄片，在第一导电薄片上的介电材料被覆层顶面。
11.如权利要求10所述的电子电路组件，其特征在于，第二导电薄片的至少一面被覆有介电材料。
12.如权利要求10所述的电子电路组件，其特征在于，第一导电薄片的两面都被覆有介电材料。
13.一种制造埋置在电子电路组件中的电容器的方法，其特征在于，它包括下列步骤：
选择第一导电薄片；
在第一导电薄片上限定间隙孔；
选择由粒状及多功能环氧树脂母料组件的介电材料；
将介电材料被覆到第一导电薄片的第一电压侧上和第二导电材料的第二电压侧上；
在接地层经处理的第三导电薄层上钻间隙孔图形；
将被覆过的第一导电薄层和被覆过的第二导电薄层连同钻好孔的第三导电薄片与其它预制的芯层堆置在一起；
将堆置体层压起来。
14.如权利要求13所述的方法，其特征在于，第一导电薄片和第二导电薄片是铜制成的。
15.如权利要求13所述的方法，其特征在于，介电材料的铺设厚度约为0.0015英寸。
16.如权利要求13所述的方法，其特征在于，被覆过的第一导电薄片和被覆过的第二导电薄片在被覆之后和堆置层压之前在烘炉中在大约140℃下干燥5分钟左右。
17.如权利要求13所述的方法，其特征在于，钻孔的第三导电薄片由铜制成。
18.如权利要求13所述的方法，其特征在于，介电材料选自由聚四氟乙烯、氰酸酯、BT环氧树脂和聚酰亚胺组成的材料组。
19.一种印刷电路板，其特征在于，它包括：
第一芯层和第二芯层，各自通过层压和电路化而制成；
第一导电薄片；
第二导电薄片；
介电材料，被覆在各第一导电薄片和第二导电薄片的至少一面；和
第三导电薄片，钻成接地层间隙孔的形式。
20.如权利要求19所述的印刷电路板，其特征在于，第一层电薄片和第二导电薄片都由铜制成。
21.如权利要求19所述的印刷电路板，其特征在于，介电材料的铺设厚度约为0.0015英寸。
22.如权利要求19所述的印刷电路板，其特征在于，钻孔的第三导电薄片由铜制成。
23.如权利要求19所述的印刷电路板，其特征在于，介电材料选自由聚四氟乙烯、氰酸酯、BT环氧树脂和聚酰亚胺组成的材料组。
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CN1856218B (zh) * 2005-04-28 2010-05-12 三星电机株式会社 具有使用杂化材料的嵌入式电容器的印刷电路板及其制造方法
CN101207104B (zh) * 2006-12-19 2011-08-24 成都锐华光电技术有限责任公司 埋入式电容超低电感设计

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DE69715523T2 (de) 2003-05-28
DE69715523D1 (de) 2002-10-24
JPH1056249A (ja) 1998-02-24
TW330370B (en) 1998-04-21
KR980006256A (ko) 1998-03-30
MY117854A (en) 2004-08-30
EP0813355A2 (en) 1997-12-17
US6256850B1 (en) 2001-07-10
JP3400677B2 (ja) 2003-04-28
US5796587A (en) 1998-08-18
EP0813355B1 (en) 2002-09-18
KR100247717B1 (ko) 2000-03-15
CN1105484C (zh) 2003-04-09
EP0813355A3 (en) 1999-04-14

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