CN117043941A - 具有多个顶侧连接的双侧芯片堆叠组合件 - Google Patents

具有多个顶侧连接的双侧芯片堆叠组合件 Download PDF

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Publication number
CN117043941A
CN117043941A CN202180092825.9A CN202180092825A CN117043941A CN 117043941 A CN117043941 A CN 117043941A CN 202180092825 A CN202180092825 A CN 202180092825A CN 117043941 A CN117043941 A CN 117043941A
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Prior art keywords
assembly
chip
connector
top side
chip stack
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CN202180092825.9A
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Inventor
A·巴拉
F·A·苏达里奥
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United Silicon Carbide Inc
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United Silicon Carbide Inc
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Publication of CN117043941A publication Critical patent/CN117043941A/zh
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  • Testing Of Individual Semiconductor Devices (AREA)

Abstract

芯片堆叠组合件使用单块金属多层连接器来接合芯片的顶侧上的不同高度处的连接，且在所述组合件的顶部顶部上提供较大稳固的连接表面。多个多层连接器能够用于提供多个顶侧连接，例如在共源共栅芯片堆叠组合件中提供多栅极、电流感测和/或开尔文连接中的一个或多个。

Description

具有多个顶侧连接的双侧芯片堆叠组合件
相关申请交叉引用
本申请要求2021年2月22日提交的名称为“双侧芯片堆叠组合件”的美国专利申请第17/181,018号的权益，所述专利申请的内容特此以引用的方式并入本文中。
背景技术
本申请涉及半导体芯片堆叠组合件，包含例如用由硅、碳化硅和其它材料构成的半导体装置制成的高电压和高电流组合件的封装。
发明内容
可使用插入件和/或多层引线框架夹制造双侧芯片堆叠组合件以实现顶侧连接的平坦化。此类插入件和多层夹可提供与大接合线(例如，铜接合线)相容的大接合区域，以提供更好的接合、更好的导电和更好的热传导。替代地，插入件和/或多层夹可用于形成模制的双侧模块以用于在成品电路组合件中直接接合在顶部表面和底部表面两者上。
多个插入件和/或多层夹可用于将多个连接带到双侧模块的顶侧。因此，举例来说，具有在较大芯片顶上具有较小芯片的芯片堆叠的双侧组合件可使用多个插入件和/或多层夹以使来自底部芯片的连接与顶部芯片的连接接合，或可使来自底部芯片的连接与模块顶部表面上的连接分离。因此，模块的顶部表面可包含除顶部芯片的一个或多个连接之外的底部芯片的一个或多个连接连接。在FET装置的情况下，此类连接可包含例如栅极、源极和漏极连接，以及用于监测装置性能的电流感测和开尔文连接。
举例来说，在包含安装在较大JFET顶上的堆叠中的较小MOSFET的双侧模块的情况下，使用本文中所描述的技术的连接选项包含单栅极调控和双栅极调控共源共栅配置，其中在后者中将分离连接提供到MOSFET和JFET栅极的顶部表面。顶部表面可进一步提供MOS和/或JFET电流感测连接，和/或MOS或JFET开尔文连接，例如JFET开尔文源极连接。
如将了解，本文中所描述的技术可进一步应用于装置的底部表面上的多个连接，例如其中顶部芯片部分地悬垂于底部芯片上。
提供此发明内容来以简化形式介绍下文在具体实施方式中进一步描述的一系列概念。此发明内容并非旨在识别所要求保护的主题的关键特征或基本特征，也并非旨在用于限制所要求保护的主题的范围。此外，要求保护的主题不限于解决本公开的任何部分中提到的任何或所有缺点的限制。
附图说明
从结合附图借助于实例给出的以下描述中可获得更详细的理解。图式通常不按比例绘制。
图1A为实例芯片堆叠的等距俯视图。
图1B为可使用芯片堆叠制成的实例共源共栅电路的电示意图。
图2A为包含四个共源共栅芯片堆叠组合件的实例模块的等距俯视图，所述共源共栅芯片堆叠组合件布置成使用线接合连接在衬底上的两对并行共源共栅芯片堆叠组合件。
图2B为图2A的模块上的共源共栅芯片堆叠的原位线接合的更近视图。
图3为在没有线接合的情况下使用插入件形成的实例芯片堆叠组合件的竖直横截面。
图4A展示在没有插入件的情况下使用夹制成的芯片堆叠组合件的竖直横截面。
图4B展示图4A的组合件顶上的连接的俯视图。
图5A展示使用图4A和图4B中说明的种类的芯片堆叠组合件中的四个的具有改进的线接合的功率模块。
图5B展示图5A的功率模块中的一个芯片堆叠组合件的更近视图。
图6展示使用图4A和图4B中说明的种类的芯片堆叠组合件的实例功率模块的竖直横截面。
图7A-7E说明用于使用夹构建芯片堆叠组合件的阵列的实例过程。
图7A为具有有暴露侧连接杆的四个芯片堆叠的实例组合件的分解图。
图7B为在囊封之前的多组合件引线框架结构中的四个芯片堆叠的等距视图。
图7C为在囊封之后的图7B的结构的等距视图。
图7D为在芯片堆叠组合件的单体化之后从图7C的四个芯片堆叠组合件中的一个的顶部的等距视图。
图7E为图7D的单元的仰视图。
图8A-8F说明用于在没有侧连接杆的情况下构建芯片堆叠组合件的阵列的实例过程。
图8A为具有四个芯片堆叠的实例组合件的分解图。
图8B为在囊封之前的引线框架结构中的四个芯片堆叠的等距视图。
图8C为在囊封之后的图8B的结构的等距视图。
图8D为在研磨图8C的结构以暴露铜衬垫且切割侧连接杆之后的等距视图。
图8E为在单体化之后来自图8D的单元的俯视图。
图8F为来自图8E的单元的仰视图。
图9A为图7D的芯片堆叠组合件的横截面，其说明侧连接到底部平面爬电距离。
图9B为图8E的芯片堆叠组合件的横截面，其说明侧连接到底部平面爬电距离。
图10展示具有实例连接变化的五个芯片堆叠组合件的俯视图，标记A到E。
图11包含芯片堆叠组合件的各种视图，所述芯片堆叠组合件具有用于MOS栅极、MOS源极和MOS电流感测(图10中的选项B)的顶部连接。
图12包含芯片堆叠组合件的各种视图，所述芯片堆叠组合件具有用于MOS栅极、MOS源极和JFET栅极(图10中的选项C)的顶部连接。
图13包含芯片堆叠组合件的各种视图，所述芯片堆叠组合件具有用于MOS栅极、MOS源极、JFET栅极和JFET源极开尔文(图10中的选项D)的顶部连接。
图14包含芯片堆叠组合件的各种视图，所述芯片堆叠组合件具有用于MOS栅极、MOS源极、MOS电流感测、JFET栅极和JFET源极开尔文(图10中的选项E)的顶部连接。
图15A为JFET栅极-源极电压(Vgs)降随着结温降低的实例的图。图15B为在测量结温的转换期间的实例栅极电流波形的图。
图16为具有用于除电源和漏极端子以外的JFET栅极、JFET源极开尔文、MOSFET栅极、MOSFET电流感测的额外连接的实例的电示意图。
具体实施方式
可使用插入件和/或多层夹以多种方式制造双侧芯片堆叠组合件以实现顶侧连接的平坦化。可使用常规或改进的线接合方法将双侧芯片堆叠组合件并入电路组合件中。插入件和多层夹可提供与大接合线(例如，铜接合线)相容的大接合区域，以提供更好的接合及更好的电和热传导。
替代地，插入件和/或多层夹可用于形成模制的双侧模块以用于在成品电路组合件中直接接合在顶部表面和底部表面两者上。举例来说，双侧芯片堆叠组合件可安装在两个直接结合铜(DBC)陶瓷衬底之间，例如具有用于连接到多个双侧芯片堆叠组合件的两侧上的各种衬垫的图案化金属化物的一个或多个DBC衬底。
这些方法解决例如在大功率和/或高电压电力电路组合件中的较低电阻和较好热传导的挑战。电力装置通常必须为并联连接的功率模块以实现所要电流额定值和/或减少有效热阻抗。在碳化硅(SiC)技术发展的情况下，尤其是例如SiC JFET共源共栅装置，芯片大小变得小得多。这造成除热的挑战。
举例来说，考虑共源共栅电路中的芯片堆叠，其中低电压MOSFET位于SiC JFET的源极衬垫顶上，且MOSFET芯片的源极衬垫充当共源共栅电力开关的源极。MOSFET芯片的大小及其源极衬垫限制用于装置的接合区域。这可限制装置的电流额定值且将其弹性限制于电力循环。
另一考虑因素为应在整合到较大组合件中之前彻底地检测和测试每一芯片堆叠。产生芯片堆叠组合件以用于整合而非将芯片堆叠直接接合到电路组合件中允许对个别芯片堆叠的更容易的测试。此继而减少了有缺陷的电力组合件的比率和与其相关联的废品或修复成本。仅一个有缺陷的芯片堆叠可能需要丢弃整个电路组合件模块。传统地，由于处置薄芯片的复杂性，在芯片级难以执行高电流和高电压测试。难以在不损坏芯片的情况下进行探针接触，高电压测试期间的电弧的问题是相当显著的。
以稳健模块形式对芯片堆叠进行测试避免了当测试呈晶片或单体化形式的裸芯片堆叠时发现的困难。也就是说，有可能在底部芯片仍呈晶片形式时将堆叠的顶部芯片添加到底部芯片。然而，举例来说，隔离芯片、在多个平面上形成连接且避免跨SiC JFET边缘终端的电弧是困难的且需要专用设备。
此外，随着技术改进，用于高功率共源共栅芯片堆叠中的SiC JFET和低电压MOSFET芯片两者都被制造得更薄，以减小电阻和热阻。此继而使得芯片越来越脆弱且更难以处置，且使得芯片级高电流和高电压测试和检测更加困难。
因此，例如出于已知良好裸片(KGD)为优选，但具有与用于处置封装芯片的技术兼容且最终介电材料在适当位置的额外优点的所有原因，需要机械稳固、已知良好、双侧芯片堆叠组合件的产生。
双侧芯片堆叠组合件的使用也是有益的，因为其允许改进或完全避免线接合。在传统的高功率电路组合件内，线接合为最可能归因于产品寿命内的电力循环而发生故障的组件。可通过使用双侧芯片堆叠组合件改进线接合，所述双侧芯片堆叠组合件提供比芯片堆叠中的芯片的顶部接合衬垫大得多的外部顶侧接合衬垫。相比于传统的金或铝接合线，这些大衬垫允许使用厚的且更具弹性的接合线，例如铜接合线。类似地，大的顶侧连接衬垫允许使用更好的冷却方法。
为了测试和组装处理，芯片堆叠可使用一个或多个插入件和/或多层夹并入芯片堆叠组合件中以形成坚固的模块。举例来说，模块可以芯片组合件的方式注射模制。应了解，此类技术可用于以传统芯片组合件的方式产生在底部平面上具有所有连接的模块。然而，在双侧芯片堆叠组合件的顶侧和底侧上呈现不同连接促进测试期间的更容易的高电压/高功率连接，和成品组合件中的更好且更可靠的连接，以及更好的热连接。
实例芯片堆叠-共源共栅
图1A展示具有直接接合在较大芯片120顶上的较小芯片110的实例芯片堆叠100。应了解，所述技术可应用于任何芯片堆叠。举例来说，出于各种目的产生的芯片堆叠可包含两个或更多个有源装置和/或无源装置的各种组合，所述有源装置例如BJT、MOSFET、JFET、IGBT、压敏电阻、二极管和/或由半导体材料(例如，硅、碳化硅(SiC)、砷化镓)构成的其它半导体装置，所述无源装置例如电阻器、保险丝、电容器等。
为简单起见，且为强调本文中所描述的使用第IV族和第III-V族半导体的芯片堆叠的技术的一些优点，本文中所使用的实例聚焦于使用接合在高功率SiC JFET 120顶上的低电压MOSFET 110的高功率共源共栅芯片堆叠100。本文中所描述的技术可用于实现高功率密度和解决任何芯片堆叠电力装置的热挑战。举例来说，本文中参考图3-9所描述的芯片堆叠组合件封装技术相较于先前技术可用于实现更好的性能、较小封装和/或减少的冷却要求。
电力芯片堆叠可在例如10V、100V、500V、1,000V、10,000V等范围内的任何电压下和在例如1A、10A、100A、500A等任何电流范围内操作。举例来说，包括低电压MOSFET/SiCJFET的共源共栅可在这些范围或更高(例如，50A到500A、600V到20,000V)中的任一个中操作。可例如通过在组合件中布置多个电力芯片堆叠来实现较高的安培数和电压。使用本文中所描述的技术，有可能实现每单位面积较高的电流电平。通过解决热导率，本文中呈现的技术减少电力装置的热循环压力且提供更稳固的连接，且由此双倍地改进可靠性。
在图1A的实例中，MOSFET 110具有顶侧MOSFET源极衬垫112和顶侧MOSFET栅极衬垫114。MOSFET 110具有背侧漏极连接116，所述背侧漏极连接使用材料130接合到且因此电连接到JFET 120的顶侧源极衬垫122。材料130可为焊料、黏着剂等，其为导热且导电的。连接可例如经由黏着剂、焊接和/或烧结而固定。
除了顶侧JFET源极衬垫122之外，JFET芯片120还具有顶侧JFET栅极衬垫124。JFET芯片具有背侧漏极连接126和边缘终端区128。
图1B展示可使用例如图1A的芯片堆叠100的芯片堆叠制成的实例共源共栅102的示意图。在图1B的实例中，MOSFET的栅极充当常关共源共栅的栅极，且JFET的漏极充当共源共栅的漏极。图1A的芯片堆叠100在MOSFET 110的源极112与JFET 120的栅极124之间没有连接。然而，图1B的共源共栅102具有将JFET的栅极接合到MOSFET的源极的连接器180。取决于芯片堆叠并入到电路组合件中的方式，可以多种方式进行此连接。在图1B的电路中，通过施加到MOSFET的栅极的电压来控制常关共源共栅102。
传统功率模块
图2A展示实例传统的电力电路组合件200，其具有电路衬底274上的四个芯片堆叠270以及包含多个连接引脚272的各种其它组件。此电路组合件通常反转以用于安装，其中引脚插入到印刷电路板的通孔中，且散热片紧固到衬底274的背侧。
图2B展示图2A的组合件200的部分202的放大图，包含芯片堆叠270中的一个的连接。出于论述的目的，假设图2A和图2B的芯片堆叠270类似于图1A的芯片堆叠100的芯片堆叠。在图2B中，芯片堆叠270的底部连接直接接合到衬底274的导电迹线。一个接合线284延伸到底部JFET芯片的栅极，且另一接合线282延伸到顶部MOSFET芯片的栅极。对MOSFET的源极进行三个连接280A-C。连接280B和280C可为单线，其中远端接合到衬底274的导电迹线，且线的中间部分用MOSFET的源极上的接合“缝合”。连接280A和280B携载源极电流，且可经由衬底274的相同导电迹线与接合线284连接，从而形成图1B的共源共栅配置。在功率模块200的实例中，接合线280C用于源极开尔文连接。针对芯片堆叠270处的电压条件的更精确测量，沿着非电流承载路径进行单独的开尔文源极连接。
传统地，铜线不用于接合高功率芯片堆叠。这是因为例如在低电压MOSFET的源极衬垫上将需要厚(例如，>10到25pm)镀铜或在适当位置烧结的铜板。在传统实践中，使用相对于铜线产生增加的电阻和降低的可靠性的非铜连接。类似地，相较于通过镀铜或铜板可制成的较大铜线，通常使用较细规格的接合线，且此再次导致增加的电阻和降低的可靠性。
具有插入件的双侧芯片堆叠组合件
图3展示使用插入件结构140制成的实例双侧芯片堆叠组合件300的竖直横截面。出于说明的目的，模块300包含连接作为如图1B中所说明的共源共栅的图1A的芯片堆叠100。MOSFET 110和JFET 120的接合衬垫本身未在图3中展示。芯片堆叠100的连接由接合材料130和132A-E指示。MOSFET 110的背侧漏极通过接合材料130接合到JFET 120的顶侧源极。接合材料132D将JFET 120的背侧漏极连接到底部直接接合铜(DBC)衬底160的导体162。衬底160具有陶瓷芯体164和外导体层166，所述外导体层可例如通过通孔连接到共源共栅漏极导体162。在图3的实例中，到芯片堆叠100的漏极的连接由导体凸片157C和157D提供，其允许隔离外层166。
包含MOSFET源极和栅极连接的MOSFET 110的顶侧连接分别形成到顶部DBC衬底150的导电迹线156C和156D。此分别使用接合材料132B和132C实现。衬底150具有陶瓷芯体154和外导体152，所述外导体可通过通孔或留下隔离连接到共源共栅源极。在图3的实例中，共源共栅栅极连接经由导体凸片157A可用，且共源共栅源极连接经由导体凸片157B可用。共源共栅的其它连接可暴露于在图3的横截面中未展示的区域中的导体166和/或152的平面上。
JFET 120的栅极衬垫位于低于MOSFET 110的顶侧连接处。JFET 120的栅极衬垫到顶部衬底150的连接可通过使用插入件140(例如，小导电块，其用材料132E接合到JFET 120顶上的栅极衬垫，且通过材料132A接合到衬底150的下部表面上的源极迹线156C)来实现。
图3的配置允许芯片堆叠100的双侧冷却。此外，此配置避免使用芯片的线接合和与其相关联的限制。芯片堆叠组合件300的性能可例如通过用高介电击穿材料填充或部分地填充间隙来进一步改进，例如以避免JFET 120的边缘终端处的电弧。囊封可进一步产生可使用常规封装芯片处置设备处置以用于检测、测试和/或组装的稳固长方体。举例来说，可在高电流和电压下测试囊封的芯片堆叠组合件而不会发生电弧或损坏芯片的危险，且作为呈例如带和卷形式的已知良好的裸片运输。
具有夹的双侧芯片堆叠组合件
图4A展示使用图1A的芯片堆叠100和可“夹”在芯片堆叠100周围以提供组合件400的顶侧和底部连接表面的引线框架元件制成的实例芯片堆叠组合件400的竖直横截面。如在图3的实例中，在模块400的核心处为芯片堆叠100，其中顶部芯片MOSFET 110用接合材料130接合到底部芯片JFET 120。在图4的实例中，JFET 120的背侧连接漏极用接合材料432E接合到散热器导体444。MOSFET 110的顶侧栅极连接衬垫通过接合材料432A接合到顶侧栅极连接导体442A。MOSFET 110的顶侧源极连接衬垫用接合材料432B接合到多层连接器源极导体442B的一部分。JFET 120的顶侧栅极连接衬垫用接合材料432C接合到多层连接导体区442C的下部部分，其为多层连接器442B的一部分。应注意，在不同高度处进行多层连接器442B和442C的连接。通过添加(例如，经由注射模制)介电囊封物470以填充组合件中的间隙来完成组合件。高质量囊封物可用于电介质470以确保极佳的电力循环可靠性，以及对湿气侵入或其它环境影响的抗性，同时还保护JFET终端免受电弧风险的影响。
导体444可为例如厚度为100pm到3mm或更大的厚铜散热器，其焊接或烧结到JFET120的背侧漏极连接。导体444可为离散的，或在初始组装时，导体444可为若干模块400同时建构于其上的底部引线框架的部分。
类似地，导体442A和442B/442C可为顶部引线框架的部分，其同时施加到组装到模块400中的芯片堆叠100或芯片堆叠100的阵列。应注意，导体442B具有进一步沿导体442A向下延伸的部分442C，以适应MOSFET 110和JFET 120的顶侧连接的高度差。导体442A和包含部分442C的导体442B可为坚硬铸造部分。替代地，一个或多个部分(例如，部分442A-C)可为类似弹簧的部件，以促进良好的连接而不管实际高度差的变化。
此外，实施顶部导体442A-C和底部导体444的引线框架可为适于附接到芯片堆叠100，或呈单体化芯片、晶片或部分晶片形式的芯片堆叠100的群组周围的夹的部分。也就是说，在单体化芯片堆叠的情况下，芯片堆叠可被围封且接合在夹中，随后用电介质470注射模制，且随后修整掉夹的部分。可通过研磨、蚀刻或激光去除来去除引线框架的非所需的部分。类似地，可通过两级锯切、研磨、激光或蚀刻进行单体化。
对于包括芯片堆叠100的阵列的晶片或晶片的一部分，包括导体442A-C和导体444的阵列的夹可围绕芯片堆叠100的阵列而夹持和接合，且所得组合件可例如通过注射模制或其它方式具备空隙填充电介质470。芯片堆叠组合件400可随后在测试之前或之后通过单体化例如将其从阵列切除。
与图3的设计相比，图4的芯片堆叠组合件400具有直接在顶部和底部表面上的顶部和底部连接，而无介入的陶瓷层，且较薄。然而，类似于图3的设计，其为稳固的长方体。芯片未机械地或环境上暴露。
此外，顶侧连接可制成比芯片顶侧接合衬垫大得多。图4B展示图4A的组合件400的俯视图。芯片堆叠组合件400可用作用于裸芯片堆叠的直接替换，具有更好的连接和更容易的测试和处置。举例来说，相较于裸芯片堆叠100，芯片堆叠组合件400可具有大于芯片接合衬垫或甚至大于芯片本身的暴露的顶侧栅极和源极连接。此外，芯片堆叠组合件的暴露的顶部和底部侧连接可为铜，例如用于准备好的焊接和/或铜线接合。
使用散热器作为导体444，例如铜散热器，和/或使用用于导体442A-C的类似材料具有若干优点。举例来说，将散热器直接接合到JFET 120使JFET 120发现的热阻最小化。由于散热器(例如，铜热散热器)的热阻低于可另外使用的陶瓷或热界面材料的热阻，因此到散热器的瞬态和稳定状态的热传递面积可极大地改进。
类似地，使用铜顶侧结构允许高得多的电流处置能力。这些顶侧结构可设计成增加由顶部衬垫提供的面积，以使超出芯片堆叠模块自身的结构的电流承载横截面接触面积最大化。铜结构越宽，装置的电流处置能力和热性能越大，其继而可进一步改进装置的电力循环寿命。
应了解，本文中描述为夹、插入件、引线框架、接合线、接合带、散热器、多层连接器、顶侧连接器等的导体可用任何导电材料实施，例如但不限于例如铝、银、金和铜的金属，或例如铜合金的合金，或其它材料。
用于将双侧模块併入较大组合件中的选项
图4A和图4B中所描绘的芯片堆叠模块400对于下游封装成更复杂的功率模块组合件极其通用。举例来说，在结构442A和442B的顶侧上使用足够厚度(例如，0.1到3mm)的铜或其它导体允许使用厚铝线接合(例如，5-20密耳)、厚铜线接合(例如，12-20密耳)、铜带接合(例如，2-20密耳，具有可变宽度以匹配顶部电极)。类似地，与可焊接、烧结、冲击焊接、超声波焊接、激光焊接或铜焊到顶部连接相比，此类厚顶侧结构可与铜导体/汇流条结构相容。这些方法无法直接应用下伏有源半导体装置的脆弱表面。这些观测结果也很大程度上适用于到底部导体444的连接，其中，例如焊接和铜焊的使用可能不会直接地适用于底部芯片。
另一形式的接触涉及弹簧负载的高压接触。这些通常与并行安装的电力装置的阵列一起使用。弹簧负载的接触形成抵抗温度循环失效的可靠的接点，同时允许双侧除热。图4A和图4B的芯片堆叠模块的结构极适合于所述目的。因此，图4A和图4B中所说明的结构不仅促进可用于将芯片堆叠并入到较大组合件中的接合材料的物质和厚度的改进，而且实现先前未在构造高功率、高电流装置时应用的封装技术的使用，从而产生具有先前未发现的热性能和可靠性的组合件。
改进的线接合
图5A展示使用四个芯片堆叠组合件570以改进的线接合制成的实例功率模块500。芯片堆叠组合件570类似于图4A和图4B中所说明的四个芯片堆叠组合件400。类似于图2A的模块200，模块500具有衬底574和其它组件，包含引脚572。
图5B展示图5A的芯片堆叠组合件570中的一个的更近视图。在图5B中，多个接合线580A、580B和580C连接到芯片堆叠组合件570的大顶侧源极衬垫。线580B和580C可为单独的线，或在线的中间部分缝合到模块的单线。芯片堆叠模块570的源极衬垫可例如能够直接接纳厚铜线。相比于使用裸芯片堆叠形成模块，芯片堆叠组合件570准许使用厚铜线接合580A-C以减小电阻且改进最终功率模块中的电力循环寿命。类似地，较大衬垫可用于共源共栅栅极连接582，且此衬垫可类似地为铜线接合的。此提供用于所有连接的单个直径的线的机会。在功率模块500的实例中，接合线580C用于源极开尔文连接，而连接580A和580B携载源极电流。
由于芯片堆叠组合件570的源极衬垫大于芯片堆叠组合件570内的MOSFET的源极衬垫，因此可对芯片堆叠组合件570源极衬垫进行更多的线接合连接，且可使用更厚的接合线连接。类似地，较厚线可用于连接栅极。由于JFET栅极形成于芯片堆叠模块570内，因此JFET栅极的单独连接是不必要的。单规格的接合线可用于所有连接，从而减少组装复杂性和成本。
用具有夹的双侧芯片堆叠组合件接合到DBC衬底
图6为包含接合在两个DBC衬底650与660之间的图4A和图4B的芯片堆叠组合件400的实例组合件600的竖直横截面。如参考图4A和图4B所描述，芯片堆叠组合件400包含图1A的芯片堆叠100以及电介质470和导体442A-C和444。此处，在图6中，芯片堆叠组合件400以类似于图3的双侧冷却模块配置的双侧冷却模块配置安装。相比于图3，具有部分442B和442C的多层导体避免了对单独插入件140的需要。结合顶侧导体442A，所有顶侧连接待通过单个平面上的单个焊接或烧结操作进行，例如使用接合材料632A和632B以连接到顶部DBC650的底部迹线656A和656B。类似地，可通过使用接合材料632F将芯片堆叠组合件400的底部导体444焊接或烧结到DBC衬底660的顶部导体662来形成底部漏极连接。图6中未展示的额外连接可使用DBC衬底上的其它迹线和/或分别穿过DBC衬底650和660的陶瓷芯体654和664的通孔形成。替代地，类似于图3的凸片157A-D的突片可用于共源共栅栅极、源极和漏极连接。
使用连接杆的实例过程
图7A-E展示用于产生例如图4A和图4B的组合件400的芯片堆叠组合件的实例过程。在图7A-E的实例中，使用在多个芯片堆叠的顶部和底部上闭合的夹引线框架部分。芯片堆叠组合件的阵列安装在下部引线框架部分上。上部引线框架包含多层结构，所述多层结构在第一高度处与每一芯片堆叠的顶部芯片连接，且在第二高度处与底部芯片连接，同时在芯片堆叠组合件的顶部表面上呈现单个连接平面。多层连接器因此形成共源共栅JFET栅极到MOSFET源极连接。图7A-E包含概念图以及在引线框架附接和模制之后的多组合件结构的外观和在单体化之后的组合件的外观。在图7A-E的实例中，成品芯片堆叠组合件包含到达侧边缘的栅极和源极衬垫铜，其可在较低电压装置中为可接受的，但可导致在高电压下测试期间的电弧挑战。
应了解，本文中所描述的许多组装步骤可以多种方式和/或以多种序列执行。举例来说，芯片堆叠可在放置于引线框架中之前组装。替代地，下部芯片可首先接合到引线框架中，且随后可在引线框架中将顶部芯片原位接合到下部芯片上。
图7A展示在不囊封的情况下的单芯片堆叠组合件700的概念分解图。芯片堆叠组合件700类似于如参考图4A和图4B所描述的芯片堆叠组合件400。顶部上为顶部引线框架部分750，其将使用连接材料712连接到MOS芯片710。MOS芯片710和顶部引线框架部分750使用连接材料722连接到JFET芯片720。JFET芯片720的底部经由连接材料762连接到底部引线框架部分760。堆叠中的连接可如参考图4A和图4B所描述例如使用焊料、导电黏着剂、烧结等来实现。
图7B展示多组合件701，其包含机械地连接在通用引线框架701B中的四个未囊封芯片堆叠701A，所述通用引线框架包含堆叠701A之间和从外部堆叠到引线框架701B的边缘的连接杆。栅极衬垫701E和源极衬垫701F在每一芯片堆叠701A的顶部上是可见的。栅极连接杆701D和源极连接杆701C是可见的。多组合件701展示为具有四个芯片堆叠701A。实际上，引线框架可设计成容纳任何数量的芯片堆叠，如由可用放置和对准技术所限制。
图7C展示多组合件702，其在添加囊封物702A之后为图7B的多组合件701。在图7C的实例中，四个芯片堆叠的顶部栅极衬垫701E和顶部源极衬垫701F在囊封之后仍然暴露，如同栅极连接杆701D、源极连接杆701C和引线框架701B的外边缘一样。
图7D展示囊封的芯片堆叠组合件703的俯视图，所述囊封的芯片堆叠组合件为在从图7C的多组合件702单体化之后的囊封的芯片堆叠组合件中的一个。在图7D的实例中，用于共源共栅栅极703A、共源共栅源极703B和共源共栅漏极703C的连接杆的末端暴露于组合件703的侧面上。否则，仅顶侧栅极衬垫701E、顶侧源极衬垫701F和囊封物702A是可见的。图7E展示芯片堆叠组合件703的仰视图，其显露底部漏极共源共栅连接件704A。
不具有暴露的顶侧连接杆的实例过程
图8A-F说明用于产生多个芯片堆叠组合件的替代过程。图8A-F的过程类似于图7A-E中所说明的过程。出于说明的目的，再次根据使用芯片堆叠(例如，如图1B中连接的图1A中的芯片堆叠)产生类似于图4A和图4B中的共源共栅装置的共源共栅装置描述过程。同样，如图4A和图7A-E中，多层连接器结构用于在不同高度处平坦化两个芯片衬垫的顶侧连接。此处，在图8A-F中，相较于图7A-E的实例，使用不同引线框架结构，使得芯片堆叠组合件不具有经暴露用于芯片堆叠组合件的侧面上的共源共栅栅极和源极的侧连接杆。此提供从组合件的底部处的漏极到栅极和源极顶侧连接的更大距离，这有益于例如避免在高电压测试期间的电弧。
此外，图8A-F中说明的方法允许在单体化之前将一个芯片堆叠的栅极和源极与其它芯片堆叠的栅极和源极隔离。也就是说，每一芯片堆叠组合件可在机械地单体化之前彼此电隔离。此允许在单体化之前经由装置的顶侧连接原位并行测试装置，这可显著地减少测试时间和成本。
替代地，使用此方法，可设计引线框架以在引线框架内并行地连接芯片堆叠组合件组，但将组彼此隔离。这允许在将组机械单体化之前同时并行测试多个单独芯片堆叠组合件组。
图8A展示类似于图7A的芯片堆叠700的芯片堆叠800的分解图。然而，在图8A的实例中，顶部引线框架850的连接杆从共源共栅栅极和源极衬垫的平面上移。其余部分类似于图7A的实例。在图8A中，顶部引线框架850通过连接材料812连接到MOS芯片810，且顶部引线框架850和MOS芯片810通过连接材料822连接到JFET芯片820。JFET 820通过连接材料862连接到底部引线框架860。
图8B展示包含具有顶侧栅极衬垫801E和顶侧源极衬垫801F的四个未囊封的芯片堆叠组合件801A的多组合件801。多组合件801类似于图7B的多组合件701。然而，此处在图8B中，例如栅极连接杆801D的顶侧连接杆在芯片堆叠组合件801A之间，且在芯片堆叠组合件801A与引线框架801B的边缘之间向上成拱形。
图8C展示多组合件802，其在囊封之后为图8B的多组合件801。一些栅极连接杆801D和源极连接杆801C在引线框架801B的边缘处可见。相比于图7C的多组合件702，在多组合件802中，顶侧栅极和源极连接衬垫尚未暴露，由囊封物802A介电材料覆盖。替代地，当然，可设计模具以防止此发生，但过程中的下一步骤将研磨掉多组合件802的顶部以去除连接杆的凸起部分。这将去除顶侧连接上的过量囊封物。将囊封物初始模制到引线框架结构的完整高度是更简单的。
图8D展示多组合件803，其在顶侧研磨之后为图8C的多组合件802。在去除囊封物802A的顶部部分之后，每一芯片堆叠的顶侧栅极衬垫801E和顶侧源极衬垫801F再次可见。多组合件803类似于图7C的多组合件702。然而，不同于多组合件702，多组合件803不具有延伸到用于顶侧栅极和源极连接的侧面的连接杆。在此实例中，一些漏极电平连接杆803A保留将芯片堆叠的中心阵列保持在引线框架801B内的适当位置。
图8E的单体化的芯片堆叠组合件804为图8C的多组合件803的四个芯片堆叠中的一个。多组合件803类似于图7D的单体化的芯片堆叠组合件703，但没有侧连接杆暴露用于顶侧栅极和源极连接。这也在图8F中看到，图8F提供单体化的芯片堆叠组合件804的仰视图，其中底部漏极衬垫805A是可见的。
暴露的连接杆的爬电效果
图9A和图9B强调来自用于图7A-E和图8A-F的实例的方法的结果的差异。图9A展示截取的图7D的横截面芯片堆叠组合件703，其中顶侧连接杆901横穿芯片上的引线框架。连接杆901在组合件背侧漏极连接的平面上方的一高度处暴露于组合件的侧面上，所述高度给定为爬电距离902。从其上设置有漏极的平面而不是从漏极触点自身到侧连接杆测量爬电，因为预期组合件将放置在延伸到组合件的两侧的漏极导体(图9A和图9B中未展示)的顶上。
图9B展示截取的图8E的横截面芯片堆叠组合件804，其中顶侧连接杆903横穿芯片上的引线框架。连接杆903不暴露于组合件的侧面上。芯片堆叠组合件804的爬电距离904包含芯片堆叠组合件的整个高度加上从芯片堆叠组合件的边缘到顶侧栅极或源极衬垫的距离，且因此长于用在组合件的侧面暴露的连接杆制成的类似组合件的爬电距离902。
应了解，可使用本文中所描述的技术通过改变引线框架图案、使用插入件和/或使用多层连接器来形成多种装置。图10展示具有MOS和JFET芯片堆叠的连接变化的五个实例芯片堆叠组合件的俯视图。
图10的实例A类似于图4B，其中芯片堆叠组合件的顶部连接用于共源共栅的MOS栅极和MOS源极。未展示JFET漏极的底部连接。此共源共栅可如图1B的实例中连接，其中JFET的栅极连接到MOSFET的源极。
图10的实例B添加MOS电流感测连接。图11包含此类芯片堆叠组合件的各种视图，所述芯片堆叠组合件具有用于MOS栅极、MOS源极和MOS电流感测的顶部连接。
图10的实例C展示用于MOS栅极、MOS源极和JFET栅极的顶侧连接。图12包含此类芯片堆叠组合件的各种视图。
图10的实例D展示用于MOS栅极、MOS源极、JFET栅极和JFET源极开尔文节点的顶部连接。图13包含此类芯片堆叠组合件的各种视图。
图10的实例E展示用于MOS栅极、MOS源极、MOS电流感测、栅极和JFET源极开尔文的顶侧连接。图14包含此类芯片堆叠组合件的各种视图。
图15A为JFET栅极-源极电压(Vgs)电压随着结温降低的实例的图。当例如JFET源极开尔文和栅极连接可直接接入时，JFET的栅极-源极PN结随着温度变化的正向电压(Vf)可用于监测JFET操作结温(Tj)。参考图15B，在具有高电压JFET的共源共栅中，可在JFET接通状态期间(例如，在等待(空白)时间段过去允许任何开启瞬态的振荡减弱之后)测量JFET栅极-源极PN结的Vf。短低电流栅极脉冲(例如，1mA)可经由可用JFET的栅极-源极环路注入，且Vf可在下一个断开信号到达JFET栅极且发生断开瞬态之前在接通状态中直接测量。可根据图15中展示的经预校准的Ig-Vf对Tj特性确定JEFT结温。此方法简化组装，因为其不涉及温度感测二极管的引入且可设计成栅极驱动系统。
图16为实例共源共栅双栅极驱动器电路的电示意图。共源共栅用JFET JI和MOSFET M1形成，所述JFET JI和MOSFET M1在堆叠组合件Ul中封装在一起。主MOSFET M1的有源区域的小区段用作电流感测，在图16中展示为MOSFET M2，其源极电极不连接到主MOSFET M1的源极，而是馈送到栅极驱动器中。电流感测用于估计在主MOSFET M1中流动的电流。M1和M2可为单芯片上的两个晶体管。
类似于图10B和图11的实例，图16的共源共栅组合件Ul具有暴露的MOS电流感测端子。类似于图10D和图13的实例，Ul具有暴露的JFET源极开尔文连接。类似于10C、10D、12和13的实例，Ul具有暴露用于JFET JI和MOSFET M1两者的栅极，从而制成U1双栅极调控共源共栅。类似于图10E和图14的实例，图16的Ul组合所有这些特征，除共源共栅漏极和源极连接之外的单独MOS栅极、JFET栅极、MOS源极、JFET源极和MOS电流感测连接。
应了解，双栅极调控共源共栅组合件可包含与共源共栅自身共同封装的其它组件。举例来说，组合件可包含速率控制装置，例如电阻器、二极管和用于控制开关特性的晶体管。另外地或替代地，一个或多个驱动器组件可与共源共栅共封装。

Claims (14)

1.一种组合件，其包括：芯片堆叠，其位于散热器顶上；第一多层连接器，其位于所述芯片堆叠顶上；及囊封，其中：
所述第一多层连接器为提供所述组合件的第一顶侧连接表面的第一顶侧连接器；
所述组合件进一步包括第二顶侧连接器和第三顶侧连接器；
所述第二顶侧连接器和所述第三顶侧连接器分别提供所述组合件的第二顶侧表面连接表面和第三顶侧表面连接表面；
所述芯片堆叠包括顶部芯片和底部芯片，所述顶部芯片和所述底部芯片为半导体装置；
所述顶部芯片和所述底部芯片各自包括第一顶侧连接衬垫和第二顶侧连接衬垫且进一步包括单个背侧连接衬垫；
所述底部芯片比所述顶部芯片更宽；
所述顶部芯片的所述背侧连接衬垫直接接合到所述底部芯片的所述第一顶侧连接衬垫；
所述散热器为具有0.1mm的最小竖直厚度的单块金属结构；
所述底部芯片的所述背侧连接衬垫直接接合到所述散热器的顶部表面；
所述散热器的底部表面充当所述组合件的底部连接表面；
所述第一多层连接器、第二顶侧连接器和第三顶侧连接器为各自具有0.1mm的最小竖直厚度的单块金属结构；
所述第一多层连接器充当第一顶侧连接器，由此所述第一多层连接器的顶部表面充当所述组合件的第一顶部连接表面；
所述第二顶侧连接器和所述第三顶侧连接器各自具有顶侧和底侧；
所述第二顶侧连接器的所述底侧在第一高度处直接接合到所述顶部芯片的所述第一顶侧连接衬垫；
所述第三顶侧连接器的所述底侧在所述第一高度处直接接合到所述顶部芯片的所述第二顶侧连接衬垫；
所述第二顶侧连接器的所述顶侧充当所述组合件的所述第二顶部连接表面；
所述第三顶侧连接器的所述顶侧充当所述组合件的所述第三顶部连接表面；
所述第一多层连接器的底部表面在第二高度处直接接合到所述底部芯片的所述第二顶侧连接衬垫；
所述囊封覆盖所述芯片堆叠的所述侧，使所述组合件的所述第一顶部连接表面、所述第二顶部连接表面和所述第三顶部连接表面及所述组合件的所述底部连接表面暴露；且
所述组合件的所述第一顶部连接表面、所述第二顶部连接表面和所述第三顶部连接表面处于第三高度。
2.根据权利要求1所述的组合件，其中所述第一多层连接器、所述第二顶侧连接器、所述第三顶侧连接器和所述头部扩散器包括铜。
3.一种功率模块，其包括根据权利要求2所述的组合件的多个例项的阵列，其中每一组合件的所述散热器为所述功率模块的第一连续金属结构的一部分。
4.根据权利要求3所述的功率模块，其中每一组合件的所述第一多层连接器为所述功率模块的第二连续金属结构的一部分。
5.一种功率模块，其包括根据权利要求2所述的组合件的多个例项的阵列，其中每一组合件的所述第一顶部连接表面、所述第二顶部连接表面和所述第三顶部连接表面经由焊料接合、烧结接合、铜焊接合或激光焊接直接连接到所述功率模块的导体。
6.一种功率模块，其包括根据权利要求2所述的组合件的多个例项的阵列，其中每一组合件的所述第一顶部连接表面经由弹簧夹直接连接到所述功率模块的导体。
7.一种功率模块，其包括根据权利要求2所述的组合件的多个例项的阵列，其中每一组合件的所述第一顶部连接表面经由一个或多个铜线接合直接连接到所述功率模块的导体。
8.一种功率模块，其包括根据权利要求2所述的组合件的多个例项的阵列，其中每一组合件的所述第一顶部连接表面经由一个或多个铝线接合直接连接到所述功率模块的导体，所述铝线接合使用具有5密耳的最小直径的铝线形成。
9.根据权利要求2所述的组合件，其中所述组合件的所述第二顶部连接表面的面积大于所述顶部芯片的总顶部面积。
10.根据权利要求2所述的组合件，其中：
所述组合件为双栅极调控共源共栅；
所述顶部芯片为MOSFET；
所述底部芯片为JFET；
所述组合件的所述第一顶部连接表面为所述JFET的栅极；
所述组合件的所述第二顶部连接表面为所述MOSFET的源极和所述共源共栅的源极；
所述组合件的所述第三顶部连接表面为所述MOSFET的栅极；且
所述底部连接表面为所述JFET的漏极和所述共源共栅的漏极。
11.根据权利要求10所述的组合件，其中：
所述MOSFET为硅MOSFET；且
所述底部芯片为碳化硅JFET。
12.根据权利要求2所述的组合件，其中：
第二多层连接器的底部表面在所述第二高度处连接所述底部芯片的第三顶侧衬垫；
所述第二多层连接器为包括铜的单块金属结构且具有0.1mm的最小竖直厚度；
所述第二多层连接器的顶部表面充当所述组合件的第四顶部连接表面。
13.根据权利要求12所述的组合件，其中：
第三顶侧连接器的顶侧充当所述组合件的第五顶侧连接器；
所述第三顶侧连接器的底部表面连接到所述顶部芯片的第三顶部衬垫；且
所述第三顶侧连接器为包括铜的单块金属结构且具有0.1mm的最小竖直厚度。
14.根据权利要求2所述的组合件，其中：
第三顶侧连接器的顶侧充当所述组合件的第四顶侧连接器；
所述第三顶侧连接器的底部表面连接到所述顶部芯片的第三顶部衬垫；且
所述第三顶侧连接器为包括铜的单块金属结构且具有0.1mm的最小竖直厚度。
CN202180092825.9A 2021-02-22 2021-11-18 具有多个顶侧连接的双侧芯片堆叠组合件 Pending CN117043941A (zh)

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