CN116190352A - 半导体结构及其制造方法 - Google Patents
半导体结构及其制造方法 Download PDFInfo
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- 239000010949 copper Substances 0.000 description 7
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
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- 239000004642 Polyimide Substances 0.000 description 1
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Abstract
本发明是一种半导体结构及其制造方法。所述半导体结构包含基板、介电层、接合层、接地金属层及多个线路层,该介电层设置于该基板的表面上,该介电层的多个开口显露该表面,该接合层设置于该介电层上,该接合层的第一接合部位于所述开口中,且该第一接合部连接该表面,该接合层的第二接合部连接该介电层,该接地金属层的第一接地层连接该接合层的该第一接合部,该接地金属层的第二接地层连接该接合层的该第二接合部,各该线路层设置于该接合层的该第二接合部上,且相邻的两个该线路层之间具有一个该第二接地层。
Description
技术领域
本发明是关于一种半导体结构,特别是关于一种具有接地金属层的半导体结构及其制造方法。
背景技术
请参阅图1及图2,为现有习知一种半导体结构200的不同视角的剖视图,该半导体结构200具有基板210、多个导接垫220、第一介电层230、第一接合层240、第一线路层250、接地金属层260、第二介电层270、第二接合层280及第二线路层290,所述导接垫220位于该基板210的表面211,该第一介电层270设置于该基板210的表面211,且该第一介电层230具有多个开口231,部分的该开口231显露各该导接垫220,部分的该开口231则显露该基板210的表面211。该第一接合层240设置于所述开口231中,该第一接合层240的第一接合部241位于该开口231中并连接各该导接垫220,该第一接合层240的第二接合部242位于该开口231中并连接该基板210的表面211。该第一线路层250连接该第一接合部241,该接地金属层260连接该第二接合部242,其中,该接地金属层260用以阻隔电磁波的干扰而设置于半导体结构200的中央,由于两个该导接垫220需要进行电流信号的传输,但因两个导接垫220之间有着该接地金属层260的阻隔,而必须借由该第二介电层270罩盖该接地金属层260,让该第二接合层280及该第二线路层290设置于该第二介电层270上而不接触该接地金属层260。这使得该半导体结构200为2P2M(2-Poly 2-Metal)的结构,导致制程较为复杂并增加整体的体积。
发明内容
本发明的主要目的在于将接地金属层分为第一金属层及第二金属层,使得线路层可由第二金属层之间通过,不需另外设置介电层罩盖接地金属层,而达成1P2M的结构。
本发明的一种半导体结构包含基板、介电层、接合层、接地金属层及多个线路层,该基板具有表面,该介电层设置于该表面上,该介电层具有多个开口,各该开口显露该表面,该接合层设置于该介电层上,该接合层的第一接合部位于所述开口中,且该第一接合部连接该表面,该接合层的第二接合部连接该介电层,该接地金属层设置于该接合层上,该接地金属层的第一接地层连接该接合层的该第一接合部,该接地金属层的第二接地层连接该接合层的该第二接合部,各该线路层设置于该接合层的该第二接合部上,且相邻的两个该线路层之间具有一个该第二接地层。
较佳地,该介电层、该第一接合部及该第一接地层位于同一第一水平高度,该第二接合部、该第二接地层及所述线路层位于同一第二水平高度,该第二水平高度高于该第一水平高度。
较佳地,该基板具有多个导接垫,所述导接垫设置于该基板的该表面,该介电层的该开口显露各该导接垫,该接合层经由该开口连接该导接垫,使各该线路层经由该接合层连接各该导接垫。
较佳地,该第一接地层经由该接合层连接该第二接地层。
较佳地,该接地金属层并未通过任何电流信号。
一种半导体结构的制造方法包含:提供基板,该基板具有表面;形成介电层于该基板的该表面,该介电层具有多个开口,所述开口显露该表面;形成接合层于该介电层上,其中部分的该接合层位于所述开口中并连接该表面,部分的该接合层连接该介电层;形成图案化光阻层于该接合层上,该图案化光阻层具有多个开孔,所述开孔显露该接合层;在该图案化光阻层的所述开孔中形成金属层,该金属层连接所述开孔显露的该接合层,且部分的该金属层位于该介电层的该开口中;剥离该图案化光阻层,以显露该图案化光阻层所罩盖的该接合层;以及以该金属层作为遮罩蚀刻该接合层,使该接合层形成为第一接合部及第二接合部,该第一接合部位于所述开口中,且该第一接合部连接该表面,该第二接合部连接该介电层,其中该金属层包含接地金属层及多个线路层,该接地金属层的第一接地层连接该接合层的该第一接合部,该接地金属层的第二接地层连接该接合层的该第二接合部,各该线路层设置于该接合层的该第二接合部上,且相邻的两个该线路层之间具有一个该第二接地层。
较佳地,该介电层、该第一接合部及该第一接地层位于同一第一水平高度,该第二接合部、该第二接地层及所述线路层位于同一第二水平高度,该第二水平高度高于该第一水平高度。
较佳地,该基板具有多个导接垫,所述导接垫设置于该基板的该表面,该介电层的该开口显露各该导接垫,该接合层经由该开口连接该导接垫,使各该线路层经由该接合层连接各该导接垫。
较佳地,该第一接地层经由该接合层连接该第二接地层。
较佳地,该接地金属层并未通过任何电流信号。
本发明借由将该半导体结构的该接地金属层分为该第一接地层及该第二接地层,使得所述线路层够直接设置于该介电层上,而达成1P2M的结构,降低制程的复杂度以及该半导体结构的体积。此外,由于该第二接地层也设置于该介电层上,能够屏蔽所述线路层互相的电磁波干扰,以提高该半导体结构电磁波屏蔽的能力。
附图说明
图1:现有习知的一种半导体结构的剖视图。
图2:现有习知的该半导体结构的剖视图。
图3:依据本发明的一实施例,一种半导体结构的俯视图。
图4:图3的A-A线段的剖视图。
图5:图3的B-B线段的剖视图。
图6:依据本发明的一实施例,一种半导体结构的制造方法的流程图。
图7A-图7G:图3的A-A线段在该半导体结构的制造方法的各步骤的剖视图。
图8A-图8G:图3的B-B线段在该半导体结构的制造方法的各步骤的剖视图。
【主要元件符号说明】
100:半导体结构 110:基板
111:表面 112:导接垫
120:介电层 121:开口
130:接合层 131:第一接合部
132:第二接合部 140:接地金属层
141:第一接地层 142:第二接地层
150:线路层 PR:图案化光阻层
O:开孔 M:金属层
H1:第一水平高度 H2:第二水平高度
200:半导体结构 210:基板
211:表面 220:导接垫
230:第一介电层 240:第一接合层
241:第一接合部 242:第二接合部
250:第一线路层 260:接地金属层
270:第二介电层 280:第二接合层
290:第二线路层 10:半导体结构的制造方法
11:提供基板 12:形成介电层
13:形成接合层 14:形成图案化光阻层
15:形成金属层 16:剥离图案化光阻层
17:蚀刻接合层
具体实施方式
请参阅图3、图4及图5,图3为本发明的一实施例,一种半导体结构100的俯视图,图4及图5则为图3中的A-A、B-B线段的剖视图,在本实施例中,该半导体结构100具有基板110、介电层120、接合层130、接地金属层140及多个线路层150。该基板110具有表面111及多个导接垫112,所述导接垫112设置于该基板110的该表面111,其中,所述导接垫112为该基板110的内部电子元件的输出/输入端或接地端。
请参阅图4及图5,该介电层120设置于该基板110的该表面111上,该介电层120具有多个开口121,各该开口121显露该表面111或各该导接垫112,其中该介电层120用以作为该基板110的该表面111的保护层及各电路元件之间的绝缘阻隔,该介电层120可为BCB或是Polyimide。
该接合层130设置于该介电层120上,该接合层130具有第一接合部131及第二接合部132,该第一接合部131位于所述开口121中,且该第一接合部131连接该基板110的该表面111或所述导接垫112,该第二接合部132位于该介电层120上并连接该介电层120。其中,该接合层130可为钛钨合金层及铜层堆叠构成,以提供金属层与该基板110的该表面111之间或金属层与该介电层120之间的接合界面。
该接地金属层140设置于该接合层130上,该接地金属层140具有第一接地层141及第二接地层142,该第一接地层141位于该介电层120的该开口121中并连接该接合层130的该第一接合部131,该第二接地层142则位于该介电层120上并连接该接合层130的该第二接合部132。较佳的,该接地金属层140并未通过任何电流信号而可做为电磁波屏蔽,且该第一接地层141经由该接合层130连接该第二接地层142而相互电性连接,使得该第一接地层141及该第二接地层142电性连接为整个导接层而具有良好的电磁波屏蔽能力。其中,该接地金属层140可为纯铜或铜层/镍层/铜层堆叠构成。
所述线路层150设置于该接合层130的该第二接合部132上并连接该第二接合部132,且各该线路层150的两端则分别伸入各该介电层120的该开口121中并经由该第一接合部131连接各该导接垫112,以提供其两端连接的该导接垫112进行电流信号的传输。由于各该线路层150所传递的电信号可能操作在射频而产生电磁波,因此,在本实施例中,相邻的两个该线路层150之间具有一个该第二接地层142,以降低各该线路层150被其他的该线路层150产生的电磁波干扰,其中,所述线路层150可为纯铜或铜层/镍层/铜层堆叠构成。
请参阅图4及图5,该介电层120、该第一接合部131及该第一接地层141位于同一第一水平高度H1,该第二接合部132、该第二接地层142及所述线路层150位于同一第二水平高度H2,该第二水平高度H2高于该第一水平高度H1。由于该第二接地层142与所述线路层150位于同一水平,因此能够避免各该线路层150产生的电磁波影响到其他的该线路层150的信号传输,并且所述线路层150可直接设置于该介电层120上而不需再设置另一层的介电层,让该半导体结构100达成1P2M的结构,降低该半导体结构100制作的复杂度及整体体积大小。
请参阅图6,为一种半导体结构的制造方法10的流程图,其包含:提供基板11、形成介电层12、形成接合层13、形成图案化光阻层14、形成金属层15、剥离图案化光阻层16及蚀刻接合层17。
请参阅图7A-图7G及图8A-图8G,其为图3的A-A线段及B-B线段在各个步骤的剖视图,请参阅图6、图7A及图8A,在步骤11中提供基板110,该基板具有表面111及多个导接垫112,所述导接垫112位于该基板110的该表面111。
请参阅图6、图7B及图8B,在步骤12中形成介电层120于该基板110的该表面111,该介电层120具有多个开口121,各该开口121显露该表面111或该导接垫112,该介电层120可通过曝光显影制程产生所述开口121。
请参阅图6、图7C及图8C,在步骤13中形成接合层130于该介电层120上,部分的该接合层130位于所述开口121中并连接该表面111或各该导接垫112,部分的该接合层130连接该介电层120,该接合层130可通过化学镀或溅镀制程形成于该介电层120上。
请参阅图6、图7D及图8D,在步骤14中形成图案化光阻层PR于该接合层130上,该图案化光阻层PR具有多个开孔O,所述开孔O显露该接合层130,以定义后续镀上该金属层的位置,该图案化光阻层PR通过涂布、曝光、显影制程形成于该接合层130上。
请参阅图6、图7E及图8E,在步骤15中在该图案化光阻层PR的所述开孔O中形成金属层M,该金属层M连接所述开孔O显露的该接合层130,且部分的该金属层M位于该介电层120的该开口121中,该金属层M可通过电镀形成于该接合层130上。
请参阅图6、图7F及图8F,在步骤16中剥离该图案化光阻层PR,以显露该图案化光阻层PR所罩盖的该接合层130。最后,请参阅图6、图7G及图8G,在步骤17中以该金属层M作为遮罩蚀刻该接合层130,使该接合层130成为该第一接合部131及该第二接合部132而完成该半导体结构100。
本发明借由将该半导体结构100的该接地金属层140分为该第一接地层141及该第二接地层142,使得所述线路层150能够直接设置于该介电层120上,而达成1P2M的结构,降低制程的复杂度以及该半导体结构100的体积。此外,由于该第二接地层142也设置于该介电层120上,能够屏蔽所述线路层150互相的电磁波干扰,以提高该半导体结构100电磁波屏蔽的能力。
以上所述,仅是本发明的较佳实施例而已,并非对本发明做任何形式上的限制,虽然本发明已以较佳实施例揭露如上,然而并非用以限定本发明,任何熟悉本专业的技术人员,在不脱离本发明技术方案范围内,当可利用上述揭示的技术内容做出些许更动或修饰为等同变化的等效实施例,但凡是未脱离本发明技术方案的内容,依据本发明的技术实质对以上实施例所做的任何简单修改、等同变化与修饰,均仍属于本发明技术方案的范围内。
Claims (10)
1.一种半导体结构,其特征在于,包含:
基板,具有表面;
介电层,设置于该表面上,该介电层具有多个开口,各该开口显露该表面;
接合层,设置于该介电层上,该接合层的第一接合部位于所述开口中,且该第一接合部连接该表面,该接合层的第二接合部连接该介电层;
接地金属层,设置于该接合层上,该接地金属层的第一接地层连接该接合层的该第一接合部,该接地金属层的第二接地层连接该接合层的该第二接合部;以及
多个线路层,各该线路层设置于该接合层的该第二接合部上,且相邻的两个该线路层之间具有一个该第二接地层。
2.根据权利要求1所述的半导体结构,其特征在于,该介电层、该第一接合部及该第一接地层位于同一第一水平高度,该第二接合部、该第二接地层及所述线路层位于同一第二水平高度,该第二水平高度高于该第一水平高度。
3.根据权利要求2所述的半导体结构,其特征在于,该基板具有多个导接垫,所述导接垫设置于该基板的该表面,该介电层的该开口显露各该导接垫,该接合层经由该开口连接该导接垫,使各该线路层经由该接合层连接各该导接垫。
4.根据权利要求2所述的半导体结构,其特征在于,该第一接地层经由该接合层连接该第二接地层。
5.根据权利要求4所述的半导体结构,其特征在于,该接地金属层并未通过任何电流信号。
6.一种半导体结构的制造方法,其特征在于,包含:
提供基板,该基板具有表面;
形成介电层于该基板的该表面,该介电层具有多个开口,所述开口显露该表面;
形成接合层于该介电层上,其中部分的该接合层位于所述开口中并连接该表面,部分的该接合层连接该介电层;
形成图案化光阻层于该接合层上,该图案化光阻层具有多个开孔,所述开孔显露该接合层;
在该图案化光阻层的所述开孔中形成金属层,该金属层连接所述开孔显露的该接合层,且部分的该金属层位于该介电层的该开口中;
剥离该图案化光阻层,以显露该图案化光阻层所罩盖的该接合层;以及
以该金属层作为遮罩蚀刻该接合层,使该接合层形成为第一接合部及第二接合部,该第一接合部位于所述开口中,且该第一接合部连接该表面,该第二接合部连接该介电层,其中该金属层包含接地金属层及多个线路层,该接地金属层的第一接地层连接该接合层的该第一接合部,该接地金属层的第二接地层连接该接合层的该第二接合部,各该线路层设置于该接合层的该第二接合部上,且相邻的两个该线路层之间具有一个该第二接地层。
7.根据权利要求6所述的半导体结构的制造方法,其特征在于,该介电层、该第一接合部及该第一接地层位于同一第一水平高度,该第二接合部、该第二接地层及所述线路层位于同一第二水平高度,该第二水平高度高于该第一水平高度。
8.根据权利要求7所述的半导体结构的制造方法,其特征在于,该基板具有多个导接垫,所述导接垫设置于该基板的该表面,该介电层的该开口显露各该导接垫,该接合层经由该开口连接该导接垫,使各该线路层经由该接合层连接各该导接垫。
9.根据权利要求7所述的半导体结构的制造方法,其特征在于,该第一接地层经由该接合层连接该第二接地层。
10.根据权利要求9所述的半导体结构的制造方法,其特征在于,该接地金属层并未通过任何电流信号。
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