CN1160621C - 处理器以及由处理器为矩阵处理使用两组寄存器的方法 - Google Patents

处理器以及由处理器为矩阵处理使用两组寄存器的方法 Download PDF

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Publication number
CN1160621C
CN1160621C CNB008108838A CN00810883A CN1160621C CN 1160621 C CN1160621 C CN 1160621C CN B008108838 A CNB008108838 A CN B008108838A CN 00810883 A CN00810883 A CN 00810883A CN 1160621 C CN1160621 C CN 1160621C
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China
Prior art keywords
registers
data matrix
register
matrix
processor
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Expired - Fee Related
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CNB008108838A
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English (en)
Chinese (zh)
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CN1365463A (zh
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Gk
G·K·陈
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Intel Corp
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Intel Corp
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Publication of CN1365463A publication Critical patent/CN1365463A/zh
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/3001—Arithmetic instructions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30032—Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/30105—Register structure
    • G06F9/30109—Register structure having multiple operands in a single register
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/3012—Organisation of register space, e.g. banked or distributed register file
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/30141—Implementation provisions of register files, e.g. ports

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  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Complex Calculations (AREA)
  • Executing Machine-Instructions (AREA)
  • Advance Control (AREA)
CNB008108838A 1999-07-26 2000-06-26 处理器以及由处理器为矩阵处理使用两组寄存器的方法 Expired - Fee Related CN1160621C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/360,612 US6625721B1 (en) 1999-07-26 1999-07-26 Registers for 2-D matrix processing
US09/360,612 1999-07-26

Related Child Applications (1)

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CN2004100038202A Division CN1532686B (zh) 1999-07-26 2000-06-26 处理器以及由处理器为矩阵处理使用两组寄存器的方法

Publications (2)

Publication Number Publication Date
CN1365463A CN1365463A (zh) 2002-08-21
CN1160621C true CN1160621C (zh) 2004-08-04

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CNB008108838A Expired - Fee Related CN1160621C (zh) 1999-07-26 2000-06-26 处理器以及由处理器为矩阵处理使用两组寄存器的方法
CN2004100038202A Expired - Fee Related CN1532686B (zh) 1999-07-26 2000-06-26 处理器以及由处理器为矩阵处理使用两组寄存器的方法

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Country Status (9)

Country Link
US (1) US6625721B1 (https=)
EP (1) EP1212677B1 (https=)
JP (2) JP4979169B2 (https=)
CN (2) CN1160621C (https=)
AU (1) AU5640400A (https=)
DE (1) DE60022206T2 (https=)
HK (1) HK1043850B (https=)
TW (1) TWI243332B (https=)
WO (1) WO2001008005A1 (https=)

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US20060190517A1 (en) * 2005-02-02 2006-08-24 Guerrero Miguel A Techniques for transposition of a matrix arranged in a memory as multiple items per word
US20070011442A1 (en) * 2005-07-06 2007-01-11 Via Technologies, Inc. Systems and methods of providing indexed load and store operations in a dual-mode computer processing environment
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US8661394B1 (en) 2008-09-24 2014-02-25 Iowa State University Research Foundation, Inc. Depth-optimal mapping of logic chains in reconfigurable fabrics
US8438522B1 (en) 2008-09-24 2013-05-07 Iowa State University Research Foundation, Inc. Logic element architecture for generic logic chains in programmable devices
US8484276B2 (en) * 2009-03-18 2013-07-09 International Business Machines Corporation Processing array data on SIMD multi-core processor architectures
JP5633122B2 (ja) * 2009-06-16 2014-12-03 富士通セミコンダクター株式会社 プロセッサ及び情報処理システム
CN101706760B (zh) * 2009-10-20 2013-07-31 龙芯中科技术有限公司 矩阵转置自动控制电路系统及矩阵转置方法
US8539201B2 (en) * 2009-11-04 2013-09-17 International Business Machines Corporation Transposing array data on SIMD multi-core processor architectures
DE112011105665T5 (de) 2011-09-26 2014-08-21 Intel Corporation Befehl und Logik zum Liefern von Vektorladen und -speichern mit Schritt- und Maskierfunktionalität
CN106951214B (zh) * 2011-09-26 2019-07-19 英特尔公司 用于向量加载/存储操作的处理器、系统、介质和方法
US9292221B2 (en) 2011-09-29 2016-03-22 Intel Corporation Bi-directional copying of register content into shadow registers
US9946541B2 (en) * 2015-12-18 2018-04-17 Intel Corporation Systems, apparatuses, and method for strided access
KR102586173B1 (ko) * 2017-10-31 2023-10-10 삼성전자주식회사 프로세서 및 그 제어 방법
CN111429346A (zh) * 2020-03-16 2020-07-17 广州兴森快捷电路科技有限公司 一种基于fpga的实时视频图像放大方法
CN114546328B (zh) * 2022-03-01 2025-02-11 上海壁仞科技股份有限公司 用于实现数据排列的方法、设备和介质
US12373214B2 (en) 2022-12-28 2025-07-29 Meta Platforms Technologies, Llc Data parallelism

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Also Published As

Publication number Publication date
HK1043850B (en) 2006-02-24
JP5466211B2 (ja) 2014-04-09
WO2001008005A1 (en) 2001-02-01
JP4979169B2 (ja) 2012-07-18
JP2012009055A (ja) 2012-01-12
CN1532686A (zh) 2004-09-29
EP1212677A1 (en) 2002-06-12
JP2003505786A (ja) 2003-02-12
DE60022206T2 (de) 2006-03-30
CN1532686B (zh) 2012-11-28
DE60022206D1 (de) 2005-09-29
CN1365463A (zh) 2002-08-21
US6625721B1 (en) 2003-09-23
EP1212677B1 (en) 2005-08-24
AU5640400A (en) 2001-02-13
TWI243332B (en) 2005-11-11
HK1043850A1 (en) 2002-09-27

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Termination date: 20130626