US3763365A - Computer graphics matrix multiplier - Google Patents

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US3763365A
US3763365A US3763365DA US3763365A US 3763365 A US3763365 A US 3763365A US 3763365D A US3763365D A US 3763365DA US 3763365 A US3763365 A US 3763365A
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C Seitz
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Evans and Sutherland Computer Corp
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    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/10Complex mathematical operations
    • G06F17/16Matrix or vector computation, e.g. matrix-matrix or matrix-vector multiplication, matrix factorization
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06TIMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T3/00Geometric image transformation in the plane of the image, e.g. from bit-mapped to bit-mapped creating a different image
    • G06T3/0006Affine transformations

Abstract

A matrix multiplier is disclosed for rotating, translating, and scaling multi-dimensional drawing definitions (vectors), the system having particular applicability to the field of computer graphics. The multiplier registers an additional dimension over that of the vectors undergoing computation, whereby to accomplish both the transformations of translation and rotation. Specifically, a multiplier is disclosed to accommodate a four-byfour matrix for use in three-dimensional transformations. Furthermore, the multiplier incorporates a cubic-array register for registering plural matrices as a push down stack, along with structure for variously delivering elements therefrom. Individual matrices may be multiplied to provide composite transformations. The system also incorporates structure for providing curve and surface information by iterating difference equations.

Description

United States Patent 1111 3,763,365

Seitz Oct. 2, 1973 COMPUTER GRAPHICS MATRIX lano, Italy) April 18, 1967.

MULTIPLIER Primar Examiner-Felix D. Gruber l t h l L.St,SltL-k Ct, y

[75] nven or 5;; es e. z a d e l y Assistant ExaminerDavid H. Malzahn A!t0rney-N ilss0n, Robbins, Wills & Berliner 73] Assignee: Evans & Sutherland Computer Corporation, Salt Lake City, Utah [57] ABSTRACT [22] Filed: Jan. 21, 1972 21 Appl. No.: 219,720

' OTHER PUBLICATIONS 1. De Lotto & R. Galimberti, Innovative Design with Computer Graphics (C.l.S,E. Laboratories & lnstituto di Elettrotecnicu ed Elettronica del Palitecnico, Mi-

A matrix multiplier is disclosed for rotating, translating, and scaling multi-dimensional drawing definitions (vectors), the system having particular applicability to the field of computer graphics. The multiplier registers an additional dimension over that of the vectors undergoing computation, whereby to accomplish both the transformations of translation and rotation. Specifically, a multiplier is disclosed to accommodate a fourby-four matrix for use in three-dimensional transformations. Furthermore, the multiplier incorporates a cubicarray register for registering plural matrices as a push down stack, along with structure for variously delivering elements therefrom. Individual matrices may be multiplied to provide composite transformations. The system also incorporates structure for providing curve and surface information by iterating difference equations.

1 10 Claims, 7 Drawing Figures COMPUTER GRAPHICS MATRIX MULTIPLIER BACKGROUND AND SUMMARY OF THE INVENTION Improvements in the speed and accuracy of modern electronic computing components have enabled the expansion of computer techniques to encompass many fresh applications For example, the field of computer graphics involves the application of computer technology for developing visual images that may be physically non-existent and which may change, as in real time, in accordance with varying input signals or other criteria. In accordance with one class of systems, visual images are defined by sets of rectangular-coordinate points. In such systems, the occasion frequently arises when a large number of coordinate points must be very rapidly transformed to accomplish a change as, for example, in the location of observation. The transformation of a point may involve rotation of the point (about a reference location) and/or translation of the point, which involves displacement in the coordinate system. Of course, the transformation (rotation and/or translation) of asubstantial number of points as normally define an image, requires substantial computation. Accordingly, a need exists for a rapid and economical structure for accomplishing transformations in a computer graphics system.

As a further complexity, in processing large volumes of data representing visual images, the need frequently occurs to perform composite or multiple transformations. For example, a display may include flying helicopters, in which the relationship of the viewer to the scene is defined by a first transformation. The positions and orientations of each of the helicopters with respect to the scene are then specified by additional transformations. To compute the relationship between the helicopter and the observer, it is necessary to concatenate the several transformations in application to each defined point (vector) in the image. Further processing is necessary to display the revolving rotors on each helicopter. The position of each of the rotors may be specitied with respect to the reference axes of the helicopters and again concatenation allows computation of the position of each rotor from the viewpoint of the observer. Thus, a prodigious volume of computation is required, and of course, if the display is in real time, the computation must be accomplished in a very short interval.

Another facility for computation that is particularly applicable in the field of computer graphics involves the iteration of sets of difference equations, as to define curves or surfaces by short line segments. The matrix multiplier hereof incorporates means for accomplishing such computation.

In general, the system hereof incorporates a memory configuration for registering a plurality of matrices which incorporates a dimension in addition to the dimension of computation. The system also incorporates means for effectively performing concatenation operations. The system further includes structure for manipulating the matrices as a push-down stack and furthermore, the system incorporates means for manipulating vectors and performing operations thereon to define curves and surfaces by the technique of difference equations.

BRIEF DESCRIPTION OF THE DRAWINGS In the drawings, which constitute a part of this specification, embodiments are illustrated demonstrating various objectives and features hereof, specifically:

FIG. lis a graph illustrative of an operation which may be performed by a system of the present invention;

FIG. 2 is a block diagram of a system including as a component, the matrix multiplier hereof;

FIG. 3 is a detailed block diagram illustrating a load ing structure portion of the matrix multiplier of FIG. 2;

FIG. 4 is a block diagram illustrating a multiplying portion of the system of FIG. 2 in greater detail;

FIG. 5 is a block diagram illustrative of surfacemultiplier aspect of the multiplier hereof as shown in FIG. 2;

FIG. 6 is a block diagram illustrative of an iterative aspect of the multiplier as shown in FIG. 2; and

FIG. 7 is a block diagram of a transposing aspect of the multiplier as shown in FIG. 2.

DETAILED DESCRIPTION OF THE ILLUSTRATIVE EMBODIMENT As explained and considered above, the need frequently arises in the field of computer graphics to revolve a large number of points (defining an image) about their location of origin and/or translate them with respect thereto, which operations are generically termed transformations. Considering a single point as a specific example, reference will now be made to FIG. 1, showing a rectangular-coordinate plot. Assume the desire to revolve a point P1 through an angle a to the location of a point P2, then further, to translate the point to the location of a point P3 by adding displacements of an x increment of 4 and a y increment of 3. That is, in the assumed example, the point P1 is to be rotated about the reference location R by an angle of a to the point P2, then translated to the point P3 (x 8, y 6).

The illustration of FIG. I is a vastly-simplified case involving two-dimension translation and rotation of a single coordinate point and serves simply for disclosure compliance. In fact, the system hereof is particularly applicable to three-dimensional displays as described in detail below and normally a multitude of vectors would be transformed, rather than a single point. However, the elemental operation analytically illustrated in FIG. 1 serves to explain a fundamental operation of the system.

Recapitulating, although the stated operations to transform a vector specifying the point P1 to a vector specifying-,the point P3 involve a rotation through the angle a coupled with a translation of Ax 4 and Ay .3; analytically the change simply involves movement of the point P1 (specified as x 5 and y 0) to the point P3 (specified as x 8 and y 6).

Preliminarily considering the mathematical operations as utilized, a two-dimensional transformation may be presented as a matrix:

with reference to its origin (in coordinates X and Y) by Tx and Ty. The vector specifying the point also may be scaled simply by multiplying the 2 X 2 trigonometric submatrix of sines and cosines (upper left) by a predetermined constant. A point of some significance to the structure as described hereinafter, is that the 2 X 2 trigonometric submatrix consists of fractional values, while the values T): and Ty are integers.

Generally as described herein, a point (which is to be transformed) is specified as a vector in terms of x, y, and either 1 or 0. That is, in the illustrative twodimensional mode, each complete'data item consists of two numbers, x and y, which are augmented by an internally generated third element to form a threeelement row vector. If the data is absolute, the vector is: [x, y, 1]. If the data is relative, the vector is: [x, y,

To accomplish a combination translation-androtation transformation, a vector definitive of a point [x, y, I or 0] is multiplied by the transformation matrix. Specifically:

[x, y, w] cos a sin a 0 Ix, y, w']

sin 01 cos a 0 Tx Ty I Multiplying the vector and the matrix provides the transformed values, as follows:

Thus, the point P3 is defined by the rectangular coordinate values x =8, y' 6 and w' 1 as indicated above and analytically illustrated in FIG. 1. It is, thus, apparent that a single matrix multiplication of the vector enables the dual transformations of translation and rotation. Generally, the system hereof functions to accomplish such transformations by providing the facility to compute matrices of one-dimension greater than the dimension of computation. Thus, in the above example, for two-dimensional computations, three dimensional matrices were utilized. Similarly, for three-dimensional computation, four-dimensional matrices are utilized.

The structure enabling combined transformations affords a powerful element in combination with other components. For example, a component disclosed in a paper entitled A Clipping Divider" presented at the Fall Joint Computer Conference (1968) and published in AFIPS Conference Proceedings, Volume 33 by Thompson Book Company, Washington, D. C., may be combined with the present structure to accomplish perspective views of three-dimensional objects tumbling in real time.

Considering an application of the present system in greater detail, a matrix multiplier 18 (FIG. 2) in accordance herewith may be placed between a computer unit 20 and a viewing system 22, which may include a clipping divider as disclosed in the above-referenced paper. The computer unit 20 also is connected to a memory 26 and an input-output unit 28. The computer unit 20, the associated memory 26 and the input-output unit 28, as well as the viewing system 22 may take any of a variety of well known forms.

The units as shown in FIG. 2 are indicated to be connected by several cables which are individually designated by the letters D and C. The cables C indicate control paths while the cables D indicate data-flow paths. Generally, the matrix multiplier 18 receives input signals from the computer unit 20 and delivers processed output signals to the viewing system 22 or to the memory 26 through the computer 20. When the matrix multiplier 18 is active, each coordinate point is multiplied by a matrix that is held in the multiplier 18. For example, in three-dimensional operation, a vector, representing a coordinate point, is multiplied by a matrix representing a transformation as follows:

["1 Y Z, n n n 14 l*''- y. 2' n n 2:! n s: n "a n n n Note, the actual multiplication is:

a x a y (1 ,2 a x x a x a y a z a w y a x a y 11 2 a w z a x a y a z a w w Considering a single exemplary plane (FIG. 3) of rows and columns in a matrix register 30 (cubic array) of the multiplier 18, (FIG. 2) loading structure is illustrated. The single plane 30 of registers contains the elements of a four-by-four matrix in component registers 30a. As indicated in FIG. 3, each of the separate registers 30a is accessible through a gating system 32 which is connected to receive data through data lines D2 and D1 from the computer unit 20 under control of signals carried in a control line C.

Generally, as well known in the prior art, the gating system 32 enters the signal-represented vector elements in the individual registers 30a. Subsequently, as described in somewhat greater detail below, the registers 30a supply signal-represented values for multiplication. The units for such multiplication may utilize fraction-arithmetic structure, which requires that one of the numbers involved in each multiplication be a fraction. However, in the system hereof, such a limitation is accommodated. That is, the operating matrices are composed ofa submatrix (upper left above) for accomplishing rotation (the components of which are the trigonometric fractions) and a vector for accomplishing translation, the components of which are integers. Considering a three-dimensional operation (involving a four-dimensional matrix) the matrix may involve elements as indicated below wherein the letters r designate rotational elements and the letters I represent translation elements. As the rotational elements r are fractions and the translational elements I are integers, the matrix takes a form of fractions and integers as represented by the letters F (fraction) and I (integer).

'11 12 0 F F F 0 '21 '22 '23 0 F F F 0 31 32 33 0 F F F 0 t2; ty t2 s I I I F As shown, the form of the transformation is homogeneous, the elements r comprising a rotation matrix and the elements t defining the displacement in three dimension space. Generally, as the elements of the rotation matrix (r) are the products of sines and cosines, each is a fraction. The translation elements may be thought of as integers. Note that the element s is a fraction which may be employed to scale the figure. In the multiplication of matrices in the form identified above, the homogeneous vectors conventionally will take the form: [x, y, z, w] [I, I, I, F]. Consequently, in the multiplication of a vector by a matrix, each component or elemental multiplication involves a fraction and in that manner, as indicated, twos complement multiplication structure may be employed as well known.

The matrix register 40 (FIG. 4) includes planes PA and PB, each of which may consist of a plane register 30 as illustrated in FIG. 3. The planes are sources of signal-represented matrices as considered above, for multiplication, which may also be provided from the computer unit (FIG. 2). Each of the memory planes PA and PB may register a four-by-four matrix including a total of sixteen elements. The individual elements and elemental registration locations are both designated by a letter A or B (indicative of the plane) with a numerical subscript (indicative of the plane position).

The plane PA of the matrix register 40 is connected through a multiplexor 41 and a cable 42 to a summing multiplier 44. The multiplier 44 is also connected to receive signal-represented vectors x, y, z, w] from the computer unit 20 (FIG. 2) through a cable 46. Functionally, the multiplier 44 multiplies the vector received through a cable 46 and the matrix received through the cable 42, providing representative product signals. The computer unit 20 (FIG. 2) provides the vector elements to the cable 46 in a predetermined order in accordance with the multiplication format, and the multiplexor 41 functions, as well known, to similarly provide the elements of the matrix from the plane PA. The multiplexor 41 is actuated by a timing signal TM which is provided by the computer unit 20.

In one mode of operation a series of accumulated multiplications are performed. Specifically, the vector elements A A A and A are provided to the multiplier 44 in synchronism with signals representative of the vector elements x, y, z and w; each pair being multiplied and accumulated as a sum that develops the transformed value x. Next, the element y is developed by accumulating products of the signal-represented values: A x A y A z A w, after which the transformed elements z and w' are similarly developed as two accumulated values:

1' 1: ss) sa w and W Aux Any 113.2 A W.

The signal-represented quantities x, y', z and w, thus developed, manifest the transformed vector and are provided in an output cable 48, which is connected to the viewing system 22 (FIG. 2) and/or the computer unit 20.

Summarizing, it may be seen that when the matrix multiplier 18 (FIG. 2) is active to accomplish a transformation, each coordinate point (vector) is multiplied by the matrix contained in the plane PA (FIG. 4) to result in signals defining a transformed point. Thus, as described above with reference to a two-dimensional array, wherein actual numerical values were employed with reference to FIG. 1, the coordinate points are revolved and translated to accomplish the desired total transformation in accordance with the principles of the present invention. Thus, the system may be very effectively employed to economically accomplish a multitude of coordinate point transformations in a short interval of time. Again, the distinctive structure enabling that capability resides in the capability for registering and manipulating an additional dimension.

The system hereof also has the capability to concatenate two transformations into a composite transformation. In that regard, as indicated above, itis sometimes necessary to impose a matrix-defined transformation on a substructure within a display, while allowing the entire drawing including the substructure to be similarly transformed. This requires that each coordinate point be multiplied by a matrix [Tl] which defines the relationship of the substructure to the drawing, after which the result must be multiplied by another matrix [70] defining the relation of the drawing to the viewer. Accordingly, the transformation for each coordinate point becomes:

[ y, z, y. z

Rather than generating intermediate sets of values for each coordinate point, by the computation: [x, y, z, w] [Tl], and subsequently multiplying that result by [T0], the multiplier hereof has the capability to develop the composite transformation, as the product of [T1] [T0]. The application of that composite to a multitude of coordinate points then greatly reduces the required volume of computation. As the formation of composite transformations generalizes to any level, in that various numbers of matrix products may be required, the system incorporates structure for manipulating such products in the form of matrices in a pushdown stack, thus allowing a subroutine structure of the display to be employed which is, patterned after the symbol structure of the drawing.

The illustrative system operates to concatenate two transformations which are then registered in a single matrix plane. Specifically, a signal-represented matrix from the plane PB (FIG. 4) is applied (element by element) through a multiplexor 54 (as previously described) to a summing multiplier 56. The multiplier 56 may be combined with the multiplier 44 in an operating embodiment of the system; however, for illustrative purposes in the disclosure, two separate multipliers are indicated.

The multiplexor 54 (computer controlled) selectively applies the signal-represented matrix elements from the addressed source plane PB to the multiplier 56 in accordance with the multiplication format. Similar elements of another matrix are supplied through a cable 60 from the computer unit 20. Consequently, as disclosed above, the individual multiplications are accumulated and a concatenated matrix is developed for which representative signals are supplied through a multiplexor 61 to be registered in the plane PA. The multiplexor 61 is rendered operative, along with a multiplexor 54 by a timing signal TC provided from the computer unit 20 which signal commands the operation to concatenate the two selected individual transformation matrices. Thus, concatenated matrices may be developed and registered inthe matrix register to effect a considerable reduction in the volume of computation required in accomplishing multiple transformations on a large number of individual vectors.

In addition to the above functions of the matrix multiplier, structure for accomplishing another operation is provided, which again is particularly useful with regard to computer-graphics applications. Essentially, the structure includes an iterative control unit 90 (FIG. 5) to operate in cooperation with the multiplier 44 and the expanded matrix register 50 so as to iterate a set of difference equations, as for drawing curves and surfaces composed of short line segments. Preliminary to considering the iterative control unit 90 in detail, some preliminary explanation of the mathematical operations involved will be provided.

Assume, for example, the desire to define a length of the curve indicated by an arbitrarily-selected illustrative equation x x y. Applying a series of independent variables x (from an initial value of l to the illustrative equation produces a series of values for the quantity y as indicated by the following chart.

x y A A A" l The above chart not only indicates independent values of x and dependent values y, but additionally indicates values of differences: A (y,,,, y,,); A (A A and A (A A As the illustrative equation is of the third order, the third difference A is constant, i.e., 6.

With the illustrative equation, x a: y, the differences between the progressive values in the dependent variable (y) with uniform increments in the independent quantity (x) are subject to increasing differentials. Similarly, the differences between the previous differences are also subject to increasing differentials. However, the differences between the last differences, i.e., differences A, are constant at 6. Accordingly, as an alternative to computing values for the dependent variable y by applying the equation on the basis of increments in the independent variable x, such values can be computed by adding differences. For example, in the above chart, the addition of the difference A i.e. 6 to the lesser value of the difference A and the addition of the result to a lesser value A results in a difference for determining the next incremental value of y which would have resulted from a uniform increment in the independent variable x. Generally, the system hereof functions to compute specific values for plotting a curve or developing a surface by the use of this technique. Of course, the technique represented by a simple mathematical example above, may be expanded to various orders and to surfaces rather than line situations. The expansion to surfaces involves the operation of the cubic array register 50 (FIG. 5).

From the above, it is apparent that the computation of the next value of the dependent variable y in each incremental progression may be obtained by performing three additions in sequence. Thus, referring to FIG. 5, it may be seen that the desired unknown values for the dependent variable y may be developed in steps by operating on known quantities of y, A, A and A whereby three additions are performed. The iterative control circuit 90 exploys an adder of the summing multiplier 44 with the array register 50 to accomplish the iterative process. The connections are complex in numbers; however, a single example is illustrative of all.

Referring to FIG. 6, four registers 90, 92, 94 and 96 are represented and coincide to the four registers in the top row 1 in the plane PA of the cubic array 50 (FIG. 5). The rows and columns of the plane PA are generally indicated in FIG. 6. For the sake of simplicity in presentation, a number of separate adders are illustrated in FIG. 6; however, it is to be understood that a single adder of the multiplier 44 may be time shared or any of the apparent intermediate alternatives can be employed.

The registers 90 and 92 are connected to an adder 98, the output of which is returned to the register 92. Somewhat similarly, the registers 92 and 94 are connected to an adder 100, the output of which is returned to the register 94. In further similarity, the registers 94 and 96 are connected to an adder 102, the output of which is provided as an output signal representative of values for the dependent variable y and is returned to the register 96.

Considering a numerical example as shown in the above chart to generate an incremental value of the dependent variable y, assume that the register 90 contains a value of 6 while the register 92 contains a value of 28, and the contents of register 94 is while that of the register 96 is I80. These levels of value are underlined in the above chart, and are deemed to exist at a time when the independent variable x is to be incremented from 6 to,7. Of course, it is to be appreciated that the registers 90, 92, 94 and 96 may be loaded directly from the computer unit 20 (FIG. 2) as illustrated in FIG. 3, to attain aparticular set of initial conditions.

On the command to increment, by a timing signal Ax, the contents of the register (6) is added to the contents of the register 92 (28) to obtain a value of 34 which is: (I) returned to the register 92 and (2) added with the contents of the register 94 (80) by the adder 100 to develop a value of 114. The value from the adder 100 is: (I) returned to the register 94 and (2) additively combined with a value of by the adder 102 to produce a value of 294 which is the next incremental value of the dependent variable y. Thus, the system performs progressive additions to accomplish curves.

i In the operation of the system to provide defined surfaces, the use of the single row of registers (Row 1 as shown in detail) is expanded to define a complete line. Specifically, the registers 90, 92, 94 and 96 of Row 1, as set forth in detail are duplicated, with interconnections in Rows 2, 3, and 4. Also, these row structures are duplicated in similar interconnected Columns 1, 2, 3, and 4 as indicated. Accordingly, a matrix plane of sixteen registers is interconnected by adders which function in timed sequence as explained above. A plurality of such planes are then provided as a cubic array as generally illustrated in FIG. 5. Thus, a group of y values can be provided which define lines, to in turn define surfaces. Specifically, just as the single Row 1 may operate as described above to generate a curve by a series of segments, a plane (comprising four columns, four rods or four rows) may be modified and to generate surfaces. That is, in the operation of the system as illustrated in FIG. 6, surfaces may be variously developed, as by working the individual registers along row configurations, along column configurations or along rod configurations, extending into the cubic array in the third dimension.

The flexibility of the illustrative multiplier system is further enhanced by structure for delivering elements of matrices as registered in the cubic array 50 (FIG. in ,a manner so as to provide transformations. The specific apparent manipulations involved include the selective delivery of matrix elements as by going down either the rods, the columns or the rows of the cubic array 50; and the transposition or reflection of the matrix elements about diagonal planes therein. Essentially, output operations are involved for exchanging: rows for columns, columns for rods or rods for rows.

Referring to FIG. 5, a transposition unit 70 is indicated to be connected to the cubic array register 50 by cables 72 and 74. The transposing unit 70 is connected to the computer unit to receive timing signals TR at an input 76 and a series of address signals, consisting of an address pattern, at an input 78. Functionally, the transposing unit provides signal-represented matrix elements to a cable 79, in various pre-arranged patterns as specified by applied address pattern signals received at the input 78 from the computer unit 20 (FIG. 2). It is to be recognized that the transposing unit 70 may include certain previously-described signal flow patterns; however, in the interests of simplicity and ease of disclosure, the transposing unit 70 is treated as a separate and distinct structure.

The detailed operation of the transposing unit 70 will be considered with reference to the cubic array register 50 as shown in FIG. 7. As indicated above, the transposition may involve the designating registers to specify columns, rods or rows. Considering the cubic array register 50 (FIG. 7) it may be seen that the memory element A registers a key element of a row X,, a column Y, and a rod 2,. If a matrix is specified from the plane PA, it will be provided element-by-element beginning with the row X (A A A A followed by the row X (A A A A in turn followed by rows X (A A A A and X, (A,,, A A A somewhat as described above. However, in accordance herewith, a matrix may also be specified on the basis of columns or rods in the cubic array register. Specifically, a matrix can be specified by columns Y Y,, Y, and Y commanding elements as follows (in the adopted terminology):

ll! A21! A31! A A... A... A...

A13 A131 A33! A43 14! A24! A341 A44 In the adopted terminology, the elements B, C, and D appear in other planes. Thus, a matrix may also be specified by rods for delivery from the cubic array memory 50. Again in the adopted terminology such a matrix would be:

The examples above indicate that the four-by-four cubic array register 50 actually carries orderly arrangements of twelve sixteen-element matrices. Physically, the definition of these matrices may be pictured on the basis of slicing the cube progressively along its three dimensions. In accordance with dimensional convention, the twelve matrices are designated: X X X X Y Y Y Y,, Z,, Z Z and 2,, as indicated in FIG. 7. The matrices may be addressed by a simple four-bit binary code as follows:

OOOl

x 0010 x, 0011 x, 0100 Y 0101 Y, 0110 Y 0111 Y, 1000 z,- 1001 2 1010 2 1011 z, 1100 In the operation of this aspect of the system, address signals, as designated by the above code, are applied (from the computer unit 20) to an address sequence unit through an address cable 82. On receipt of such signals, the address sequence unit 80 provides a series of address signals to an address unit 84 specifying the locations of matrix elements in the cubic array register 50 to provide the selected matrix as indicated above. Elements are then either registered or sensed, depending upon the command supplied to the address unit 84.

Considering a specific example in detail, assume a desire to sense a matrix Y from the cubic array register 50. Accordingly, signals representative of the code 0111 are applied to the address sequence unit 80 while the sense input 92 to the address unit 84 receives a high signal and the register input 94 receives a low signal. The code 0111 applied to the unit 80 results in a predetermined series of elemental addresses (registered or generated) to specify elements from the cubic array register 50 as follows:

31 sa sa 34 D31 32 03 ar Thus, 'the matrix Y as specified, is provided, element-by-element, in signal represented form at an output cable 96 from the cubic array register 50. During registration operations, a similar sequence results in the registration of matrix elements received through an input cable 98. Accordingly, any orderly matrix may be specified in the cubic array register 50, which enables considerable flexibility in operation, particularly as related to the other structural aspects thereof as de-' scribed above.

Of course, the various aspects hereof are important solely and cooperatively and consequently the system hereof is not to be interpreted by an analysis of the disclosed system but rather shall be determined by the claims as follows.

2. A matrix multiplier according to claim 1 wherein said matrix register comprises a cubic array register for containing a plurality of said matrices.

3. A matrix multiplier according to claim 2 further including multiplexor means connected between said matrix register and said multiplication means for selectively providing signal-representative matrices from at least two planes as registered in said matrix register.

4. A matrix multiplier according to claim 2 further including means connected to said matrix register for transposing signal-representative matrices in said matrix register.

5. A matrix multiplier according to claim 2 further including concatenation multiplier means connected to said matrix register for providing signals representative of the products of two matrices to said multiplication means and means for registering such products in said matrix register.

6. A matrix multiplier according to claim 2 further including means connected to said matrix register for iteratively adding the contents of portions of said matrix register to provide signals to designate points along a generated curve.

7. A matrix multiplier for manipulating vector matrix components, comprising:

a matrix register including a plurality of planar registers, for registering plural matrices in a cubic array defining rows, elements and rods;

multiplier means connected to said matrix register to receive signal-represented matrix components therefrom to provide signal-represented products; and

means for variously addressing said matrix register including means for effectively transposing matrix components within said matrix register between rods, rows and columns whereby to provide signalrepresented matrix components registered in different portions of said matrix register to said multiplier means for combination with other signalrepresented values by said multiplier means.

8. A matrix multiplier according to claim 7 wherein said means for variously addressing comprises means for selecting matrices from one plane elemental register in said cubic array.

9. A matrix multiplier according to claim 7 further including means for transferring matrix components to said multiplier means in an iterative pattern to define geometric patterns.

10. A matrix multiplier according to claim 7 wherein said matrix register registers transformation matrices of at least one degree greater than the degree of vectors whereby said multiplier means accomplishes both rotation and translation.

Patent No.

Inventor(s) UNITED STATES PATENT OFFICE Dated October 2, 1973 Charles L. Seitz Column Column Column Column Column Column Column Column (SEAL) Attest:

-- operate Column 2, line line line

line

line

line

line

line

It is certified that error appears in the above-identified patent and that said Letters Patent are hereby corrected as shown below:

"is" should be its "L; +O L should be L +O+L "a X" should be a w 11,1 L l after "display" should be code after "is" delete the comma;

"a" should be "28" should be 2 8 "80" should be Q "180" should be 18o line 1 after "modified and" should be EDWARDM.FLETCHER, JR. Attesting Officer FORM PO-IO5O (10-69) Signed and sealed this 19th day of March 197A.

0. MARSHALL DANN Commissioner of Patents USCOMM-DC 50376-P69 US. GOVERNMENT PRINTING OFFICE I969 0-366-334,

Claims (10)

1. A matrix multiplier to process transformations for vectors of a predetermined number of dimensions D, comprising: a matrix register for registering (D + (1 or more)) by (D + (1 or more)) matrices; and multiplication means connected for receiving a signalrepresented matrix from said matrix register and for receiving a signal-represented one of said vectors, to multiply said signal-represented matrix with said signal-represented vector, to accomplish both transformations of translation and rotation.
2. A matrix multiplier according to claim 1 wherein said matrix register comprises a cubic array register for containing a plurality of said matrices.
3. A matrix multiplier according to claim 2 further including multiplexor means connected between said matrix register and said multiplication means for selectively providing signal-representative matrices from at least two planes as registered in said matrix register.
4. A matrix multiplier according to claim 2 further including means connected to said matrix register for transposing signal-representative matrices in said matrix register.
5. A matrix multiplier according to claim 2 further including concatenation multiplier means connected to said matrix register for providing signals representative of the products of two matrices to said multiplication means and means for registering such products in said matrix register.
6. A matrix multiplier according to claim 2 further including means connected to said matrix register for iteratively adding the contents of portions of said matrix register to provide signals to designate points along a generated curve.
7. A matrix multiplier for manipulating vector matrix components, comprising: a matrix register including a plurality of planar registers, for registering plural matrices in a cubic array defining rows, elements and rods; multiplier means connected to said matrix register to receive signal-represented matrix components therefrom to provide signal-represented products; and means for variously addressing said matrix register including means for effectively transposing matrix components within said matrix register between rods, rows and columns whereby to provide signal-represented matrix components registered in different portions of said matrix register to said multiplier means for combination with other signal-represented values by said multiplier means.
8. A matrix multiplier according to claim 7 wherein said means for variously addressing comprises means for selecting matrices from one plane elemental register in said cubic array.
9. A matrix multiplier according to claim 7 further including means for transferring matrix components to said multiplier means in an iterative pattern to define geometric patterns.
10. A matrix multiplier according to claim 7 wherein said matrix register registers transformation matrices of at least one degree greater than the degree of vectors whereby said multiplier means accomplishes both rotation and translation.
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EP0069541A2 (en) * 1981-07-04 1983-01-12 Gec-Marconi Limited Data processing arrangement
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EP0146250A2 (en) * 1983-11-03 1985-06-26 Bts-Broadcast Television Systems, Inc. System and method for a data processing pipeline
US4553220A (en) * 1983-05-19 1985-11-12 Gti Corporation Matrix multiplier with normalized output
EP0172920A1 (en) * 1984-03-05 1986-03-05 Fanuc Ltd. Picture display method
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US4667300A (en) * 1983-07-27 1987-05-19 Guiltech Research Company, Inc. Computing method and apparatus
US4697247A (en) * 1983-06-10 1987-09-29 Hughes Aircraft Company Method of performing matrix by matrix multiplication
US4719588A (en) * 1983-05-06 1988-01-12 Seiko Instruments & Electronics Ltd. Matrix multiplication circuit for graphic display
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US4945500A (en) * 1987-11-04 1990-07-31 Schlumberger Technologies, Inc. Triangle processor for 3-D graphics display system
US5025407A (en) * 1989-07-28 1991-06-18 Texas Instruments Incorporated Graphics floating point coprocessor having matrix capabilities
EP0461030A1 (en) * 1990-06-08 1991-12-11 France Telecom Vector processing circuit and method
US5113490A (en) * 1989-06-19 1992-05-12 Silicon Graphics, Inc. Method for forming a computer model from an intersection of a cutting surface with a bounded volume
US5644523A (en) * 1994-03-22 1997-07-01 Industrial Technology Research Institute State-controlled half-parallel array Walsh Transform
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Cited By (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3881098A (en) * 1973-07-05 1975-04-29 Gerber Scientific Instr Co Photoexposure system
US3976982A (en) * 1975-05-12 1976-08-24 International Business Machines Corporation Apparatus for image manipulation
US4283765A (en) * 1978-04-14 1981-08-11 Tektronix, Inc. Graphics matrix multiplier
US4275268A (en) * 1978-07-20 1981-06-23 Sony Corporation Mixing apparatus
US4449201A (en) * 1981-04-30 1984-05-15 The Board Of Trustees Of The Leland Stanford Junior University Geometric processing system utilizing multiple identical processors
US4616217A (en) * 1981-05-22 1986-10-07 The Marconi Company Limited Visual simulators, computer generated imagery, and display systems
EP0069541A2 (en) * 1981-07-04 1983-01-12 Gec-Marconi Limited Data processing arrangement
EP0069541A3 (en) * 1981-07-04 1985-12-27 Gec-Marconi Limited Data processing arrangement
US4719588A (en) * 1983-05-06 1988-01-12 Seiko Instruments & Electronics Ltd. Matrix multiplication circuit for graphic display
US4553220A (en) * 1983-05-19 1985-11-12 Gti Corporation Matrix multiplier with normalized output
US4697247A (en) * 1983-06-10 1987-09-29 Hughes Aircraft Company Method of performing matrix by matrix multiplication
US4667300A (en) * 1983-07-27 1987-05-19 Guiltech Research Company, Inc. Computing method and apparatus
EP0146250A3 (en) * 1983-11-03 1987-11-19 Bts-Broadcast Television Systems, Inc. System and method for a data processing pipeline
EP0146250A2 (en) * 1983-11-03 1985-06-26 Bts-Broadcast Television Systems, Inc. System and method for a data processing pipeline
US4646075A (en) * 1983-11-03 1987-02-24 Robert Bosch Corporation System and method for a data processing pipeline
EP0172920A1 (en) * 1984-03-05 1986-03-05 Fanuc Ltd. Picture display method
EP0172920A4 (en) * 1984-03-05 1986-08-21 Fanuc Ltd Picture display method.
US4736330A (en) * 1984-09-04 1988-04-05 Capowski Joseph J Computer graphics display processor for generating dynamic refreshed vector images
US4885703A (en) * 1987-11-04 1989-12-05 Schlumberger Systems, Inc. 3-D graphics display system using triangle processor pipeline
US4888712A (en) * 1987-11-04 1989-12-19 Schlumberger Systems, Inc. Guardband clipping method and apparatus for 3-D graphics display system
US4901064A (en) * 1987-11-04 1990-02-13 Schlumberger Technologies, Inc. Normal vector shading for 3-D graphics display system
US4945500A (en) * 1987-11-04 1990-07-31 Schlumberger Technologies, Inc. Triangle processor for 3-D graphics display system
US5113490A (en) * 1989-06-19 1992-05-12 Silicon Graphics, Inc. Method for forming a computer model from an intersection of a cutting surface with a bounded volume
US5025407A (en) * 1989-07-28 1991-06-18 Texas Instruments Incorporated Graphics floating point coprocessor having matrix capabilities
EP0461030A1 (en) * 1990-06-08 1991-12-11 France Telecom Vector processing circuit and method
FR2663138A1 (en) * 1990-06-08 1991-12-13 France Etat Method and signal processing circuit digital REPRESENTATIVE vectors or tuples of the same dimension and their application sets of cardinality and vectors or tuples of any dimensions.
US5335195A (en) * 1990-06-08 1994-08-02 France Telcom Method and circuit for processing digital signals representative of vectors or tuples of the same dimension and application thereof to sets having any cardinality and to vectors or tuples of any dimensions
US5786823A (en) * 1993-05-07 1998-07-28 Eastman Kodak Company Method and apparatus employing composite transforms of intermediary image data metrics for achieving imaging device/media compatibility and color appearance matching
US5644523A (en) * 1994-03-22 1997-07-01 Industrial Technology Research Institute State-controlled half-parallel array Walsh Transform
US6407736B1 (en) 1999-06-18 2002-06-18 Interval Research Corporation Deferred scanline conversion architecture
US6611264B1 (en) 1999-06-18 2003-08-26 Interval Research Corporation Deferred scanline conversion architecture
US6625721B1 (en) * 1999-07-26 2003-09-23 Intel Corporation Registers for 2-D matrix processing
WO2001009837A1 (en) * 1999-07-30 2001-02-08 Microsoft Corporation Graphics container
US6518976B1 (en) 1999-07-30 2003-02-11 Microsoft Corporation Graphics container
US20020143838A1 (en) * 2000-11-02 2002-10-03 Hidetaka Magoshi Parallel arithmetic apparatus, entertainment apparatus, processing method, computer program and semiconductor device

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