CN115769373A - 用于集成电路的有机间隔物 - Google Patents

用于集成电路的有机间隔物 Download PDF

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CN115769373A
CN115769373A CN202080099982.8A CN202080099982A CN115769373A CN 115769373 A CN115769373 A CN 115769373A CN 202080099982 A CN202080099982 A CN 202080099982A CN 115769373 A CN115769373 A CN 115769373A
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silicon die
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organic
die
silicon
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B·刘
F·易
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Intel Ndtm Usa LLC
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Intel Corp
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Abstract

提供了用于集成电路的有机间隔物。有机间隔物提供了用于解决诸如热膨胀系数(CTE)失配、动态翘曲和焊料接合可靠性(SJR)等等之类问题具有费效比且具有成本效益的解决方案。

Description

用于集成电路的有机间隔物
技术领域
本公开的实施例总体上关于集成电路领域，并且更具体地关于用于集成电路的有机间隔物。
背景技术
集成电路(integrated circuit，IC)被用于各种广泛的应用。一些IC封装可具有组件，这些组件具有相对于其他支撑组件的大型悬垂物(overhang)。此外，一些IC封装会由于与衬底的热膨胀系数(coefficient of thermal expansion,CTE)失配而遭受角落应力聚集。这些应力聚集常导致管芯的角落处的衬底迹线破裂。另外，一些IC封装可具有相对大的管芯大小和不平衡的布局，这会导致动态翘曲和焊料接合可靠性(solder jointreliability，SJR)问题。
附图说明
通过下列具体实施方式并结合所附附图，可容易地理解实施例。为了便于该描述，类似的附图标记指示类似的结构元件。通过示例方式而非通过限制的方式在附图的各图中示出各实施例。
图1A-图1C图示根据各实施例的利用有机间隔物的集成电路的截面图。
图2A和图2B图示根据各实施例的利用有机间隔物的集成电路的附加的截面图。
图3是图示根据一些实施例的与提供有机间隔物相关联的过程的示例的流程图。
图4A-图4C是图示图3的过程的多个方面的等轴测图。
图5示意性地图示根据各实施例的包括集成电路的计算设备的示例。
具体实施方式
本公开的实施例涉及在IC应用中利用有机间隔物的系统、方法和装置。本公开的实施例的有机间隔物有助于提供具有费效比且具有成本效益的解决方案，以解决诸如CTE失配、动态翘曲和SJR等等的问题。在一些实例中，IC包括：半导体衬底；硅管芯；以及间隔物，设置在硅管芯与半导体衬底之间，其中，间隔物包括有机化合物，并且其中，间隔物被提供以减小半导体衬底与硅管芯之间的热膨胀系数(CTE)失配。
在下列描述中，将使用由本领域技术人员通常采用以将他们的工作实质传达给本领域的其他技术人员的术语来描述说明性实现方式的各方面。然而，对本领域技术人员将显而易见的是，可仅利用所描述的方面中的一些方面来实施本公开的实施例。为了解释的目的，陈述特定的数字、材料和配置以提供对说明性实现方式的透彻理解。然而，对本领域技术人员将显而易见的是，可在没有这些特定细节的情况下实施本公开的实施例。在其他实例中，省略或简化公知的特征，以免混淆说明性实现方式。
在下列具体实施方式中，参考形成其一部分的附图，在附图中，同样的数字通篇指定同样的部分，并且在附图中，通过说明的方式示出了可在其中实施本公开的主题的实施例。应理解，可利用其他实施例，并且可作出结构或逻辑的改变而不背离本公开的范围。因此，以下具体实施方式不应以限制的意义来理解，并且实施例的范围由所附权利要求及其等效方案来限定。
出于本公开的目的，短语“A和/或B”意指(A)、(B)、(A)或(B)、或者(A和B)。出于本公开的目的，短语“A、B和/或C”意指(A)、(B)、(C)、(A和B)、(A和C)、(B和C)或(A、B和C)。
本说明书可使用基于视角的描述，诸如，顶部/底部、中/外、上方/下方等等。此类描述仅用于方便讨论，并且不旨在将本文中所描述的实施例的应用限于任何特定定向。
说明书可使用短语“在实施例中”或“在多个实施例中”，其可各自指代相同或不同实施例中的一个或多个。此外，如相对于本公开的实施例所使用的术语“包含”、“包括”、“具有”等是同义的。
本文中可使用术语“与……耦合”及其派生词。“耦合的”可意指以下各项中的一项或多项。“耦合的”可意指两个或更多个元件处于直接的物理或电气接触。然而，“耦合的”还可意指两个或更多个元件彼此间接接触，但仍彼此协作或交互，并且可意指一个或多个其他元件被耦合或连接在被称为彼此耦合的元件之间。
用于解决这些问题的一些先前的解决方案包括使用硅间隔物来抬起悬垂组件并平衡IC的结构。一些先前的解决方案在IC封装的底部使用大型硅间隔物，以试图保持衬底应力并改善SJR。此外，一些先前的解决方案涉及调整衬底芯CTE和环氧模制化合物(epoxymold compound,EMC)CTE，以试图尝试降低破裂迹线的可能性。
然而，使用硅间隔物实现起来常常是异常昂贵的。类似地，调整衬底/EMC CTE涉及配制和应用特殊的EMC和衬底材料，这同样常常是昂贵的。此外，使用大型硅间隔物典型地仅减少(但不消除)应力聚集问题。
相比之下，本公开的实施例有助于提供使用有机间隔物来解决此类问题的更具费效比且更具成本效益的解决方案。例如，本公开的有机间隔物具有更高效的组装过程流程，并且能以比常规的硅间隔物更低的成本被生产。此外，通过提供平衡的硅相比EMC的比率，有机间隔物能够更有效地解决上文描述的动态翘曲问题。
图1A图示根据各实施例的利用有机间隔物(在该示例中为EMC砖式间隔物)的IC的截面图。在该示例中，有机间隔物允许IC结构保持不被改变，同时减小衬底与管芯之间的CTE失配或使衬底与管芯之间的CTE失配最小化。具体地，图1A图示硅管芯结构100，该硅管芯结构100包括设置在半导体衬底105上的硅管芯D1、D2、D3和D4，其中，D1、D2、D3和D4如图所示地彼此堆叠。如从图1A可见，管芯D3和D4可从堆叠式结构101伸出，从而至少部分地悬于衬底105的区域115之上。
换言之，提供硅管芯D1-D4的布局结构，其中，硅管芯D1设置为与衬底105接触，但免于与硅管芯D3和间隔物102接触。当硅管芯D2设置在硅管芯D1与硅管芯D3之间时，硅管芯D3基本上悬于硅管芯D2之上(在区域115中)，并且间隔物102为硅管芯D3和D4提供支撑。在常规解决方案中，此类悬垂会导致结构101的某种程度的不平衡状态。
如图1A中所示，间隔物102设置于硅管芯D3与半导体衬底105之间，其中，间隔物包括有机化合物，并且其中，间隔物被提供，以减小半导体衬底105与硅管芯D3之间的热膨胀系数(CTE)失配。在该示例中，间隔物102包括有机化合物EMC。然而，结合本公开的实施例的间隔物也可由其他有机化合物(诸如，有机焊料研磨材料)形成。在一些实施例中，有机间隔物可由两种或更多种不同的有机化合物形成。
在图1A中，可提供硅管芯D1-D4的布局结构100，其中，硅管芯D1与衬底105接触，但免于与硅管芯D3和间隔物102接触。当硅管芯D2设置在硅管芯D1与硅管芯D3之间时，硅管芯D3基本上悬于硅管芯D2之上，并且间隔物102为硅管芯D3和D4提供支撑。
如图1A中所示，间隔物102设置在硅管芯D3与半导体衬底105之间，以减少上文描述的应力和翘曲问题或使上文描述的应力和翘曲问题最小化，并且进一步使得悬垂的管芯D3和D4稳定，由此提供结构100的平衡。在实施例中，间隔物102包括有机化合物，并且可提供半导体衬底105与硅管芯D3之间的热膨胀系数(CTE)失配的减小。在该示例中，间隔物102包括有机化合物EMC。然而，结合本公开的实施例的间隔物也可由其他有机化合物(诸如，有机焊料研磨材料)形成。在一些实施例中，有机间隔物可由两种或更多种不同的有机化合物形成。
图1B和图1C图示根据本公开的实施例的有机间隔物的使用。图1B图示布局结构120的示例，其中，硅管芯121包括与间隔物130接触的膜层122。类似地，图1A中的硅管芯D1-D4同样可包括膜层。例如，在图1A中，硅管芯D3包括与间隔物102接触的膜层110。在硅管芯D4的底侧上的膜层111同样与硅管芯D3的顶侧接触。在图1B中，有机间隔物130有助于减小硅管芯121与衬底之间的CTE失配，由此有助于减小硅管芯121的角落处的角落应力聚集和衬底迹线破裂。
图1C图示在硅管芯结构140的底部的细长的有机间隔物145(例如，EMC砖式间隔物)的示例。细长的有机间隔物145帮助结构支撑结构140中的大管芯大小，由此有助于解决动态翘曲问题和SJR问题。
在一些实施例中，有机间隔物可被用于帮助提供用于减小IC封装布局设计大小的解决方案。此外，本公开的有机间隔物可利用对EMC相比硅的比率的改变来帮助更好地利用IC封装布局中的竖直空间和水平空间。例如，在一些实例中，IC布局可能缺乏组件之间的水平空间，但是具有在竖直方向上的未使用空间。
图2A和图2B图示根据各实施例的利用有机间隔物的集成电路的附加的截面图。具体而言，图2A图示根据一些实施例的、提供组件之间的增加的水平间距的IC的示例的截面图。如图所示，结构200可使用设置在衬底205与硅管芯D1之间的有机间隔物202(在该示例中为EMC间隔物)，以提升硅管芯D1的层面水平(level)，从而悬于硅管芯D2之上并允许组件之间的增加的水平间距。
图2B图示另一实施例的示例。在该示例中，布局结构210包括第一有机间隔物220，该第一有机间隔物220设置在衬底205与硅管芯D1之间以提升硅管芯D1的竖直层面水平，而第二有机间隔物225与第一间隔物220相邻并设置在衬底205与硅管芯D2之间以提升硅管芯D2的竖直层面水平。以此方式，间隔物220和225允许布局结构210的竖直空间被更好地利用，并且允许硅管芯D1、D2与其他组件重叠，同时保持免于与其他组件接触。
图3是图示根据本公开的各种实施例的用于提供有机间隔物的过程300的示例的流程图。参考图4A-图4C提供对过程300的描述。
如图3中所图示，过程300包括：在310处，在玻璃载体上模制包括有机间隔物的晶片，该有机间隔物具有目标类型和目标厚度。图4A图示该步骤的示例，其中，具有目标EMC类型和目标厚度420的晶片400被模制在玻璃载体405上。如图4B中所示，模制的晶片400可与玻璃载体405分离，并被安装到膜410上。
过程300进一步包括：在320处，切割晶片以提供具有目标厚度420的一个或多个有机间隔物砖，如图4C中所图示。有机间隔物砖可(例如，以如图4C中所示的网格图案)被切割为特定的目标大小，以用于特定电路中的应用。相应地，有机间隔物砖可被切割为目标尺寸，该目标尺寸具有目标厚度420和任何合适的目标长度和目标宽度。一个或多个有机间隔物砖可被设置在电子设备的衬底上，以基于目标类型减小电子设备的衬底与硅管芯之间的热膨胀系数(CTE)失配。
过程300进一步包括：在330处，将一个或多个有机间隔物砖附连至电子设备的衬底，以在电子设备的衬底与硅管芯之间提供间隔物层，其中，硅管芯被设置在衬底上或要被设置在衬底上。间隔物砖可按各种配置被附连至设备的衬底，其示例在上文描述并在图1A-图1C和图2A-图2B中图示。
图5示意性地图示根据本文中公开的各实施例的示例计算设备，该示例计算设备可包括具有一个或多个有机间隔物的集成电路。计算设备500包括：耦合至一个或多个处理器504的系统控制逻辑508；存储器设备512；一个或多个通信接口516；以及输入/输出(input/output，I/O)设备520。在一些实施例中，例如包括一个或多个有机间隔物的集成电路(例如，如图1A-图1C和图2A-图2B中所图示)的集成电路可被包括在存储器设备512中，或被包括在系统500的组件中的另一组件中。
例如，存储器设备512可包括耦合至电路板513的封装管芯514，封装管芯514包括半导体衬底、硅管芯、以及设置在硅管芯和半导体衬底之间的间隔物，其中，该间隔物包括有机化合物，并且其中，间隔物被提供以减小半导体衬底与硅管芯之间的热膨胀系数(CTE)失配。
存储器设备512可以是非易失性计算机存储芯片(例如，设于管芯上)。在一些实施例中，存储器设备512包括封装(诸如，具有设置于其中的存储器设备512的IC组件)、驱动器电路(例如，驱动器)、用于将存储器设备512与计算设备500的其他组件电气耦合的输入/输出连接等等。存储器设备512可被配置成用于可移除地或永久地与计算设备500耦合。在实施例中，存储器设备512包括例如NAND设备，例如，3D SLC NAND设备、TLC(triple-levelper cell，每单元三级)NAND设备、QLC(quad-level per cell，每单元四级)NAND设备、或SLC NAND设备。
在一些实施例中，存储器设备512包括任何合适的持久性存储器，例如，受益于实施例的原位写入(write-in-place)字节可寻址非易失性存储器，诸如，竖直地缩放的存储器设备。在一些实施例中，存储器设备512可包括通过改变存储器单元的电阻来存储数据的任何合适的存储器。在实施例中，存储器512可包括字节可寻址原位写入三维交叉点存储器设备、或其他字节可寻址原位写入NVM设备，诸如，单级或多级相变存储器(Phase ChangeMemory，PCM)或具有开关的相变存储器(phase change memory with a switch，PCMS)、使用硫属化物相变材料(例如，硫属化物玻璃)的NVM设备、包括金属氧化物基底、氧空位基底和导电桥随机访问存储器(Conductive Bridge Random Access Memory，CB-RAM)的电阻式存储器、纳米线存储器、铁电随机访问存储器(ferroelectric random access memory，FeTRAM、FRAM)、结合忆阻器技术的磁阻随机访问存储器(magneto resistive randomaccess memory，MRAM)、自旋转移力矩(spin transfer torque，STT)-MRAM、基于自旋电子磁结存储器的设备、基于磁隧穿结(magnetic tunnelling junction，MTJ)的设备、基于DW(Domain Wall，畴壁)和SOT(Spin Orbit Transfer，自旋轨道转移)的设备、基于晶闸管的存储器设备、上述任何的组合或其他存储器。
(一个或多个)通信接口516可为计算设备500提供接口以通过一个或多个网络进行通信和/或与任何其他合适的设备进行通信。(一个或多个)通信接口516可包括任何合适的硬件和/或固件。用于一个实施例的(一个或多个)通信接口516可包括例如网络适配器、无线网络适配器、电话调制解调器、和/或无线调制解调器。对于无线通信，用于一个实施例的(一个或多个)通信接口516可使用一个或多个天线来将计算设备500与无线网络通信地耦合。
对于一个实施例，(一个或多个)处理器504中的至少一个可与用于系统控制逻辑508的一个或多个控制器的逻辑封装在一起。对于一个实施例，(一个或多个)处理器504中的至少一个可与用于系统控制逻辑508的一个或多个控制器的逻辑封装在一起，以形成系统级封装(System in Package，SiP)。对于一个实施例，(一个或多个)处理器504中的至少一个可集成在与用于系统控制逻辑508的一个或多个控制器的逻辑相同的管芯上。对于一个实施例，(一个或多个)处理器504中的至少一个可集成在与系统控制逻辑508的一个或多个控制器的逻辑相同的管芯上，以形成片上系统(System on Chip，SoC)。
用于一个实施例的系统控制逻辑508可包括用于提供至(一个或多个)处理器504中的至少一个处理器和/或至与系统控制逻辑508通信的任何合适的设备或组件的任何合适的接口的任何合适的接口控制器。系统控制逻辑508可将数据移入和/或移出计算设备500的各种组件。
用于一个实施例的系统控制逻辑508可包括存储器控制器824，用于提供至存储器设备512的接口以控制各种存储器访问操作。存储器控制器524可包括控制逻辑528，该控制逻辑528可专门被配置成用于控制存储器设备512的访问。
在各实施例中，I/O设备520可包括：被设计成启用与计算设备500的用户交互的用户接口、被设计成启用与计算设备500的外围组件交互的外围组件接口、和/或被设计成确定与计算设备500有关的环境状况和/或位置信息的传感器。在各实施例中，用户接口可包括但不限于显示器(例如，液晶显示器、触摸屏显示器等)、扬声器、麦克风、用于捕捉图片和/或视频的一个或多个数码相机、闪光灯(例如，发光二极管闪光灯)、以及键盘。在各实施例中，外围组件接口可包括但不限于非易失性存储器端口、音频插口、以及功率供应接口。在各实施例中，传感器可包括但不限于陀螺仪传感器、接近度传感器、环境光传感器和定位单元。附加地或替代地，定位单元可以是(一个或多个)通信接口516的部分，或可与(一个或多个)通信接口516交互，以与定位网络的组件(例如，全球定位系统(global positioningsystem，GPS)卫星)通信。
在各实施例中，计算设备500可以是移动计算设备，诸如但不限于膝上型计算设备、平板计算设备、上网本、智能电话等；台式计算设备；工作站；服务器等。计算设备500可具有更多或更少的组件和/或不同的体系结构。在进一步的实现方式中，计算设备500可以是处理数据的任何其他电子设备。
示例
根据各种实施例，本公开描述了多个示例。
示例1包括一种装置，该装置包括：半导体衬底；硅管芯；以及间隔物，设置在硅管芯与半导体衬底之间，其中，间隔物包括有机化合物，并且其中，间隔物被提供以减小半导体衬底与硅管芯之间的热膨胀系数(CTE)失配。
示例2包括示例1或本文中的某个其他示例的装置，其中，有机化合物包括环氧模制化合物(EMC)或有机焊料掩模材料。
示例3包括示例1或本文中的某个其他示例的装置，其中，硅管芯包括膜层，并且其中，该膜层与间隔物接触。
示例4包括示例1或本文中的某个其他示例的装置，其中，硅管芯是第一硅管芯，并且该装置进一步包括与半导体衬底接触的第二硅管芯。
示例5包括示例4或本文中的某个其他示例的装置，其中，第二硅管芯免于与第一硅管芯或EMC间隔物接触。
示例6包括示例4或本文中的某个其他示例的装置，其中，该装置进一步包括设置在第一硅管芯与第二硅管芯之间的第三硅管芯。
示例7包括示例4-6中的任一项或本文中的某个其他示例的装置，其中，每个相应的硅管芯包括相应的膜层。
示例8包括示例1或本文中的某个其他示例的装置，其中，硅管芯是第一管芯，其中，第一硅管芯的第一侧与间隔物接触，并且其中，第一硅管芯的第二侧与第二硅管芯接触。
示例9包括示例8或本文中的某个其他示例的装置，其中，第一硅管芯包括在第一硅管芯的第一侧接触间隔物的第一膜层，并且其中，第二硅管芯包括与第一硅管芯的第二侧接触的第二膜层。
示例10包括示例1或本文中的某个其他示例的装置，其中，硅管芯是第一硅管芯，并且间隔物是第一间隔物，并且其中，该装置进一步包括：第二硅管芯；以及第二间隔物，与第一间隔物相邻，第二间隔物设置在衬底与第二硅管芯之间。
示例11包括一种方法，该方法包括：在玻璃载体上模制包括有机间隔物的晶片，该有机间隔物包括目标类型和目标厚度；以及切割晶片以提供具有目标厚度的一个或多个有机间隔物砖，其中，一个或多个有机间隔物砖用于被设置在电子设备的衬底上，以基于目标类型减小电子设备的衬底与硅管芯之间的热膨胀系数(CTE)失配。
示例12包括示例11或本文中的某个其他示例的方法，进一步包括：将一个或多个有机间隔物砖附连至电子设备的衬底，以在电子设备的衬底与硅管芯之间提供间隔物层，其中，硅管芯被设置在衬底上或要被设置在衬底上。
示例13包括示例11或本文中的某个其他示例的装置，其中，有机间隔物具有目标类型，所述目标类型包括环氧模制化合物(EMC)或有机焊料掩模材料。
示例14包括示例11或本文中的某个其他示例的方法，其中，切割晶片包括：提供具有目标大小的一个或多个间隔物砖，该目标大小包括目标厚度、目标长度和目标宽度。
示例15包括示例11或本文中的某个其他示例的方法，其中，硅管芯是第一硅管芯，并且电子设备进一步包括与衬底接触的第二硅管芯。
示例16包括示例15或本文中的某个其他示例的方法，其中，第二硅管芯免于与第一硅管芯或有机间隔物接触。
示例17包括一种计算设备，该计算设备包括：电路板；以及封装管芯，与电路板耦合，该封装管芯包括：半导体衬底；硅管芯；以及间隔物，设置在硅管芯与半导体衬底之间，其中，间隔物包括有机化合物，并且其中，间隔物被提供以减小半导体衬底与硅管芯之间的热膨胀系数(CTE)失配。
示例18包括示例17或本文中的某个其他示例的电子设备，其中，有机化合物包括环氧模制化合物(EMC)或有机焊料掩模材料。
示例19包括示例17或本文中的某个其他示例的计算设备，其中，硅管芯包括膜层，并且其中，该膜层与间隔物接触。
示例20包括示例17或本文中的某个其他示例的电子设备，其中，硅管芯是第一硅管芯，并且封装管芯进一步包括与半导体衬底接触的第二硅管芯。
各实施例可包括上述实施例的任何合适的组合，包括以上以联合形式(和)描述的实施例的替代(或)实施例(例如“和”可以是“和/或”)。此外，一些实施例可包括具有存储在其上的指令的一个或多个制品(例如，非暂态计算机可读介质)，这些指令在被执行时产生上文描述的实施例中的任一实施例的动作。另外，一些实施例可包括具有用于执行上文描述的实施例的各种操作的任何合适装置的设备或系统。
所图示的实现方式的以上描述(包括摘要中描述的内容)不旨在是排他性的，也不旨在将本公开的实施例限于所公开的确切形式。虽然为了说明目的在本文中描述了具体实现和示例，但如相关领域技术人员将认识到的，在本公开的范围内有各种等效修改是可能的。
鉴于以上详细描述，可对本公开的实施例作出这些修改。所附权利要求中使用的术语不应当解释为将本公开的各实施例限制为说明书和权利要求书中公开的特定实现。相反，范围将完全由所附权利要求书确定，所附权利要求书将根据既定的权利要求解释原则来解释。

Claims (20)

1.一种装置，包括：
半导体衬底；
硅管芯；以及
间隔物，设置在所述硅管芯与所述半导体衬底之间，其中，所述间隔物包括有机化合物，并且其中，所述间隔物被提供以减小所述半导体衬底与所述硅管芯之间的热膨胀系数(CTE)失配。
2.如权利要求1所述的装置，其中，所述有机化合物包括环氧模制化合物(EMC)或有机焊料掩模材料。
3.如权利要求1所述的装置，其中，所述硅管芯包括膜层，并且其中，所述膜层与所述间隔物接触。
4.如权利要求1所述的装置，其中，所述硅管芯是第一硅管芯，并且所述装置进一步包括与所述半导体衬底接触的第二硅管芯。
5.如权利要求4所述的装置，其中，所述第二硅管芯免于与所述第一硅管芯或所述EMC间隔物接触。
6.如权利要求4所述的装置，其中，所述装置进一步包括设置在所述第一硅管芯与所述第二硅管芯之间的第三硅管芯。
7.如权利要求4-6中的任一项所述的装置，其中，每个相应的硅管芯包括相应的膜层。
8.如权利要求1所述的装置，其中，所述硅管芯是第一管芯，其中，所述第一硅管芯的第一侧与所述间隔物接触，并且其中，所述第一硅管芯的第二侧与第二硅管芯接触。
9.如权利要求8所述的装置，其中，所述第一硅管芯包括在所述第一硅管芯的第一侧接触所述间隔物的第一膜层，并且其中，所述第二硅管芯包括与所述第一硅管芯的第二侧接触的第二膜层。
10.如权利要求1所述的装置，其中，所述硅管芯是第一硅管芯，并且所述间隔物是第一间隔物，并且其中，所述装置进一步包括：
第二硅管芯；以及
第二间隔物，与所述第一间隔物相邻，所述第二间隔物设置在所述衬底与所述第二硅管芯之间。
11.一种方法，包括：
在玻璃载体上模制包括有机间隔物的晶片，所述有机间隔物具有目标类型和目标厚度；以及
切割所述晶片以提供具有所述目标厚度的一个或多个有机间隔物砖，其中，所述一个或多个有机间隔物砖用于被设置在电子设备的衬底上，以基于所述目标类型减小所述电子设备的所述衬底与硅管芯之间的热膨胀系数(CTE)失配。
12.如权利要求11所述的方法，进一步包括：将所述一个或多个有机间隔物砖附连至所述电子设备的所述衬底，以在所述电子设备的所述衬底与所述硅管芯之间提供间隔物层，其中，所述硅管芯被设置在所述衬底上或要被设置在所述衬底上。
13.如权利要求11所述的方法，其中，所述有机间隔物具有目标类型，所述目标类型包括环氧模制化合物(EMC)或有机焊料掩模材料。
14.如权利要求11所述的方法，其中，切割所述晶片包括：提供具有目标大小的所述一个或多个间隔物砖，所述目标大小包括目标厚度、目标长度和目标宽度。
15.如权利要求11所述的方法，其中，所述硅管芯是第一硅管芯，并且所述电子设备进一步包括与所述衬底接触的第二硅管芯。
16.如权利要求15所述的方法，其中，所述第二硅管芯免于与所述第一硅管芯或所述有机间隔物接触。
17.一种计算设备，包括：
电路板；以及
封装管芯，与所述电路板耦合，所述封装管芯包括：
半导体衬底；
硅管芯；以及
间隔物，设置在所述硅管芯与所述半导体衬底之间，其中，所述间隔物包括有机化合物，并且其中，所述间隔物被提供以减小所述半导体衬底与所述硅管芯之间的热膨胀系数(CTE)失配。
18.如权利要求17所述的计算设备，其中，所述有机化合物包括环氧模制化合物(EMC)或有机焊料掩模材料。
19.如权利要求17所述的计算设备，其中，所述硅管芯包括膜层，并且其中，所述膜层与所述间隔物接触。
20.如权利要求17所述的计算设备，其中，所述硅管芯是第一硅管芯，并且所述封装管芯进一步包括与所述半导体衬底接触的第二硅管芯。
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