CN1157024C - 时钟同步方法及其所用的装置 - Google Patents
时钟同步方法及其所用的装置 Download PDFInfo
- Publication number
- CN1157024C CN1157024C CNB991220013A CN99122001A CN1157024C CN 1157024 C CN1157024 C CN 1157024C CN B991220013 A CNB991220013 A CN B991220013A CN 99122001 A CN99122001 A CN 99122001A CN 1157024 C CN1157024 C CN 1157024C
- Authority
- CN
- China
- Prior art keywords
- clock
- data
- circuit
- pointer
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4027—Coupling between buses using bus bridges
- G06F13/405—Coupling between buses using bus bridges where the bridge performs a synchronising function
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Software Systems (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
- Accessory Devices And Overall Control Thereof (AREA)
Abstract
Description
Claims (12)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP318322/1998 | 1998-10-22 | ||
JP31832298A JP3447586B2 (ja) | 1998-10-22 | 1998-10-22 | クロック同期化方法及びその装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1252658A CN1252658A (zh) | 2000-05-10 |
CN1157024C true CN1157024C (zh) | 2004-07-07 |
Family
ID=18097900
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB991220013A Expired - Fee Related CN1157024C (zh) | 1998-10-22 | 1999-10-22 | 时钟同步方法及其所用的装置 |
Country Status (5)
Country | Link |
---|---|
US (1) | US6519709B1 (zh) |
JP (1) | JP3447586B2 (zh) |
KR (1) | KR100346675B1 (zh) |
CN (1) | CN1157024C (zh) |
TW (1) | TW523989B (zh) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6633972B2 (en) * | 2001-06-07 | 2003-10-14 | Intel Corporation | Method and apparatus for utilizing static queues in processor staging |
JP3542574B2 (ja) * | 2001-08-28 | 2004-07-14 | Necマイクロシステム株式会社 | システムクロック同期化回路 |
US6952791B2 (en) * | 2001-12-03 | 2005-10-04 | Broadcom Corporation | Method and circuit for initializing a de-skewing buffer in a clock forwarded system |
US6895481B1 (en) | 2002-07-03 | 2005-05-17 | Cisco Technology, Inc. | System and method for decrementing a reference count in a multicast environment |
JP2005101771A (ja) * | 2003-09-22 | 2005-04-14 | Matsushita Electric Ind Co Ltd | クロック乗せ替え回路および方法 |
JP2006279326A (ja) * | 2005-03-28 | 2006-10-12 | Naohiko Yasui | パケット送受信装置 |
CN101227689B (zh) * | 2007-12-27 | 2011-01-19 | 华为技术有限公司 | 信息上报方法及装置 |
JP6190699B2 (ja) * | 2013-11-12 | 2017-08-30 | 株式会社メガチップス | Emi低減回路 |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61196497A (ja) | 1985-02-26 | 1986-08-30 | Toshiba Corp | メモリ制御回路 |
JPH0481142A (ja) | 1990-07-24 | 1992-03-13 | Fujitsu Ltd | 脱落重複判定信号出力回路 |
US5742760A (en) * | 1992-05-12 | 1998-04-21 | Compaq Computer Corporation | Network packet switch using shared memory for repeating and bridging packets at media rate |
JPH0669913A (ja) | 1992-06-18 | 1994-03-11 | Fujitsu Ltd | クロック乗換回路 |
JPH066333A (ja) | 1992-06-19 | 1994-01-14 | Fujitsu Ltd | クロック乗換回路 |
JPH0730528A (ja) | 1993-07-09 | 1995-01-31 | Fujitsu Ltd | クロック乗換回路 |
US5555524A (en) * | 1995-02-13 | 1996-09-10 | Standard Microsystems Corporation | Semi-synchronous dual port FIFO |
US5668767A (en) * | 1995-12-29 | 1997-09-16 | Cypress Semiconductor Corp. | Polled FIFO flags |
US5956748A (en) * | 1997-01-30 | 1999-09-21 | Xilinx, Inc. | Asynchronous, dual-port, RAM-based FIFO with bi-directional address synchronization |
US6101329A (en) * | 1997-02-18 | 2000-08-08 | Lsi Logic Corporation | System for comparing counter blocks and flag registers to determine whether FIFO buffer can send or receive data |
US5982741A (en) * | 1998-09-17 | 1999-11-09 | Tut Systems, Inc. | Method and apparatus for automatically reducing cross-talk between wires coupled to a common network device |
TW406265B (en) | 1998-09-23 | 2000-09-21 | Ind Tech Res Inst | Structure and method of asynchronous dual port FIFO memory |
-
1998
- 1998-10-22 JP JP31832298A patent/JP3447586B2/ja not_active Expired - Fee Related
-
1999
- 1999-10-19 US US09/421,137 patent/US6519709B1/en not_active Expired - Fee Related
- 1999-10-21 TW TW88118225A patent/TW523989B/zh not_active IP Right Cessation
- 1999-10-22 KR KR1019990046144A patent/KR100346675B1/ko not_active IP Right Cessation
- 1999-10-22 CN CNB991220013A patent/CN1157024C/zh not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
TW523989B (en) | 2003-03-11 |
JP2000134188A (ja) | 2000-05-12 |
KR100346675B1 (ko) | 2002-07-27 |
KR20000029266A (ko) | 2000-05-25 |
CN1252658A (zh) | 2000-05-10 |
US6519709B1 (en) | 2003-02-11 |
JP3447586B2 (ja) | 2003-09-16 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C06 | Publication | ||
PB01 | Publication | ||
ASS | Succession or assignment of patent right |
Owner name: NEC ELECTRONICS TAIWAN LTD. Free format text: FORMER OWNER: NIPPON ELECTRIC CO., LTD. Effective date: 20030418 |
|
C41 | Transfer of patent application or patent right or utility model | ||
TA01 | Transfer of patent application right |
Effective date of registration: 20030418 Address after: Kanagawa, Japan Applicant after: NEC Corp. Address before: Tokyo, Japan Applicant before: NEC Corp. |
|
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
REG | Reference to a national code |
Ref country code: HK Ref legal event code: GR Ref document number: 1054609 Country of ref document: HK |
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C17 | Cessation of patent right | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20040707 Termination date: 20091123 |