CN1154182C - 半导体器件 - Google Patents

半导体器件 Download PDF

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CN1154182C
CN1154182C CNB981052975A CN98105297A CN1154182C CN 1154182 C CN1154182 C CN 1154182C CN B981052975 A CNB981052975 A CN B981052975A CN 98105297 A CN98105297 A CN 98105297A CN 1154182 C CN1154182 C CN 1154182C
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signal terminal
semiconductor device
terminal electrode
lead frame
electrode
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CN1192582A (zh
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石田秀俊
宫辻和郎
上田大助
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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Abstract

本发明揭示一种使半导体器件封装小型化，并且使信号端子电极其电气隔离性提高的半导体器件。半导体器件在封装1的中央部位配置引线框2，周边部位配置信号端子电极3至信号端子电极7，在引线框2上搭载半导体芯片8，在信号端子电极4和信号端子电极5之间配置具有接地电位的接地电极16，信号端子电极5和信号端子电极6之间配置具有接地电位的接地电极17。

Description

半导体器件
技术领域
本发明涉及一种具有安放高频器件的封装的半导体器件。
背景技术
近年来以便携电话、PHS为代表的移动通信终端需要小型化。因此，考虑将移动通信终端所用的半导体器件的封装进行缩小。
先说明现有的半导体器件。图5是一具有6端子小型封装的现有半导体器件的平面图，该封装安放有在高频下工作的半导体芯片。图5中，封装1上中央部位配置有引线框2，周边部位配置有信号端子电极3至信号端子电极7，引线框2上搭载有半导体芯片8。半导体芯片8上设置的芯片电极9至芯片电极13通过导线15分别与信号端子电极3至信号端子电极7连接，半导体芯片8上设置的芯片电极14通过导线15与引线框2连接。相邻信号端子电极4和信号端子电极5之间间隔以及信号端子电极5和信号端子电极6之间间隔分别为0.5mm。
上述现有半导体器件中，为了使封装尺度缩小，考虑使相邻2个信号端子电极如信号端子电极4和信号端子电极5那样互相的间隔变窄。
而使半导体器件在高频下工作时，由于需要对信号端子电极互相之间保证电气隔离，即良好的隔离性，因而必须使相邻信号端子电极互相之间间隔超过规定值。要获得-30dB隔离，需要使信号端子电极互相之间间隔超过0.5mm。
因而，上述半导体器件无法同时满足封装小型化和提高信号端子电极隔离性。
发明内容
本发明目的在于提供一种封装尺度小且信号端子电极隔离性好的半导体器件。
本发明其特征在于，设有防止半导体器件中信号端子电极间电气干扰的屏蔽手段。
本发明半导体器件的一个实施例，在封装上中央部位配置有引线框，在封装上周边部位分别配置有多个信号端子电极，引线框上搭载有半导体芯片，相邻2个信号端子电极之间配置有具有接地电位的接地电极。另一实施例，在封装上中央部位配置有引线框，在封装上周边部位分别配置有多个信号端子电极，引线框上搭载有半导体芯片，引线框上中央部位横跨在半导体芯片上配置有具有接地电位的桥型导电线。由此信号端子电极互相得到电气屏蔽。
本发明第一方面的半导体器件，其特征在于，包括封装；设于所述封装上中央部位的引线框；设于所述封装上周边部位的多个信号端子电极；搭载于所述引线框上的半导体芯片，还设有防止所述信号端子电极间电气干扰的屏蔽手段，所述屏蔽手段由横跨在所述半导体芯片上设于所述引线框上中央位置，具有接地电位的桥型导电线所组成。
附图说明
图1是本发明实施例1半导体器件的平面图。
图2示出的是该半导体器件和现有半导体器件的频率特性。
图3是本发明实施例2半导体器件的平面图。
图4示出的是该半导体器件和现有半导体器件的频率特性。
图5是现有半导体器件的平面图。
具体实施方式
以下说明本发明实施例。
(实施例1)
图1是本发明实施例1半导体器件的平面图。
图1中，封装1上中央部位配置有引线框2，周边部位配置有信号端子电极3至信号端子电极7，引线框2上搭载有半导体芯片8。半导体芯片8上设有芯片电极9至芯片电极14，芯片电极9至芯片电极13通过导线15分别与信号端子电极3至信号端子电极7连接，芯片电极14通过导线15与引线框2连接。信号端子电极4和信号端子电极5之间配置有与引线框2形成为一体的接地电极16，具有接地电位。同样，信号端子电极5和信号端子电极6之间配置有接地电极17。
以下说明上述半导体器件的工作。
由信号端子电极4输入的信号在导线15和芯片电极10上传输，在半导体芯片8内接受放大、衰减等处理，经芯片电极11和导线15从信号端子电极5输出。这时，信号端子电极4和信号端子电极5之间配置有为接地电位的接地电极16，因而信号端子电极4所产生的电磁波被屏蔽，信号端子电极5不易受到信号端子电极4产生的电磁波的影响。同样，信号端子电极5所产生的电磁波也为接地电极16屏蔽。因此，信号端子电极4和信号端子电极5的隔离良好。
图2示出的是现有半导体器件(曲线a)和实施例1半导体器件(曲线b)其频率和隔离性之间的关系。由图2可知，显然具有接地电极16、17的实施例1的半导体器件与现有半导体器件相比，电气隔离性有提高。
上述实施例1中，尽管是对6端子封装例子说明的，但对具有多端子的封装来说，也可获得相同效果。
(实施例2)
图3是本发明实施例2半导体器件的平面图。
实施例2的半导体器件与实施例1半导体器件不同之处在于，不具有接地电极16、17，而在引线框2上的中央部位，设有呈横跨在半导体芯片8上的桥型导电线这种接地导线18，具有接地电位。
这种半导体器件，接地导线18对信号端子电极3和信号端子电极7所产生的电磁波具有屏蔽作用，因而信号端子电极4至信号端子电极6的隔离性提高，反之，对于信号端子电极3和信号端子电极7的隔离性来说，也有提高。
图4示出的是现有半导体器件(曲线a)和实施例2半导体器件(曲线b)其频率和隔离性之间的关系。由图4可知，显然具有接地导线18的实施例2的半导体器件与现有半导体器件相比，隔离性有提高。
综上所述，本发明通过在半导体器件封装上中央部位配置引线框，周边部位分别配置多个信号端子电极，在引线框上搭载半导体芯片，在相邻2个信号端子电极之间配置具有接地电位的接地电极，可获得小型、电气干扰少的半导体器件。

Claims (1)

1.一种半导体器件，其特征在于，包括封装；设于所述封装上中央部位的引线框；设于所述封装上周边部位的多个信号端子电极；搭载于所述引线框上的半导体芯片，还设有防止所述信号端子电极间电气干扰的屏蔽手段，所述屏蔽手段由横跨在所述半导体芯片上设于所述引线框上中央位置，具有接地电位的桥型导电线所组成。
CNB981052975A 1997-03-04 1998-02-27 半导体器件 Expired - Fee Related CN1154182C (zh)

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JP9048664A JPH10247717A (ja) 1997-03-04 1997-03-04 半導体装置
JP48664/1997 1997-03-04
JP48664/97 1997-03-04

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CN1154182C true CN1154182C (zh) 2004-06-16

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CN100382295C (zh) * 2003-06-10 2008-04-16 矽品精密工业股份有限公司 可提高接地品质的半导体封装件及其导线架
EP1746648A3 (en) * 2005-07-22 2008-09-03 Marvell World Trade Ltd. Packaging for high speed integrated circuits
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