CN104505378A - 引线框架和半导体封装体 - Google Patents

引线框架和半导体封装体 Download PDF

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CN104505378A
CN104505378A CN201410778609.1A CN201410778609A CN104505378A CN 104505378 A CN104505378 A CN 104505378A CN 201410778609 A CN201410778609 A CN 201410778609A CN 104505378 A CN104505378 A CN 104505378A
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lead frame
raised line
supporting disk
semiconductor package
pin array
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周素芬
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Ase Assembly & Test (shanghai) Ltd
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    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
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    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
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    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
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    • H01L2224/45001—Core members of the connector
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    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
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    • H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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Abstract

本发明涉及引线框架和半导体封装体。一种引线框架包括：支撑盘，其经配置为承载晶片；位于所述支撑盘周围的至少一个引脚阵列，其经配置为连接至承载于所述支撑盘的晶片；连接于所述支撑盘的一个或多个凸条，其延伸到所述至少一个引脚阵列中。本发明中的至少部分技术方案对集成电路芯片的不同线路信号起到了良好的屏蔽作用，这尤其对于医疗仪器、汽车、测试设备、航天航空等领域的应用是有利的。

Description

引线框架和半导体封装体
技术领域
本发明大体上涉及芯片封装，更具体地，涉及引线框架(Lead Frame)结构的封装。
背景技术
引线框架作为集成电路的芯片载体，是一种借助于键合材料(金丝、铜丝、铝丝)实现芯片内部电路引出端与外引线的电性连接，形成电性回路的关键结构件，它起到了和外部导线连接的桥梁作用。大部分的半导体集成块中都使用引线框架，它是电子信息产业中重要的基础材料。
发明内容
集成电路集成度越来越高，芯片的I/O线越来越多。芯片的速度越来越快，功率也越来越大。在高频电路中，寄生电容和电感的影响较大，在控制系统中为了减少信号中电容耦合噪声、准确检测和控制，现有的引线框架和半导体封装技术仍有待进一步改进。
在本发明的一个实施例中，揭示了一种引线框架，该引线框架包括：支撑盘，其经配置为承载晶片；位于所述支撑盘周围的至少一个引脚阵列，其经配置为连接至承载于所述支撑盘的晶片；连接于所述支撑盘的一个或多个凸条，其延伸到所述至少一个引脚阵列中。
在本发明的另一个实施例中，揭示了一种半导体封装体，该半导体封装体包括：支撑盘；晶片，其承载于所述支撑盘之上；位于所述支撑盘周围的至少一个引脚阵列，其经配置为电性连接至所述晶片；连接于所述支撑盘的一个或多个凸条，其延伸到所述至少一个引脚阵列中；封装材料，其包覆所述晶片、所述至少一个引脚阵列、以及所述一个或多个凸条。
在上述引线框架或半导体封装体的一些具体实施例中，所述一个或多个凸条中的至少一者的厚度大于所述至少一个引脚阵列的厚度。
在上述引线框架或半导体封装体的一些具体实施例中，所述一个或多个凸条中的至少一者在相邻引脚阵列中的延伸长度超过引脚长度的一半。
在上述引线框架或半导体封装体的一些具体实施例中，所述一个或多个凸条中的至少一者具有包覆层，所述包覆层的导电率高于所述至少一个引脚阵列的导电率。
在上述引线框架或半导体封装体的一些具体实施例中，所述一个或多个凸条中的至少一者设置于电源引脚旁边。
在上述引线框架或半导体封装体的一些具体实施例中，所述一个或多个凸条中的至少一者在与所述支撑盘连接处加粗。
本发明中的至少部分技术方案对集成电路芯片的不同线路信号起到了良好的屏蔽作用，这尤其对于医疗仪器、汽车、测试设备、航天航空等领域的应用是有利的。
附图说明
结合附图，以下关于本发明的优选实施例的详细说明将更易于理解。本发明以举例的方式予以说明，并非受限于附图，附图中类似的附图标记指示相似的元件。
图1是一个引线框架的平面布局示意图；
图2A示出了一个实施例的引线框架的局部200；
图2B放大示出了图2A的局部；
图3示出了另一个实施例的引线框架的局部300；
图4示出了另一个实施例的引线框架在附着晶片和引线接合之后的局部400。
具体实施方式
附图的详细说明意在作为本发明的当前优选实施例的说明，而非意在代表本发明能够得以实现的仅有形式。应理解的是，相同或等同的功能可以由意在包含于本发明的精神和范围之内的不同实施例完成。
图1是一个引线框架10的平面布局示意图。引线框架10包括支撑盘102所组成的阵列。引脚104的阵列排布于支撑盘102的周围。引脚阵列通过连筋106连接在一起。连筋106互相连接形成网格型的框架，从而使引线框架10构成一个整体。支撑盘102通过支撑杆103连接到框架。应理解的是，图1仅意在示意性地表达支撑盘102、支撑杆103、引脚104的阵列、连筋106之间的相对位置关系，而非意在精确地显示各部件的尺寸比例。引线框架10适合作为整体与其他部件(如晶片等)封装，例如包括：将晶片安装于支撑盘102上，将晶片与引脚104进行电性连接，灌胶封装后切单(Singulation)去除连筋106可形成各个独立的半导体封装体。引线框架10例如但不限于是由金属、合金等导电性材料制成的。
图2A示出了一个实施例的引线框架的局部200。该引线框架包括网格型的框架，而局部200位于其中的一个网格。图中所示支撑盘201大体上呈方形，并经由四个角上的支撑杆211、212、213和214连接到网格的边框。引脚阵列221、222、223和224分布于支撑盘201的周围，其经配置为电性连接至承载于支撑盘201的晶片。凸条231、232和233连接于支撑盘201，其中，凸条231和232延伸到引脚阵列221中，凸条233延伸到引脚阵列223中。支撑盘201通常兼用做接地，凸条231、232和233因而也是接地导体，其延伸于引脚阵列之中可以隔离两侧引脚的信号辐射造成的相互干扰。连筋206将相邻网格的引脚阵列连接在一起。虚线框203示出了灌胶封装的范围。完成灌胶封装后，切单去除连筋并断开支撑杆211至214与网格边框的连接，从而形成独立的半导体封装体。根据封装的具体类型，可能还包括弯曲引脚在灌胶区域以外的部分的步骤。
图2B放大地示出了图2A的局部。如图所示，凸条231、232在相邻引脚阵列中的延伸长度超过了引脚长度的一半甚至是2/3。绝缘胶带208用于将凸条231、232与相邻引脚阵列221固定在一起，以保证整体的平整度。灌胶封装时可以连同绝缘胶条208一起包覆于封装材料之中。
图3示出了另一个实施例的引线框架的局部300。该引线框架的结构与图2A和图2B所示实施例大体上类似。在凸条331和332与支撑盘301的连接处加粗。
图4示出了另一个实施例的引线框架在附着晶片(die bonding)和引线接合(wirebonding)之后的局部400。该引线框架包括网格型的框架，而局部400位于其中的一个网格。图中所示支撑盘401大体上呈方形，并经由四个角上的支撑杆411、412、413和414连接到网格的边框。引脚阵列421、422、423和424分布于支撑盘401的周围。晶片409附着于支撑盘401之上。晶片409和引脚阵列421、422、423、424之间通过引线(例如金丝、铜丝)键合。凸条431和432连接于支撑盘401，并且延伸到引脚阵列423中。凸条431、432在相邻引脚阵列中的延伸长度超过了引脚长度的一半。支撑盘401通常兼用做接地，凸条431和432因而也是接地导体，其延伸于引脚阵列之中可以隔离两侧引脚的信号辐射造成的相互干扰。连筋406将相邻网格的引脚阵列连接在一起。线框403示出了灌胶封装的范围。完成灌胶封装后，切单去除连筋并断开支撑杆411至414与网格边框的连接，从而形成独立的半导体封装体。根据封装的具体类型，可能还包括弯曲引脚在灌胶区域以外的部分的步骤。
在上述引线框架或半导体封装体的一些变化例中，凸条中的至少一者的厚度大于引脚阵列的厚度，以更好地隔离两侧引脚的信号之间的相互干扰。
在上述引线框架或半导体封装体的另一些变化例中，凸条中的至少一者具有包覆层，且包覆层的导电率高于引脚阵列的导电率。例如，引线框架由铁或者铁合金材料制成，凸条的包覆层为铜材料。
在上述引线框架或半导体封装体的又一些变化例中，凸条中的至少一者设置于电源引脚旁边。由于电源引脚的信号强度较大，辐射较强，旁边设置接地凸条有利于隔离或者减弱电源引脚的信号对其他引脚的干扰。
尽管已经阐明和描述了本发明的不同实施例，本发明并不限于这些实施例。仅在某些权利要求或实施例中出现的技术特征并不意味着不能与其他权利要求或实施例中的其他特征相结合以实现有益的新的技术方案。在不背离如权利要求书所描述的本发明的精神和范围的情况下，许多修改、改变、变形、替代以及等同对于本领域技术人员而言是明显的。

Claims (12)

1.一种引线框架，其特征在于，该引线框架包括：
支撑盘，其经配置为承载晶片；
位于所述支撑盘周围的至少一个引脚阵列，其经配置为连接至承载于所述支撑盘的晶片；
连接于所述支撑盘的一个或多个凸条，其延伸到所述至少一个引脚阵列中。
2.如权利要求1所述的引线框架，其特征在于，所述一个或多个凸条中的至少一者的厚度大于所述至少一个引脚阵列的厚度。
3.如权利要求1所述的引线框架，其特征在于，所述一个或多个凸条中的至少一者在相邻引脚阵列中的延伸长度超过引脚长度的一半。
4.如权利要求1所述的引线框架，其特征在于，所述一个或多个凸条中的至少一者具有包覆层，所述包覆层的导电率高于所述至少一个引脚阵列的导电率。
5.如权利要求1所述的引线框架，其特征在于，所述一个或多个凸条中的至少一者设置于电源引脚旁边。
6.如权利要求1所述的引线框架，其特征在于，所述一个或多个凸条中的至少一者在与所述支撑盘连接处加粗。
7.一种半导体封装体，其特征在于，该半导体封装体包括：
支撑盘；
晶片，其承载于所述支撑盘之上；
位于所述支撑盘周围的至少一个引脚阵列，其经配置为电性连接至所述晶片；
连接于所述支撑盘的一个或多个凸条，其延伸到所述至少一个引脚阵列中；
封装材料，其包覆所述晶片、所述至少一个引脚阵列、以及所述一个或多个凸条。
8.如权利要求7所述的半导体封装体，其特征在于，所述一个或多个凸条中的至少一者的厚度大于所述至少一个引脚阵列的厚度。
9.如权利要求7所述的半导体封装体，其特征在于，所述一个或多个凸条中的至少一者在相邻引脚阵列中的延伸长度超过引脚长度的一半。
10.如权利要求7所述的半导体封装体，其特征在于，所述一个或多个凸条中的至少一者具有包覆层，所述包覆层的导电率高于所述至少一个引脚阵列的导电率。
11.如权利要求7所述的半导体封装体，其特征在于，所述一个或多个凸条中的至少一者设置于电源引脚旁边。
12.如权利要求7所述的半导体封装体，其特征在于，所述一个或多个凸条中的至少一者在与所述支撑盘连接处加粗。
CN201410778609.1A 2014-12-15 2014-12-15 引线框架和半导体封装体 Pending CN104505378A (zh)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1192582A (zh) * 1997-03-04 1998-09-09 松下电子工业株式会社 半导体器件
US20030160320A1 (en) * 2002-02-26 2003-08-28 Wen-Lo Shieh High heat dissipation micro-packaging body for semiconductor chip
US20030201529A1 (en) * 2002-04-24 2003-10-30 Do-Soo Jeong Package stacked semiconductor device having pin linking means
CN103715163A (zh) * 2013-12-31 2014-04-09 日月光封装测试(上海)有限公司 引线框架及半导体封装
CN204315564U (zh) * 2014-12-15 2015-05-06 日月光封装测试(上海)有限公司 引线框架和半导体封装体

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1192582A (zh) * 1997-03-04 1998-09-09 松下电子工业株式会社 半导体器件
US20030160320A1 (en) * 2002-02-26 2003-08-28 Wen-Lo Shieh High heat dissipation micro-packaging body for semiconductor chip
US20030201529A1 (en) * 2002-04-24 2003-10-30 Do-Soo Jeong Package stacked semiconductor device having pin linking means
CN103715163A (zh) * 2013-12-31 2014-04-09 日月光封装测试(上海)有限公司 引线框架及半导体封装
CN204315564U (zh) * 2014-12-15 2015-05-06 日月光封装测试(上海)有限公司 引线框架和半导体封装体

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