CN115223964A - 半导体装置及半导体装置的制造方法 - Google Patents

半导体装置及半导体装置的制造方法 Download PDF

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Publication number
CN115223964A
CN115223964A CN202210391309.2A CN202210391309A CN115223964A CN 115223964 A CN115223964 A CN 115223964A CN 202210391309 A CN202210391309 A CN 202210391309A CN 115223964 A CN115223964 A CN 115223964A
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circuit pattern
paste material
semiconductor device
paste
chip
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江口佳佑
益本宽之
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Abstract

涉及半导体装置及其制造方法。目的在于提供在半导体装置中能够确保针对功率半导体芯片的散热性且实现小型化的技术。半导体装置具有：金属板(1)；绝缘图案(2)，设置于金属板(1)之上；功率电路图案(3a)及信号电路图案(3b)，设置于绝缘图案(2)之上；功率半导体芯片(5a～5f)，搭载于功率电路图案(3a)之上；以及控制半导体芯片(6a～6d)，搭载于信号电路图案(3b)之上，并且对功率半导体芯片(5a～5f)进行控制，功率半导体芯片(5a～5f)通过铜制的第一芯片键合材料(4a)与功率电路图案(3a)接合，控制半导体芯片(6a～6d)通过第二芯片键合材料(4b)与信号电路图案(3b)接合。

Description

半导体装置及半导体装置的制造方法
技术领域
本发明涉及半导体装置及半导体装置的制造方法。
背景技术
当前，将功率半导体芯片、对功率半导体芯片进行控制的控制半导体芯片单一模块化后的半导体装置已实现了产品化。在这样的半导体装置中还谋求进一步的小型化。
例如，在专利文献1中公开了如下半导体装置，即，通过引线框等薄的金属板构成了将功率半导体芯片及控制半导体芯片接合的电路图案。通过使电路图案的厚度薄化，从而能够实现半导体装置的小型化。
专利文献1：日本特开2013-149779号公报
但是，就专利文献1所记载的半导体装置而言，由于电路图案由引线框等薄的金属板构成，因此电路图案的导热性降低。其结果，存在针对功率半导体芯片的散热性恶化这样的问题。
发明内容
因此，本发明的目的在于提供在半导体装置中，能够确保针对功率半导体芯片的散热性，并且能够实现小型化的技术。
本发明涉及的半导体装置具有：金属板；绝缘图案，其设置于所述金属板之上；电路图案，其设置于所述绝缘图案之上；功率半导体芯片，其搭载于所述电路图案之上；以及控制半导体芯片，其搭载于所述电路图案之上，并且对所述功率半导体芯片进行控制，所述功率半导体芯片通过铜制的第一芯片键合材料与所述电路图案接合，所述控制半导体芯片通过第二芯片键合材料与所述电路图案接合。
发明的效果
根据本发明，由于将铜制的第一芯片键合材料用于功率半导体芯片与电路图案的接合，因此与以往的使用了焊料的情况相比，针对功率半导体芯片的散热性提高。其结果，在使电路图案薄化的情况下也能够确保针对功率半导体芯片的散热性。由此，能够确保针对功率半导体芯片的散热性，并且实现半导体装置的小型化。
附图说明
图1是表示实施方式1涉及的半导体装置的构造的俯视图。
图2是图1的A-A线剖视图。
图3是实施方式1涉及的半导体装置的电路图。
图4是表示实施方式1涉及的半导体装置的制造方法的剖视图。
图5是表示实施方式1的变形例1涉及的半导体装置的制造方法的剖视图。
图6是表示实施方式1的变形例2涉及的半导体装置的制造方法的剖视图。
图7是表示实施方式2涉及的半导体装置的构造的俯视图。
图8是图7的B-B线剖视图。
图9是实施方式2的变形例中的与图8相当的图。
图10是表示实施方式2的变形例涉及的半导体装置的制造方法的剖视图。
具体实施方式
<实施方式1>
<半导体装置的构造＞
下面使用附图对实施方式1进行说明。图1是表示实施方式1涉及的半导体装置的构造的俯视图。图2是图1的A-A线剖视图。
如图1和图2所示，半导体装置具有金属板1、绝缘图案2、多个功率电路图案3a、多个信号电路图案3b、多个(例如6个)功率半导体芯片5a～5f、多个(例如4个)控制半导体芯片6a～6d、P电极8、U电极9、V电极10、W电极11、N电极12、多个信号端子13、多个铝导线14、壳体15。
金属板1是用于将由功率半导体芯片5a～5f产生的热量进行散热的部件。绝缘图案2由陶瓷或树脂等构成，设置于金属板1的上表面整体。绝缘图案2可以为1个，也可以被分割为多个。此外，金属板1和绝缘图案2也可以经由焊料进行接合。
多个功率电路图案3a设置于绝缘图案2的上表面的功率侧(图1的纸面的下侧)。多个信号电路图案3b设置于绝缘图案2的上表面的信号侧(图1的纸面的上侧)。这里，功率电路图案3a和信号电路图案3b相当于电路图案。另外，在不对功率电路图案3a和信号电路图案3b进行区分时，也简称为电路图案。
功率半导体芯片5a～5f例如是将开关部和续流部单芯片化后的RC-IGBT(ReverseConducting insulated gate bipolar transistor)，搭载于功率电路图案3a之上。功率半导体芯片5a～5f通过铜制的第一芯片键合材料4a与功率电路图案3a进行接合。
以往，将材料成本低廉的焊料用于功率半导体芯片和功率电路图案的接合，但在本实施方式中，为了使针对功率半导体芯片5a～5f的散热性提高而使用铜制的第一芯片键合材料4a。
这里，功率半导体芯片5a～5f也称为第一RC-IGBT 5a～第六RC-IGBT 5f。在图1中，将功率半导体芯片5a～5f表示为第一RC-IGBT 5a～第六RC-IGBT 5f。
此外，功率半导体芯片5a～5f也可以是开关部和续流部分离的IGBT芯片和二极管芯片。
另外，金属板1、绝缘图案2和电路图案也可以是一体地构成的树脂绝缘基板。在该情况下，作为树脂绝缘基板的电路图案，也可以采用对于铜制的第一芯片键合材料4a的接触热阻优异的铜制的电路图案。
控制半导体芯片6a～6d是对功率半导体芯片5a～5f进行控制的控制用的半导体芯片，搭载于信号电路图案3b之上。控制半导体芯片6a～6d通过第二芯片键合材料4b与信号电路图案3b进行接合。作为第二芯片键合材料4b，使用焊料。此外，控制半导体芯片6a～6d也称为第一IC芯片6a～第四IC芯片6d。
另外，作为第二芯片键合材料4b，也可以替代焊料，而使用铜制的芯片键合材料、银芯片键合材料或硅酮粘接剂等非导电性的芯片键合材料。
壳体15形成为将金属板1、绝缘图案2、功率电路图案3a、信号电路图案3b、功率半导体芯片5a～5f及控制半导体芯片6a～6d的侧面包围。
P电极8、U电极9、V电极10、W电极11及N电极12设置于壳体15的功率侧，与功率电路图案3a通过铝导线14进行连接。另外，信号端子13设置于壳体15的信号侧，与信号电路图案3b通过铝导线14进行连接。
接下来，使用图3对半导体装置的电路结构进行说明。图3是实施方式1涉及的半导体装置的电路图。此外，在图3中，将控制半导体芯片6a～6d表示为第一IC芯片6a～第四IC芯片6d。
如图3所示，控制半导体芯片6a～6d为了使输出相及上下桥臂不同的功率半导体芯片5a～5f得到驱动而设置为与各相成对。但是，由于控制半导体芯片6d成为对功率半导体芯片5d～5f进行驱动的电路结构，因此控制半导体芯片6d被单芯片化。
此外，控制半导体芯片6d也可以由3个控制半导体芯片构成，以使得单独地对功率半导体芯片5d～5f进行驱动。
<半导体装置的制造方法>
接下来，使用图4对半导体装置的制造方法进行说明。图4(a)～(c)是表示实施方式1涉及的半导体装置的制造方法的剖视图。此外，在图4(a)～(c)中仅示出功率半导体芯片5b，没有示出功率半导体芯片5a、5c～5f，但它们通过相同的方法进行接合，因此这里对功率半导体芯片5a、5c～5f的接合省略说明。
首先，准备在绝缘图案2之上设置有功率电路图案3a和信号电路图案3b的金属板1。如图4(a)所示，在功率电路图案3a之上配置丝网印刷用的掩模16。此时，虽然未图示，但掩模16也配置于信号电路图案3b之上。然后，使用刮板17，使第一糊状材料14a流入至功率电路图案3a中的从掩模16露出的部位。另外，虽然未图示，但使第二糊状材料流入至信号电路图案3b中的从掩模16露出的部位。
接下来，如图4(b)所示，通过将掩模16除去，从而完成第一糊状材料14a的涂敷和未图示的第二糊状材料的涂敷。
这里，第一糊状材料14a是第一芯片键合材料4a固化前的状态，具体而言是铜糊状材料。另外，第二糊状材料是第二芯片键合材料4b固化前的状态，具体而言是焊料糊状材料。
接下来，将功率半导体芯片5b搭载于第一糊状材料14a之上。另外，虽然未图示，但在第二糊状材料之上搭载控制半导体芯片6a～6d。然后，进行加热处理，使第一糊状材料14a固化，从而如图4(c)所示，形成第一芯片键合材料4a，通过第一芯片键合材料4a将功率半导体芯片5b接合于功率电路图案3a。另外，虽然未图示，但通过利用上述加热处理使第二糊状材料固化，从而形成第二芯片键合材料4b，通过第二芯片键合材料4b将控制半导体芯片6a～6d与信号电路图案3b接合。
在上面，以相同工序对第一糊状材料14a和第二糊状材料14b进行了加热处理。但是，由于第一糊状材料14a为铜糊状材料，第二糊状材料14b为焊料糊状材料，因此第二糊状材料14b的固化温度比第一糊状材料14a的固化温度低。因此，也可以通过不同的工序对第一糊状材料14a和第二糊状材料14b进行加热处理。
图5(a)～(f)是表示实施方式1的变形例1涉及的半导体装置的制造方法的剖视图。此外，在图5(a)～(f)中仅示出功率半导体芯片5b和控制半导体芯片6b，没有示出功率半导体芯片5a、5c～5f及控制半导体芯片6a、6c、6d，但功率半导体芯片5a～5f通过相同的方法进行接合，另外，控制半导体芯片6a～6d通过相同的方法进行接合，因此这里对功率半导体芯片5a、5c～5f及控制半导体芯片6a、6c、6d的接合省略说明。
如图5(a)所示，在电路图案之上配置丝网印刷用的掩模16。然后，使用刮板17，使第二糊状材料14b流入至信号电路图案3b中的从掩模16露出的部位。
接下来，如图5(b)所示，通过将掩模16除去，从而完成第二糊状材料14b的涂敷。
接下来，将控制半导体芯片6b搭载于第二糊状材料14b之上。然后，通过以比第一糊状材料14a低的温度进行加热处理，使第二糊状材料14b固化，从而如图5(c)所示，形成第二芯片键合材料4b，通过第二芯片键合材料4b将控制半导体芯片6b接合于信号电路图案3b。
接下来，如图5(d)所示，在电路图案之上配置丝网印刷用的掩模16。此时，掩模16配置为将控制半导体芯片6b覆盖。然后，使用刮板17，使第一糊状材料14a流入至功率电路图案3a中的从掩模16露出的部位。
接下来，如图5(e)所示，通过将掩模16除去，从而完成第一糊状材料14a的涂敷。
接下来，将功率半导体芯片5b搭载于第一糊状材料14a之上。然后，通过以比第二糊状材料14b高的温度进行加热处理，使第一糊状材料14a固化，从而如图5(f)所示，形成第一芯片键合材料4a，通过第一芯片键合材料4a将功率半导体芯片5b接合于功率电路图案3a。
在上述两种制造方法中，第一糊状材料14a以上表面为平面状的方式进行涂敷。但是，在向第一糊状材料14a搭载功率半导体芯片5b时，由于功率半导体芯片5b被压入至第一糊状材料14a，因此存在产生第一糊状材料14a的攀升的情况。为了抑制这样的情况，也可以进行第一糊状材料14a的成形。图6(a)～(e)是表示实施方式1的变形例2涉及的半导体装置的制造方法的剖视图。
此外，在图6(a)～(e)中仅示出功率半导体芯片5b，没有示出功率半导体芯片5a、5c～5f，但它们通过相同的方法进行接合，因此这里对功率半导体芯片5a、5c～5f的接合省略说明。另外，由于通过与图4(a)～(c)的情况相同的方法对控制半导体芯片6a～6d进行接合，因此省略它们的说明。
如图6(a)所示，在功率电路图案3a之上配置丝网印刷用的掩模16。然后，使用刮板17，使第一糊状材料14a流入至功率电路图案3a中的从掩模16露出的部位。
接下来，如图6(b)所示，通过将掩模16除去，从而完成第一糊状材料14a的涂敷。
接下来，如图6(c)所示，在涂敷于功率电路图案3a之上的第一糊状材料14a之上配置成形用的掩模18。掩模18的俯视轮廓形成为与涂敷于功率电路图案3a之上的第一糊状材料14a的俯视轮廓相同的大小。在掩模18的下表面处的除了外周部之外的部分，即掩模18的下表面处的内周部形成有向上方凹陷的凹陷部18a。通过将凹陷部18a配置于第一糊状材料14a之上，从而使第一糊状材料14a成形。通过将掩模18除去，从而如图6(d)所示，成为第一糊状材料14a的除了外周部之外的部分，即第一糊状材料14a的内周部向上方凸出的形状。
接下来，将功率半导体芯片5b搭载于第一糊状材料14a之上。此时，虽然未图示，但功率半导体芯片5b被压入至第一糊状材料14a的向上方凸出的部分。由于与第一糊状材料14a的向上方凸出的部分相比外周侧的部分向下方凹陷，因此通过压入功率半导体芯片5b，从而使第一糊状材料14a的上表面整体变得平坦。其结果，能够对第一糊状材料14a的攀升进行抑制。
接下来，进行加热处理，使第一糊状材料14a固化，从而如图6(e)所示，形成第一芯片键合材料4a，通过第一芯片键合材料4a将功率半导体芯片5b接合于功率电路图案3a。
此外，也可以将实施方式1的变形例2中的第一糊状材料14a的成形用于实施方式1的变形例1。
<效果>
如上所述，实施方式1涉及的半导体装置具有：金属板1；绝缘图案2，其设置于金属板1之上；功率电路图案3a及信号电路图案3b，它们设置于绝缘图案2之上；功率半导体芯片5a～5f，其搭载于功率电路图案3a之上；以及控制半导体芯片6a～6d，其搭载于信号电路图案3b之上，并且对功率半导体芯片5a～5f进行控制，功率半导体芯片5a～5f通过铜制的第一芯片键合材料4a与功率电路图案3a进行接合，控制半导体芯片6a～6d通过第二芯片键合材料4b与信号电路图案3b进行接合。
因此，由于将铜制的第一芯片键合材料4a用于功率半导体芯片5a～5f与功率电路图案3a的接合，因此与以往的使用了焊料的情况相比，针对功率半导体芯片5a～5f的散热性提高。其结果，在使功率电路图案3a薄化的情况下也能够确保针对功率半导体芯片5a～5f的散热性。由此，能够确保针对功率半导体芯片5a～5f的散热性，并且实现半导体装置的小型化。
另外，金属板1、绝缘图案2、功率电路图案3a和信号电路图案3b构成为一体。
在绝缘图案2由陶瓷构成的情况下，陶瓷为对于位移来说脆弱的脆性材料，为了在驱动半导体装置时抑制由金属板1的变形引起的影响，有时将绝缘图案2分为多个。在金属板1、绝缘图案2、功率电路图案3a和信号电路图案3b构成为一体的树脂绝缘基板的情况下，即使不将绝缘图案分割成多个，也能够抑制由金属板1的变形引起的影响。因此，能够提高半导体装置的设计布局的自由度，实现半导体装置的进一步小型化。
另外，实施方式1涉及的半导体装置的制造方法具有：工序(a)，在功率电路图案3a之上涂敷第一芯片键合材料4a的固化前的状态即第一糊状材料14a，在信号电路图案3b之上涂敷第二芯片键合材料4b的固化前的状态即第二糊状材料14b；工序(b)，将功率半导体芯片5a～5f搭载于第一糊状材料14a之上，将控制半导体芯片6a～6d搭载于第二糊状材料14b之上；以及工序(c)，使第一糊状材料14a和第二糊状材料14b固化。
因此，通过进行丝网印刷，从而能够集中地进行针对各相的功率半导体芯片5a～5f的第一糊状材料14a的涂敷，因此能够使半导体装置的生产率提高。
另外，实施方式1的变形例1涉及的半导体装置的制造方法具有：工序(h)，在信号电路图案3b之上涂敷第二芯片键合材料4b的固化前的状态即第二糊状材料14b；工序(i)，将控制半导体芯片6a～6d搭载于第二糊状材料14b之上；工序(j)，使第二糊状材料14b固化；工序(k)，在功率电路图案3a之上涂敷第一芯片键合材料4a的固化前的状态即第一糊状材料14a；工序(l)，将功率半导体芯片5a～5f搭载于第一糊状材料14a之上；以及工序(m)，使第一糊状材料14a固化，第二糊状材料14b的固化温度低于第一糊状材料14a的固化温度。
因此，能够使第二糊状材料14b的固化时间比第一糊状材料14a的固化时间短，所以能够使半导体装置的生产率提高。
另外，实施方式1的变形例2涉及的半导体装置的制造方法在工序(a)和工序(b)之间、或工序(k)和工序(l)之间还具有工序(n)，在该工序(n)中，以与第一糊状材料14a的内周部相比第一糊状材料14a的外周部向下方凹陷的方式进行第一糊状材料14a的成形。
在将功率半导体芯片5a～5f搭载于第一糊状材料14a之上时，功率半导体芯片5a～5f被压入至第一糊状材料14a的向上方凸出的部分。由于与第一糊状材料14a的向上方凸出的部分相比外周侧的部分向下方凹陷，因此第一糊状材料14a的上表面整体变得平坦。其结果，能够对第一糊状材料14a的攀升进行抑制。
<实施方式2>
<半导体装置的构造＞
接下来，对实施方式2涉及的半导体装置进行说明。图7是表示实施方式2涉及的半导体装置的构造的俯视图。图8是图7的B-B线剖视图。此外，在实施方式2中，对与实施方式1中说明过的结构要素相同的结构要素标注相同标号并省略说明。
如图7和图8所示，在实施方式2中，半导体装置还具有搭载于信号电路图案3b之上的电容性部件7a～7d。电容性部件7a～7d例如为电容器。
电容性部件7a～7d通过铜制的第三芯片键合材料4c与两个信号电路图案3b进行接合，配置为分别与控制半导体芯片6a～6d成对。这里，第三芯片键合材料4c的厚度与第一芯片键合材料4a的厚度相同。另外，电容性部件7a～7d通过铝导线14与功率半导体芯片5a～5f电连接。
通过设置有电容性部件7a～7d，从而在半导体装置驱动时发生了电压下降的情况下能够从电容性部件7a～7d向功率半导体芯片5a～5f供给稳定的电压。
此外，也可以使第一芯片键合材料4a的厚度形成得比第三芯片键合材料4c的厚度厚。图9是实施方式2的变形例中的与图8相当的图。
如图9所示，通过将功率半导体芯片5b正下方的第一芯片键合材料4a的厚度设得厚，从而能够使半导体装置的散热性进一步提高。
<半导体装置的制造方法>
接下来，对半导体装置的制造方法进行说明。如图8所示，在第三芯片键合材料4c的厚度与第一芯片键合材料4a的厚度相同的情况下，在图4(a)～(c)中，通过与功率半导体芯片5a～5f相同的工序，将第三芯片键合材料4c的固化前的状态即第三糊状材料进行涂敷，在搭载了电容性部件7a～7d后，使第三糊状材料14c固化。因此，对图8的情况省略说明。
这里，使用图10，对图9所示的实施方式2的变形例涉及的半导体装置的制造方法进行说明。图10(a)～(d)是表示实施方式2的变形例涉及的半导体装置的制造方法的剖视图。
此外，在图10(a)～(d)中仅示出功率半导体芯片5b和电容性部件7b，没有示出功率半导体芯片5a、5c～5f及电容性部件7a、7c、7d，但功率半导体芯片5a～5f通过相同的方法进行接合，另外，电容性部件7a～7d通过相同的方法进行接合，因此对功率半导体芯片5a、5c～5f的接合及电容性部件7a、7c、7d的接合省略说明。
如图10(a)所示，在电路图案之上配置丝网印刷用的掩模16。然后，使用刮板17，使第三糊状材料14c流入至信号电路图案3b的从掩模16露出的部位中的搭载电容性部件7b的部位。另外，虽然未图示，但第二糊状材料流入至信号电路图案3b的从掩模16露出的部位中的搭载控制半导体芯片6a～6d的部位。然后，通过将掩模16除去，从而完成第三糊状材料14c的涂敷和未图示的第二糊状材料的涂敷。
接下来，如图10(b)所示，在电路图案之上配置厚度比掩模16厚的丝网印刷用的掩模16a。然后，使用刮板17，使第一糊状材料14a流入至功率电路图案3a中的从掩模16a露出的部位。然后，通过将掩模16a除去，从而完成第一糊状材料14a的涂敷。
接下来，如图10(c)所示，将功率半导体芯片5b搭载于第一糊状材料14a之上，将电容性部件7b搭载于第三糊状材料14c之上。另外，虽然未图示，但在第二糊状材料之上搭载控制半导体芯片6a～6d。
然后，进行加热处理，使第一糊状材料14a和第三糊状材料14c固化，从而如图10(d)所示，形成第一芯片键合材料4a和第三芯片键合材料4c。由此，通过第一芯片键合材料4a将功率半导体芯片5b与功率电路图案3a接合，通过第三芯片键合材料4c将电容性部件7b与信号电路图案3b接合。另外，虽然未图示，但通过利用上述加热处理使第二糊状材料固化，从而形成第二芯片键合材料4b，通过第二芯片键合材料4b将控制半导体芯片6a～6d与信号电路图案3b接合。
<效果>
如上所述，实施方式2涉及的半导体装置还具有搭载于信号电路图案3b之上且与功率半导体芯片5a～5f电连接的电容性部件7a～7d，电容性部件7a～7d通过铜制的第三芯片键合材料4c与信号电路图案3b进行接合。
因此，在半导体装置驱动时发生了电压下降的情况下能够从电容性部件7a～7d向功率半导体芯片5a～5f供给稳定的电压。由此，能够提高半导体装置的可靠性。
另外，由于第一芯片键合材料4a的厚度比第三芯片键合材料4c的厚度厚，因此能够使半导体装置的散热性提高。此时，还能够实现电容性部件7a～7d正下方的信号电路图案3b的微小化，因此有助于半导体装置的小型化。
另外，实施方式2的变形例涉及的半导体装置的制造方法具有：工序(d)，在信号电路图案3b之上，将第二芯片键合材料4b的固化前的状态即第二糊状材料14b和第三芯片键合材料4c的固化前的状态即第三糊状材料14c涂敷得比第一芯片键合材料4a的固化前的状态即第一糊状材料14a的厚度薄；工序(e)，在功率电路图案3a之上涂敷第一糊状材料14a；工序(f)，将功率半导体芯片5a～5f搭载于第一糊状材料14a之上，将控制半导体芯片6a～6d搭载于第二糊状材料14b之上，将电容性部件7a～7d搭载于第三糊状材料14c之上；以及工序(g)，使第一糊状材料14a、第二糊状材料14b和第三糊状材料14c固化。
因此，通过将丝网印刷分为两次，从而能够涂敷厚度不同的糊状材料，因此能够容易地制造提高了散热性的半导体装置。
此外，也可以将实施方式1的变形例2中的第一糊状材料14a的成形用于实施方式2和其变形例。即，在工序(e)和工序(f)之间还具有工序(n)，在该工序(n)中，以与第一糊状材料14a的内周部相比第一糊状材料14a的外周部向下方凹陷的方式进行第一糊状材料14a的成形。由此，能够对第一糊状材料14a的攀升进行抑制。
此外，可以将各实施方式自由地组合，对各实施方式适当进行变形、省略。
标号的说明
1金属板，2绝缘图案，3a功率电路图案，3b信号电路图案，4a第一芯片键合材料，4b第二芯片键合材料，4c第三芯片键合材料，5a～5f功率半导体芯片，6a～6d控制半导体芯片，7a～7d电容性部件，14a第一糊状材料，14b第二糊状材料，14c第三糊状材料。

Claims (8)

1.一种半导体装置，其具有：
金属板；
绝缘图案，其设置于所述金属板之上；
电路图案，其设置于所述绝缘图案之上；
功率半导体芯片，其搭载于所述电路图案之上；以及
控制半导体芯片，其搭载于所述电路图案之上，并且对所述功率半导体芯片进行控制，
所述功率半导体芯片通过铜制的第一芯片键合材料与所述电路图案接合，
所述控制半导体芯片通过第二芯片键合材料与所述电路图案接合。
2.根据权利要求1所述的半导体装置，其中，
还具有电容性部件，该电容性部件搭载于所述电路图案之上且与所述功率半导体芯片电连接，
所述电容性部件通过铜制的第三芯片键合材料与所述电路图案接合。
3.根据权利要求1所述的半导体装置，其中，
所述金属板、所述绝缘图案和所述电路图案构成为一体。
4.根据权利要求2所述的半导体装置，其中，
所述第一芯片键合材料的厚度比所述第三芯片键合材料的厚度厚。
5.一种半导体装置的制造方法，其制造权利要求1所述的半导体装置，该半导体装置的制造方法具有：
工序(a)，在所述电路图案之上涂敷所述第一芯片键合材料的固化前的状态即第一糊状材料和所述第二芯片键合材料的固化前的状态即第二糊状材料；
工序(b)，将所述功率半导体芯片搭载于所述第一糊状材料之上，将所述控制半导体芯片搭载于所述第二糊状材料之上；以及
工序(c)，使所述第一糊状材料和所述第二糊状材料固化。
6.一种半导体装置的制造方法，其制造权利要求2所述的半导体装置，该半导体装置的制造方法具有：
工序(d)，在所述电路图案之上，将所述第二芯片键合材料的固化前的状态即第二糊状材料和所述第三芯片键合材料的固化前的状态即第三糊状材料涂敷得比所述第一芯片键合材料的固化前的状态即第一糊状材料的厚度薄；
工序(e)，在所述电路图案之上涂敷所述第一糊状材料；
工序(f)，将所述功率半导体芯片搭载于所述第一糊状材料之上，将所述控制半导体芯片搭载于所述第二糊状材料之上，将所述电容性部件搭载于所述第三糊状材料之上；以及
工序(g)，使所述第一糊状材料、所述第二糊状材料和所述第三糊状材料固化。
7.一种半导体装置的制造方法，其制造权利要求1所述的半导体装置，该半导体装置的制造方法具有：
工序(h)，在所述电路图案之上涂敷所述第二芯片键合材料的固化前的状态即第二糊状材料；
工序(i)，将所述控制半导体芯片搭载于所述第二糊状材料之上；
工序(j)，使所述第二糊状材料固化；
工序(k)，在所述电路图案之上涂敷所述第一芯片键合材料的固化前的状态即第一糊状材料；
工序(l)，将所述功率半导体芯片搭载于所述第一糊状材料之上；以及
工序(m)，使所述第一糊状材料固化，
所述第二糊状材料的固化温度低于所述第一糊状材料的固化温度。
8.根据权利要求5至7中任一项所述的半导体装置的制造方法，其中，
在所述工序(a)和所述工序(b)之间、所述工序(e)和所述工序(f)之间、或所述工序(k)和所述工序(l)之间还具有工序(n)，在该工序(n)中，以与所述第一糊状材料的内周部相比所述第一糊状材料的外周部向下方凹陷的方式进行所述第一糊状材料的成形。
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